| /device/linaro/bootloader/arm-trusted-firmware/include/lib/cpus/aarch32/ |
| cortex_a32.h | 17 #define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15
|
| cortex_a53.h | 25 #define CORTEX_A53_ECTLR p15, 1, c15
38 #define CORTEX_A53_MERRSR p15, 2, c15
43 #define CORTEX_A53_CPUACTLR p15, 0, c15
52 #define CORTEX_A53_L2ACTLR p15, 1, c15, c0, 0
60 #define CORTEX_A53_L2ECTLR p15, 1, c9, c0, 3
68 #define CORTEX_A53_L2MERRSR p15, 3, c15
|
| cortex_a72.h | 17 #define CORTEX_A72_ECTLR p15, 1, c15
27 #define CORTEX_A72_MERRSR p15, 2, c15
32 #define CORTEX_A72_CPUACTLR p15, 0, c15
42 #define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
54 #define CORTEX_A72_L2MERRSR p15, 3, c15
|
| cortex_a57.h | 26 #define CORTEX_A57_ECTLR p15, 1, c15
39 #define CORTEX_A57_CPUMERRSR p15, 2, c15
44 #define CORTEX_A57_CPUACTLR p15, 0, c15
60 #define CORTEX_A57_L2CTLR p15, 1, c9, c0, 2
71 #define CORTEX_A57_L2ECTLR p15, 1, c9, c0, 3
79 #define CORTEX_A57_L2MERRSR p15, 3, c15
|
| /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/ |
| arch.h | 386 #define SCR p15, 0, c1, c1, 0
387 #define SCTLR p15, 0, c1, c0, 0
388 #define SDCR p15, 0, c1, c3, 1
389 #define MPIDR p15, 0, c0, c0, 5
390 #define MIDR p15, 0, c0, c0, 0
391 #define VBAR p15, 0, c12, c0, 0
392 #define MVBAR p15, 0, c12, c0, 1
393 #define NSACR p15, 0, c1, c1, 2
394 #define CPACR p15, 0, c1, c0, 2
395 #define DCCIMVAC p15, 0, c7, c14,
[all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmCpuLib/ArmCortexA9Lib/ |
| ArmCortexA9Helper.S | 22 mrc p15, 4, r0, c15, c0, 0
|
| /device/linaro/bootloader/edk2/ArmPkg/Drivers/ArmGic/GicV3/Arm/ |
| ArmGicV3.S | 25 mrc p15, 0, r0, c12, c12, 5 // ICC_SRE
34 mcr p15, 0, r0, c12, c12, 5 // ICC_SRE
44 mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
53 mcr p15, 0, r0, c12, c12, 7 // ICC_IGRPEN1
61 mcr p15, 0, r0, c12, c12, 1 //ICC_EOIR1
69 mrc p15, 0, r0, c12, c8, 0 //ICC_IAR1
77 mcr p15, 0, r0, c4, c6, 0 //ICC_PMR
85 mcr p15, 0, r0, c12, c12, 3 //ICC_BPR1
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Arm/ |
| ArmLibSupport.S | 20 mrc p15,0,R0,c0,c0,0
24 mrc p15,0,R0,c0,c0,1
42 mcr p15,0,r0,c3,c0,0
63 mrc p15, 0, r0, c1, c0, 2
67 mcr p15, 0, r0, c1, c0, 2
72 mcr p15, 0, r0, c1, c0, 1
76 mrc p15, 0, r0, c1, c0, 1
80 mcr p15,0,r0,c2,c0,0
85 mcr p15, 0, r0, c2, c0, 2
90 mrc p15,0,r0,c2,c0,0
[all...] |
| ArmV7Support.S | 28 mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
32 mcr p15, 0, r0, c7, c10, 1 @clean single data cache line
37 mcr p15, 0, r0, c7, c11, 1 @clean single data cache line to PoU
41 mcr p15, 0, r0, c7, c5, 1 @Invalidate single instruction cache line to PoU
42 mcr p15, 0, r0, c7, c5, 7 @Invalidate branch predictor
46 mcr p15, 0, r0, c7, c14, 1 @clean and invalidate single data cache line
51 mcr p15, 0, r0, c7, c6, 2 @ Invalidate this line
56 mcr p15, 0, r0, c7, c14, 2 @ Clean and Invalidate this line
61 mcr p15, 0, r0, c7, c10, 2 @ Clean this line
65 mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
[all...] |
| ArmV7ArchTimerSupport.S | 19 mrc p15, 0, r0, c14, c0, 0 @ Read CNTFRQ
23 mcr p15, 0, r0, c14, c0, 0 @ Write to CNTFRQ
27 mrrc p15, 0, r0, r1, c14 @ Read CNTPT (Physical counter register)
31 mrc p15, 0, r0, c14, c1, 0 @ Read CNTK_CTL (Timer PL1 Control Register)
35 mcr p15, 0, r0, c14, c1, 0 @ Write to CNTK_CTL (Timer PL1 Control Register)
39 mrc p15, 0, r0, c14, c2, 0 @ Read CNTP_TVAL (PL1 physical timer value register)
43 mcr p15, 0, r0, c14, c2, 0 @ Write to CNTP_TVAL (PL1 physical timer value register)
47 mrc p15, 0, r0, c14, c2, 1 @ Read CNTP_CTL (PL1 Physical Timer Control Register)
51 mcr p15, 0, r0, c14, c2, 1 @ Write to CNTP_CTL (PL1 Physical Timer Control Register)
55 mrc p15, 0, r0, c14, c3, 0 @ Read CNTV_TVAL (Virtual Timer Value register)
[all...] |
| ArmV7Support.asm | 29 mcr p15, 0, r0, c7, c6, 1 ; invalidate single data cache line
33 mcr p15, 0, r0, c7, c10, 1 ; clean single data cache line
38 mcr p15, 0, r0, c7, c5, 1 ; invalidate single instruction cache line to PoU
39 mcr p15, 0, r0, c7, c5, 7 ; invalidate branch predictor
44 mcr p15, 0, r0, c7, c11, 1 ; clean single data cache line to PoU
49 mcr p15, 0, r0, c7, c14, 1 ; clean and invalidate single data cache line
54 mcr p15, 0, r0, c7, c6, 2 ; Invalidate this line
59 mcr p15, 0, r0, c7, c14, 2 ; Clean and Invalidate this line
64 mcr p15, 0, r0, c7, c10, 2 ; Clean this line
69 mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
[all...] |
| ArmLibSupportV7.S | 20 mrc p15,0,R0,c0,c0,5
74 mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
76 mrc p15,1,r0,c0,c0,0 @ Read current CP15 Cache Size ID Register (CCSIDR)
84 mrc p15,1,r0,c0,c0,1 @ Read CP15 Cache Level ID Register
88 mrc p15, 0, r0, c1, c1, 2
92 mcr p15, 0, r0, c1, c1, 2
|
| /external/arm-neon-tests/ |
| InitCache.s | 18 MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0
24 MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1
30 MRC p15, 0, r0, c1, c0, 1 ; Read Auxiliary Control Register
36 MCR p15, 0, r0, c1, c0, 1 ; Write Auxiliary Control Register
42 MRC p15, 0, r0, c1, c0, 0 ; read CP15 register 1 into r0
45 MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1
|
| Init.s | 33 MRC p15, 0, r0, c1, c0, 0 ; Read CP15 Control Register into r0
36 MCRNE p15, 0, r0, c1, c0, 0 ; Write value back
51 MCR p15, 0, r0, c8, c7, 0 ; Cortex-A8 I-TLB and D-TLB invalidation
59 MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR
62 MCRNE p15, 0, r0, c7, c5, 0 ; Invalidate Instruction Cache
66 MRC p15, 1, r0, c0, c0, 1 ; Read CLIDR
78 MCR p15, 2, r10, c0, c0, 0 ; Write the Cache Size selection register
80 MCR p15, 0, r1, c7, c5, 4 ; PrefetchFlush to sync the change to the CacheSizeID reg
81 MRC p15, 1, r1, c0, c0, 0 ; Reads current Cache Size ID register
94 MCR p15, 0, r11, c7, c14, 2 ; Clean and Invalidate by set/wa
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BaseLib/Ipf/ |
| PalCallStatic.s | 25 cmp.eq p15 = in0, r0
29 (p15) mov in0 = ar.k5
|
| /bionic/libc/arch-arm/bionic/ |
| vfork.S | 34 mrc p15, 0, r3, c13, c0, 3
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| reg-alias.s | 7 MMUCP .req p15
|
| armv8_2-a.s | 12 mrc p15, \Opc1,\() r0, \CRn\(), \CRm\(), \Opc2\()
14 mcr p15, \Opc1\(), r1, \CRn\(), \CRm\(), \Opc2\()
|
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmMmuLib/Arm/ |
| ArmMmuLibV7Support.S | 26 mrc p15,0,R0,c0,c0,5
32 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 Register
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/cris/ |
| rd-v32s-4.s | 20 move $r13,$p15
37 move $p15,$r13
54 move 13,$p15
71 move $p15,[$r13]
88 move [$r13],$p15
|
| /bionic/tests/math_data/ |
| fmod_intel_data.h | 71 0x1.0p15
81 0x1.0p15
110 0x1.0p15,
115 0x1.0p15,
130 0x1.0p15,
131 0x1.0p15
134 0x1.p15,
135 0x1.0p15,
141 0x1.0p15
149 0x1.p15,
[all...] |
| fmodf_intel_data.h | 46 0x1.p15
56 0x1.p15
85 0x1.p15,
90 0x1.p15,
105 0x1.p15,
106 0x1.p15
109 0x1.p15,
110 0x1.p15,
116 0x1.p15
124 0x1.p15,
[all...] |
| remainder_intel_data.h | 56 0x1.0p15
66 0x1.0p15
95 0x1.0p15,
100 0x1.0p15,
115 0x1.0p15,
116 0x1.0p15
119 0x1.p15,
120 0x1.0p15,
126 0x1.0p15
134 0x1.p15,
[all...] |
| remainderf_intel_data.h | 41 0x1.p15
51 0x1.p15
80 0x1.p15,
85 0x1.p15,
100 0x1.p15,
101 0x1.p15
104 0x1.p15,
105 0x1.p15,
111 0x1.p15
119 0x1.p15,
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/DebugSupportDxe/Ipf/ |
| AsmFuncs.s | 66 cmp.ltu p14,p15=r32, r31
298 cmp.eq p14, p15 = 0, in2;; // Check if done
350 cmp.ge p14, p15 = SLOT2, loc2;; // Check if maximum slot
351 (p15) br.sptk.few RelocateBundleDone
364 cmp.eq p14, p15 = 1, out0;; // Check if branch slot
365 (p15) add loc2=1,loc2 // Increment slot
366 (p15) br.sptk.few RelocateBundleNextSlot
371 cmp.eq p14, p15 = 1, out1;; // Check if relocated slot
372 (p15) mov in0=0 // in0 = failure
373 (p15) br.sptk.few RelocateBundleDone
[all...] |
