| /external/mesa3d/src/amd/vulkan/ |
| radv_util.h | 5 #define util_bitcount(i) __builtin_popcount(i) macro
8 util_bitcount(unsigned int n);
|
| si_cmd_buffer.c | 334 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
[all...] |
| /external/mesa3d/src/gallium/drivers/softpipe/ |
| sp_quad_fs.c | 78 util_bitcount(quad->inout.mask);
|
| sp_setup.c | 168 setup->numFragsEmitted += util_bitcount(quad->inout.mask);
243 setup->numFragsEmitted += util_bitcount(quadmask);
[all...] |
| /external/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| radv_amdgpu_winsys.c | 304 ws->info.sdma_rings = MIN2(util_bitcount(dma.available_rings),
306 ws->info.compute_rings = MIN2(util_bitcount(compute.available_rings),
314 util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
|
| /external/mesa3d/src/gallium/auxiliary/util/ |
| u_math.h | 481 util_bitcount(unsigned n) function
507 return util_bitcount(n) + util_bitcount(n >> 32);
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_state_emit.c | 128 *batch_space = 1 + util_bitcount(dirty);
204 int i, num = util_bitcount(dirty);
233 *batch_space = util_bitcount(i915->dynamic_dirty & ((1 << I915_MAX_DYNAMIC) - 1));
|
| /external/mesa3d/src/gallium/drivers/llvmpipe/ |
| lp_rast_tri_tmp.h | 131 LP_COUNT_ADD(nr_empty_4, util_bitcount(0xffff & ~(partial_mask | inmask)));
285 LP_COUNT_ADD(nr_empty_16, util_bitcount(0xffff & ~(partial_mask | inmask)));
|
| lp_setup_tri.c | 925 int count = util_bitcount(partial);
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| r600_streamout.c | 80 unsigned num_bufs = util_bitcount(rctx->streamout.enabled_mask);
81 unsigned num_bufs_appended = util_bitcount(rctx->streamout.enabled_mask &
|
| /external/mesa3d/src/gallium/state_trackers/clover/api/ |
| memory.cpp | 43 util_bitcount(d_flags & dev_access_flags) > 1 ||
44 util_bitcount(d_flags & host_access_flags) > 1)
|
| /external/mesa3d/src/amd/common/ |
| ac_debug.c | 119 util_bitcount(field->mask));
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir_util.cpp | 291 count += util_bitcount(data[i]);
|
| /external/mesa3d/src/gallium/drivers/freedreno/a3xx/ |
| fd3_program.c | 96 util_bitcount(rast->clip_plane_enable) > 6 ||
|
| fd3_emit.c | 583 MIN2(util_bitcount(planes), 6));
[all...] |
| /external/mesa3d/src/gallium/drivers/nouveau/nv50/ |
| nv50_screen.c | 958 screen->TPs = util_bitcount(value & 0xffff)
[all...] |
| nv50_shader_state.c | 318 unsigned n = util_bitcount(fp->in[i].mask);
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_shader_tgsi_setup.c | 502 lp_build_const_int32(gallivm, util_bitcount(array->writemask)),
508 util_bitcount(array->writemask & ((1 << swizzle) - 1))),
818 array_size = ((last - first) + 1) * util_bitcount(writemask);
[all...] |
| /external/mesa3d/src/gallium/winsys/amdgpu/drm/ |
| amdgpu_winsys.c | 351 util_bitcount(ws->amdinfo.cu_bitmap[i][j]);
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_state_common.c | 404 util_bitcount(state->dirty_mask & state->has_bordercolor_mask) * 11 +
405 util_bitcount(state->dirty_mask & ~state->has_bordercolor_mask) * 5;
539 util_bitcount(rctx->vertex_buffer_state.dirty_mask);
595 util_bitcount(state->dirty_mask);
[all...] |
| evergreen_compute.c | 509 rctx->cs_vertex_buffer_state.atom.num_dw = 12 * util_bitcount(rctx->cs_vertex_buffer_state.dirty_mask);
[all...] |
| /external/mesa3d/src/gallium/drivers/r300/ |
| r300_emit.c | [all...] |
| /external/mesa3d/src/compiler/nir/ |
| nir_validate.c | 943 validate_assert(state, util_bitcount(var->data.mode) == 1);
[all...] |
| /external/mesa3d/src/gallium/drivers/svga/ |
| svga_tgsi_vgpu10.c | [all...] |
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_exec.c | [all...] |
