| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neon-cmp-encoding.s | 3 vceq.i8 d16, d16, d17
4 vceq.i16 d16, d16, d17
5 vceq.i32 d16, d16, d17
6 vceq.f32 d16, d16, d17
7 vceq.i8 q8, q8, q9
8 vceq.i16 q8, q8, q9
9 vceq.i32 q8, q8, q9
10 vceq.f32 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
13 @ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3
[all...] |
| /external/arm-neon-tests/ |
| ref_vceq.c | 26 #define INSN_NAME vceq
27 #define TEST_MSG "VCEQ/VCEQQ"
29 /* Extra tests for _p8 variants, which exist only for vceq */
|
| Android.mk | 25 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| Makefile | 40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| /external/llvm/test/MC/ARM/ |
| neon-cmp-encoding.s | 3 vceq.i8 d16, d16, d17
4 vceq.i16 d16, d16, d17
5 vceq.i32 d16, d16, d17
6 vceq.f32 d16, d16, d17
7 vceq.i8 q8, q8, q9
8 vceq.i16 q8, q8, q9
9 vceq.i32 q8, q8, q9
10 vceq.f32 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
13 @ CHECK: vceq.i16 d16, d16, d17 @ encoding: [0xb1,0x08,0x50,0xf3
[all...] |
| fullfp16-neon-neg.s | 56 vceq.f16 d2, d3, d4
57 vceq.f16 q2, q3, q4
61 vceq.f16 d2, d3, #0
62 vceq.f16 q2, q3, #0
|
| fullfp16-neon.s | 74 vceq.f16 d2, d3, d4
75 vceq.f16 q2, q3, q4
76 @ ARM: vceq.f16 d2, d3, d4 @ encoding: [0x04,0x2e,0x13,0xf2]
77 @ ARM: vceq.f16 q2, q3, q4 @ encoding: [0x48,0x4e,0x16,0xf2]
78 @ THUMB: vceq.f16 d2, d3, d4 @ encoding: [0x13,0xef,0x04,0x2e]
79 @ THUMB: vceq.f16 q2, q3, q4 @ encoding: [0x16,0xef,0x48,0x4e]
81 vceq.f16 d2, d3, #0
82 vceq.f16 q2, q3, #0
83 @ ARM: vceq.f16 d2, d3, #0 @ encoding: [0x03,0x25,0xb5,0xf3]
84 @ ARM: vceq.f16 q2, q3, #0 @ encoding: [0x46,0x45,0xb5,0xf3
[all...] |
| neon-bitwise-encoding.s | 307 vceq.s16 q5, q3
308 vceq.s16 d5, d3
322 vceq.s16 q5, #0
323 vceq.s16 d5, #0
360 @ CHECK: vceq.i16 q5, q5, q3 @ encoding: [0x56,0xa8,0x1a,0xf3]
361 @ CHECK: vceq.i16 d5, d5, d3 @ encoding: [0x13,0x58,0x15,0xf3]
375 @ CHECK: vceq.i16 q5, q5, #0 @ encoding: [0x4a,0xa1,0xb5,0xf3]
376 @ CHECK: vceq.i16 d5, d5, #0 @ encoding: [0x05,0x51,0xb5,0xf3]
|
| /external/capstone/suite/MC/ARM/ |
| neon-cmp-encoding.s.cs | 2 0xb1,0x08,0x40,0xf3 = vceq.i8 d16, d16, d17
3 0xb1,0x08,0x50,0xf3 = vceq.i16 d16, d16, d17
4 0xb1,0x08,0x60,0xf3 = vceq.i32 d16, d16, d17
5 0xa1,0x0e,0x40,0xf2 = vceq.f32 d16, d16, d17
6 0xf2,0x08,0x40,0xf3 = vceq.i8 q8, q8, q9
7 0xf2,0x08,0x50,0xf3 = vceq.i16 q8, q8, q9
8 0xf2,0x08,0x60,0xf3 = vceq.i32 q8, q8, q9
9 0xe2,0x0e,0x40,0xf2 = vceq.f32 q8, q8, q9
48 0x20,0x01,0xf1,0xf3 = vceq.i8 d16, d16, #0
|
| neon-bitwise-encoding.s.cs | 109 0x56,0xa8,0x1a,0xf3 = vceq.i16 q5, q5, q3
110 0x13,0x58,0x15,0xf3 = vceq.i16 d5, d5, d3
119 0x4a,0xa1,0xb5,0xf3 = vceq.i16 q5, q5, #0
120 0x05,0x51,0xb5,0xf3 = vceq.i16 d5, d5, #0
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| neon-omit.s | 15 vceq.i16 q5,#0
16 vceq.i16 q5,q5
64 vceq.i16 q5,q3,#0
65 vceq.i16 q5,q3,q5
|
| armv8-2-fp16-simd.d | 39 6c: f2142e0e vceq.f16 d2, d4, d14
40 70: f2184e6c vceq.f16 q2, q4, q14
53 a4: f2100eec vceq.f16 q0, q8, q14
138 1f8: f3b5e502 vceq.f16 d14, d2, #0
139 1fc: f3f5c544 vceq.f16 q14, q2, #0
|
| neon-omit.d | 16 0[0-9a-f]+ <[^>]+> f3b5a14a vceq\.i16 q5, q5, #0
17 0[0-9a-f]+ <[^>]+> f31aa85a vceq\.i16 q5, q5, q5
62 0[0-9a-f]+ <[^>]+> f3b5a146 vceq\.i16 q5, q3, #0
63 0[0-9a-f]+ <[^>]+> f316a85a vceq\.i16 q5, q3, q5
|
| armv8-2-fp16-simd-thumb.d | 39 6c: ef14 2e0e vceq.f16 d2, d4, d14
40 70: ef18 4e6c vceq.f16 q2, q4, q14
53 a4: ef10 0eec vceq.f16 q0, q8, q14
138 1f8: ffb5 e502 vceq.f16 d14, d2, #0
139 1fc: fff5 c544 vceq.f16 q14, q2, #0
|
| armv8-2-fp16-simd.s | 28 .irp op, vacge.f16, vacgt.f16, vaclt.f16, vacle.f16, vceq.f16, vcge.f16, vcgt.f16, vcle.f16, vclt.f16
35 .irp op, vceq.f16, vcge.f16, vcgt.f16, vcle.f16, vclt.f16
|
| neon-cov.d | [all...] |
| armv8-2-fp16-simd-warning.l | 29 [^:]*:175: Error: selected processor does not support fp16 instruction -- `vceq.f16 d2,d4,d14'
30 [^:]*:175: Error: selected processor does not support fp16 instruction -- `vceq.f16 q2,q4,q14'
128 [^:]*:224: Error: selected processor does not support fp16 instruction -- `vceq.f16 d14,d2,#0'
129 [^:]*:224: Error: selected processor does not support fp16 instruction -- `vceq.f16 q14,q2,#0'
|
| neon-cov.s | 192 regs3_if_32 vceq vceqq
215 regs2i_if_0 vceq vceqq
|
| /external/libavc/common/arm/ |
| ih264_resi_trans_quant_a9.s | 215 vceq.s16 q5, q15, #0 @I compare with zero row 1 and 2 blk 1
216 vceq.s16 q6, q0 , #0 @I compare with zero row 1 and 2 blk 1
410 vceq.s16 q5, q15, #0 @I compare with zero row 1 and 2 blk 1
411 vceq.s16 q6, q0 , #0 @I compare with zero row 1 and 2 blk 1
557 vceq.s16 q5, q11, #0
558 vceq.s16 q6, q12, #0
673 vceq.s16 q7, q4, #0 @Compute nnz
|
| /external/valgrind/none/tests/arm/ |
| neon128.stdout.exp | [all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc | 52 M(vceq) \
210 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vceq-a32.h"
|
| test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc | 52 M(vceq) \
210 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vceq-t32.h"
|
| /external/v8/src/compiler/arm/ |
| code-generator-arm.cc | [all...] |
| /external/libjpeg-turbo/simd/ |
| jsimd_arm_neon.S | [all...] |
| /external/vixl/src/aarch32/ |
| assembler-aarch32.h | 3996 void vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { function in class:vixl::aarch32::Assembler
4005 void vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { function in class:vixl::aarch32::Assembler
4011 void vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
4017 void vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
[all...] |
