1 @ Neon tests. Basic bitfield tests, using zero for as many registers/fields as 2 @ possible, but without causing instructions to be badly-formed. 3 4 .arm 5 .syntax unified 6 .text 7 8 .macro regs3_1 op opq vtype 9 \op\vtype q0,q0,q0 10 \opq\vtype q0,q0,q0 11 \op\vtype d0,d0,d0 12 .endm 13 14 .macro dregs3_1 op vtype 15 \op\vtype d0,d0,d0 16 .endm 17 18 .macro regn3_1 op operand2 vtype 19 \op\vtype d0,q0,\operand2 20 .endm 21 22 .macro regl3_1 op operand2 vtype 23 \op\vtype q0,d0,\operand2 24 .endm 25 26 .macro regw3_1 op operand2 vtype 27 \op\vtype q0,q0,\operand2 28 .endm 29 30 .macro regs2_1 op opq vtype 31 \op\vtype q0,q0 32 \opq\vtype q0,q0 33 \op\vtype d0,d0 34 .endm 35 36 .macro regs3_su_32 op opq 37 regs3_1 \op \opq .s8 38 regs3_1 \op \opq .s16 39 regs3_1 \op \opq .s32 40 regs3_1 \op \opq .u8 41 regs3_1 \op \opq .u16 42 regs3_1 \op \opq .u32 43 .endm 44 45 regs3_su_32 vaba vabaq 46 regs3_su_32 vhadd vhaddq 47 regs3_su_32 vrhadd vrhaddq 48 regs3_su_32 vhsub vhsubq 49 50 .macro regs3_su_64 op opq 51 regs3_1 \op \opq .s8 52 regs3_1 \op \opq .s16 53 regs3_1 \op \opq .s32 54 regs3_1 \op \opq .s64 55 regs3_1 \op \opq .u8 56 regs3_1 \op \opq .u16 57 regs3_1 \op \opq .u32 58 regs3_1 \op \opq .u64 59 .endm 60 61 regs3_su_64 vqadd vqaddq 62 regs3_su_64 vqsub vqsubq 63 regs3_su_64 vrshl vrshlq 64 regs3_su_64 vqrshl vqrshlq 65 66 regs3_su_64 vshl vshlq 67 regs3_su_64 vqshl vqshlq 68 69 .macro regs2i_1 op opq imm vtype 70 \op\vtype q0,q0,\imm 71 \opq\vtype q0,q0,\imm 72 \op\vtype d0,d0,\imm 73 .endm 74 75 .macro regs2i_su_64 op opq imm 76 regs2i_1 \op \opq \imm .s8 77 regs2i_1 \op \opq \imm .s16 78 regs2i_1 \op \opq \imm .s32 79 regs2i_1 \op \opq \imm .s64 80 regs2i_1 \op \opq \imm .u8 81 regs2i_1 \op \opq \imm .u16 82 regs2i_1 \op \opq \imm .u32 83 regs2i_1 \op \opq \imm .u64 84 .endm 85 86 .macro regs2i_i_64 op opq imm 87 regs2i_1 \op \opq \imm .i8 88 regs2i_1 \op \opq \imm .i16 89 regs2i_1 \op \opq \imm .i32 90 regs2i_1 \op \opq \imm .s32 91 regs2i_1 \op \opq \imm .u32 92 regs2i_1 \op \opq \imm .i64 93 .endm 94 95 regs2i_i_64 vshl vshlq 0 96 regs2i_su_64 vqshl vqshlq 0 97 98 .macro regs3_ntyp op opq 99 regs3_1 \op \opq .8 100 .endm 101 102 regs3_ntyp vand vandq 103 regs3_ntyp vbic vbicq 104 regs3_ntyp vorr vorrq 105 regs3_ntyp vorn vornq 106 regs3_ntyp veor veorq 107 108 .macro logic_imm_1 op opq imm vtype 109 \op\vtype q0,\imm 110 \opq\vtype q0,\imm 111 \op\vtype d0,\imm 112 .endm 113 114 .macro logic_imm op opq 115 logic_imm_1 \op \opq 0x000000a5000000a5 .i64 116 logic_imm_1 \op \opq 0x0000a5000000a500 .i64 117 logic_imm_1 \op \opq 0x00a5000000a50000 .i64 118 logic_imm_1 \op \opq 0xa5000000a5000000 .i64 119 logic_imm_1 \op \opq 0x00a500a500a500a5 .i64 120 logic_imm_1 \op \opq 0xa500a500a500a500 .i64 121 logic_imm_1 \op \opq 0x000000ff .i32 122 logic_imm_1 \op \opq 0x000000ff .s32 123 logic_imm_1 \op \opq 0x000000ff .u32 124 logic_imm_1 \op \opq 0x0000ff00 .i32 125 logic_imm_1 \op \opq 0x00ff0000 .i32 126 logic_imm_1 \op \opq 0xff000000 .i32 127 logic_imm_1 \op \opq 0x00a500a5 .i32 128 logic_imm_1 \op \opq 0xa500a500 .i32 129 logic_imm_1 \op \opq 0x00ff .i16 130 logic_imm_1 \op \opq 0xff00 .i16 131 logic_imm_1 \op \opq 0x00 .i8 132 .endm 133 134 logic_imm vbic vbicq 135 logic_imm vorr vorrq 136 137 .macro logic_inv_imm op opq 138 logic_imm_1 \op \opq 0xffffff5affffff5a .i64 139 logic_imm_1 \op \opq 0xffff5affffff5aff .i64 140 logic_imm_1 \op \opq 0xff5affffff5affff .i64 141 logic_imm_1 \op \opq 0x5affffff5affffff .i64 142 logic_imm_1 \op \opq 0xff5aff5aff5aff5a .i64 143 logic_imm_1 \op \opq 0x5aff5aff5aff5aff .i64 144 logic_imm_1 \op \opq 0xffffff00 .i32 145 logic_imm_1 \op \opq 0xffffff00 .s32 146 logic_imm_1 \op \opq 0xffffff00 .u32 147 logic_imm_1 \op \opq 0xffff00ff .i32 148 logic_imm_1 \op \opq 0xff00ffff .i32 149 logic_imm_1 \op \opq 0x00ffffff .i32 150 logic_imm_1 \op \opq 0xff5aff5a .i32 151 logic_imm_1 \op \opq 0x5aff5aff .i32 152 logic_imm_1 \op \opq 0xff00 .i16 153 logic_imm_1 \op \opq 0x00ff .i16 154 logic_imm_1 \op \opq 0xff .i8 155 .endm 156 157 logic_inv_imm vand vandq 158 logic_inv_imm vorn vornq 159 160 regs3_ntyp vbsl vbslq 161 regs3_ntyp vbit vbitq 162 regs3_ntyp vbif vbifq 163 164 .macro regs3_suf_32 op opq 165 regs3_1 \op \opq .s8 166 regs3_1 \op \opq .s16 167 regs3_1 \op \opq .s32 168 regs3_1 \op \opq .u8 169 regs3_1 \op \opq .u16 170 regs3_1 \op \opq .u32 171 regs3_1 \op \opq .f32 172 .endm 173 174 .macro regs3_if_32 op opq 175 regs3_1 \op \opq .i8 176 regs3_1 \op \opq .i16 177 regs3_1 \op \opq .i32 178 regs3_1 \op \opq .s32 179 regs3_1 \op \opq .u32 180 regs3_1 \op \opq .f32 181 .endm 182 183 regs3_suf_32 vabd vabdq 184 regs3_suf_32 vmax vmaxq 185 regs3_suf_32 vmin vminq 186 187 regs3_suf_32 vcge vcgeq 188 regs3_suf_32 vcgt vcgtq 189 regs3_suf_32 vcle vcleq 190 regs3_suf_32 vclt vcltq 191 192 regs3_if_32 vceq vceqq 193 194 .macro regs2i_sf_0 op opq 195 regs2i_1 \op \opq 0 .s8 196 regs2i_1 \op \opq 0 .s16 197 regs2i_1 \op \opq 0 .s32 198 regs2i_1 \op \opq 0 .f32 199 .endm 200 201 regs2i_sf_0 vcge vcgeq 202 regs2i_sf_0 vcgt vcgtq 203 regs2i_sf_0 vcle vcleq 204 regs2i_sf_0 vclt vcltq 205 206 .macro regs2i_if_0 op opq 207 regs2i_1 \op \opq 0 .i8 208 regs2i_1 \op \opq 0 .i16 209 regs2i_1 \op \opq 0 .i32 210 regs2i_1 \op \opq 0 .s32 211 regs2i_1 \op \opq 0 .u32 212 regs2i_1 \op \opq 0 .f32 213 .endm 214 215 regs2i_if_0 vceq vceqq 216 217 .macro dregs3_suf_32 op 218 dregs3_1 \op .s8 219 dregs3_1 \op .s16 220 dregs3_1 \op .s32 221 dregs3_1 \op .u8 222 dregs3_1 \op .u16 223 dregs3_1 \op .u32 224 dregs3_1 \op .f32 225 .endm 226 227 dregs3_suf_32 vpmax 228 dregs3_suf_32 vpmin 229 230 .macro sregs3_1 op opq vtype 231 \op\vtype q0,q0,q0 232 \opq\vtype q0,q0,q0 233 \op\vtype d0,d0,d0 234 .endm 235 236 .macro sclr21_1 op opq vtype 237 \op\vtype q0,q0,d0[0] 238 \opq\vtype q0,q0,d0[0] 239 \op\vtype d0,d0,d0[0] 240 .endm 241 242 .macro mul_incl_scalar op opq 243 regs3_1 \op \opq .i8 244 regs3_1 \op \opq .i16 245 regs3_1 \op \opq .i32 246 regs3_1 \op \opq .s32 247 regs3_1 \op \opq .u32 248 regs3_1 \op \opq .f32 249 sclr21_1 \op \opq .i16 250 sclr21_1 \op \opq .i32 251 sclr21_1 \op \opq .s32 252 sclr21_1 \op \opq .u32 253 sclr21_1 \op \opq .f32 254 .endm 255 256 mul_incl_scalar vmla vmlaq 257 mul_incl_scalar vmls vmlsq 258 259 .macro dregs3_if_32 op 260 dregs3_1 \op .i8 261 dregs3_1 \op .i16 262 dregs3_1 \op .i32 263 dregs3_1 \op .s32 264 dregs3_1 \op .u32 265 dregs3_1 \op .f32 266 .endm 267 268 dregs3_if_32 vpadd 269 270 .macro regs3_if_64 op opq 271 regs3_1 \op \opq .i8 272 regs3_1 \op \opq .i16 273 regs3_1 \op \opq .i32 274 regs3_1 \op \opq .s32 275 regs3_1 \op \opq .u32 276 regs3_1 \op \opq .i64 277 regs3_1 \op \opq .f32 278 .endm 279 280 regs3_if_64 vadd vaddq 281 regs3_if_64 vsub vsubq 282 283 .macro regs3_sz_32 op opq 284 regs3_1 \op \opq .8 285 regs3_1 \op \opq .16 286 regs3_1 \op \opq .32 287 .endm 288 289 regs3_sz_32 vtst vtstq 290 291 .macro regs3_ifp_32 op opq 292 regs3_1 \op \opq .i8 293 regs3_1 \op \opq .i16 294 regs3_1 \op \opq .i32 295 regs3_1 \op \opq .s32 296 regs3_1 \op \opq .u32 297 regs3_1 \op \opq .f32 298 regs3_1 \op \opq .p8 299 .endm 300 301 regs3_ifp_32 vmul vmulq 302 303 .macro dqmulhs op opq 304 regs3_1 \op \opq .s16 305 regs3_1 \op \opq .s32 306 sclr21_1 \op \opq .s16 307 sclr21_1 \op \opq .s32 308 .endm 309 310 dqmulhs vqdmulh vqdmulhq 311 dqmulhs vqrdmulh vqrdmulhq 312 313 regs3_1 vacge vacgeq .f32 314 regs3_1 vacgt vacgtq .f32 315 regs3_1 vacle vacleq .f32 316 regs3_1 vaclt vacltq .f32 317 regs3_1 vrecps vrecpsq .f32 318 regs3_1 vrsqrts vrsqrtsq .f32 319 320 .macro regs2_sf_32 op opq 321 regs2_1 \op \opq .s8 322 regs2_1 \op \opq .s16 323 regs2_1 \op \opq .s32 324 regs2_1 \op \opq .f32 325 .endm 326 327 regs2_sf_32 vabs vabsq 328 regs2_sf_32 vneg vnegq 329 330 .macro rshift_imm op opq 331 regs2i_1 \op \opq 7 .s8 332 regs2i_1 \op \opq 15 .s16 333 regs2i_1 \op \opq 31 .s32 334 regs2i_1 \op \opq 63 .s64 335 regs2i_1 \op \opq 7 .u8 336 regs2i_1 \op \opq 15 .u16 337 regs2i_1 \op \opq 31 .u32 338 regs2i_1 \op \opq 63 .u64 339 .endm 340 341 rshift_imm vshr vshrq 342 rshift_imm vrshr vrshrq 343 rshift_imm vsra vsraq 344 rshift_imm vrsra vrsraq 345 346 regs2i_1 vsli vsliq 0 .8 347 regs2i_1 vsli vsliq 0 .16 348 regs2i_1 vsli vsliq 0 .32 349 regs2i_1 vsli vsliq 0 .64 350 351 regs2i_1 vsri vsriq 7 .8 352 regs2i_1 vsri vsriq 15 .16 353 regs2i_1 vsri vsriq 31 .32 354 regs2i_1 vsri vsriq 63 .64 355 356 regs2i_1 vqshlu vqshluq 0 .s8 357 regs2i_1 vqshlu vqshluq 0 .s16 358 regs2i_1 vqshlu vqshluq 0 .s32 359 regs2i_1 vqshlu vqshluq 0 .s64 360 361 .macro qrshift_imm op 362 regn3_1 \op 7 .s16 363 regn3_1 \op 15 .s32 364 regn3_1 \op 31 .s64 365 regn3_1 \op 7 .u16 366 regn3_1 \op 15 .u32 367 regn3_1 \op 31 .u64 368 .endm 369 370 .macro qrshiftu_imm op 371 regn3_1 \op 7 .s16 372 regn3_1 \op 15 .s32 373 regn3_1 \op 31 .s64 374 .endm 375 376 .macro qrshifti_imm op 377 regn3_1 \op 7 .i16 378 regn3_1 \op 15 .i32 379 regn3_1 \op 15 .s32 380 regn3_1 \op 15 .u32 381 regn3_1 \op 31 .i64 382 .endm 383 384 qrshift_imm vqshrn 385 qrshift_imm vqrshrn 386 qrshiftu_imm vqshrun 387 qrshiftu_imm vqrshrun 388 389 qrshifti_imm vshrn 390 qrshifti_imm vrshrn 391 392 regl3_1 vshll 1 .s8 393 regl3_1 vshll 1 .s16 394 regl3_1 vshll 1 .s32 395 regl3_1 vshll 1 .u8 396 regl3_1 vshll 1 .u16 397 regl3_1 vshll 1 .u32 398 399 regl3_1 vshll 8 .i8 400 regl3_1 vshll 16 .i16 401 regl3_1 vshll 32 .i32 402 regl3_1 vshll 32 .s32 403 regl3_1 vshll 32 .u32 404 405 .macro convert op opr arg="" t1=".s32.f32" t2=".u32.f32" t3=".f32.s32" t4=".f32.u32" 406 \op\t1 \opr,\opr\arg 407 \op\t2 \opr,\opr\arg 408 \op\t3 \opr,\opr\arg 409 \op\t4 \opr,\opr\arg 410 .endm 411 412 convert vcvt q0 413 convert vcvtq q0 414 convert vcvt d0 415 convert vcvt q0 ",1" 416 convert vcvtq q0 ",1" 417 convert vcvt d0 ",1" 418 419 vmov q0,q0 420 vmov d0,d0 421 vmov.8 d0[0],r0 422 vmov.16 d0[0],r0 423 vmov.32 d0[0],r0 424 vmov d0,r0,r0 425 vmov.s8 r0,d0[0] 426 vmov.s16 r0,d0[0] 427 vmov.u8 r0,d0[0] 428 vmov.u16 r0,d0[0] 429 vmov.32 r0,d0[0] 430 vmov r0,r1,d0 431 432 .macro mov_imm op imm vtype 433 \op\vtype q0,\imm 434 \op\vtype d0,\imm 435 .endm 436 437 mov_imm vmov 0x00000077 .i32 438 mov_imm vmov 0x00000077 .s32 439 mov_imm vmov 0x00000077 .u32 440 mov_imm vmvn 0x00000077 .i32 441 mov_imm vmvn 0x00000077 .s32 442 mov_imm vmvn 0x00000077 .u32 443 mov_imm vmov 0x00007700 .i32 444 mov_imm vmvn 0x00007700 .i32 445 mov_imm vmov 0x00770000 .i32 446 mov_imm vmvn 0x00770000 .i32 447 mov_imm vmov 0x77000000 .i32 448 mov_imm vmvn 0x77000000 .i32 449 mov_imm vmov 0x0077 .i16 450 mov_imm vmvn 0x0077 .i16 451 mov_imm vmov 0x7700 .i16 452 mov_imm vmvn 0x7700 .i16 453 mov_imm vmov 0x000077ff .i32 454 mov_imm vmvn 0x000077ff .i32 455 mov_imm vmov 0x0077ffff .i32 456 mov_imm vmvn 0x0077ffff .i32 457 mov_imm vmov 0x77 .i8 458 mov_imm vmov 0xff0000ff000000ff .i64 459 mov_imm vmov 4.25 .f32 460 461 mov_imm vmov 0xa5a5 .i16 462 mov_imm vmvn 0xa5a5 .i16 463 mov_imm vmov 0xa5a5a5a5 .i32 464 mov_imm vmvn 0xa5a5a5a5 .i32 465 mov_imm vmov 0x00a500a5 .i32 466 mov_imm vmov 0xa500a500 .i32 467 mov_imm vmov 0xa5a5a5a5a5a5a5a5 .i64 468 mov_imm vmvn 0xa5a5a5a5a5a5a5a5 .i64 469 mov_imm vmov 0x00a500a500a500a5 .i64 470 mov_imm vmov 0xa500a500a500a500 .i64 471 mov_imm vmov 0x000000a5000000a5 .i64 472 mov_imm vmov 0x0000a5000000a500 .i64 473 mov_imm vmov 0x00a5000000a50000 .i64 474 mov_imm vmov 0xa5000000a5000000 .i64 475 mov_imm vmov 0x0000a5ff0000a5ff .i64 476 mov_imm vmov 0x00a5ffff00a5ffff .i64 477 mov_imm vmov 0xa5ffffffa5ffffff .i64 478 479 vmvn q0,q0 480 vmvnq q0,q0 481 vmvn d0,d0 482 483 .macro long_ops op 484 regl3_1 \op d0 .s8 485 regl3_1 \op d0 .s16 486 regl3_1 \op d0 .s32 487 regl3_1 \op d0 .u8 488 regl3_1 \op d0 .u16 489 regl3_1 \op d0 .u32 490 .endm 491 492 long_ops vabal 493 long_ops vabdl 494 long_ops vaddl 495 long_ops vsubl 496 497 .macro long_mac op 498 regl3_1 \op d0 .s8 499 regl3_1 \op d0 .s16 500 regl3_1 \op d0 .s32 501 regl3_1 \op d0 .u8 502 regl3_1 \op d0 .u16 503 regl3_1 \op d0 .u32 504 regl3_1 \op "d0[0]" .s16 505 regl3_1 \op "d0[0]" .s32 506 regl3_1 \op "d0[0]" .u16 507 regl3_1 \op "d0[0]" .u32 508 .endm 509 510 long_mac vmlal 511 long_mac vmlsl 512 513 .macro wide_ops op 514 regw3_1 \op d0 .s8 515 regw3_1 \op d0 .s16 516 regw3_1 \op d0 .s32 517 regw3_1 \op d0 .u8 518 regw3_1 \op d0 .u16 519 regw3_1 \op d0 .u32 520 .endm 521 522 wide_ops vaddw 523 wide_ops vsubw 524 525 .macro narr_ops op 526 regn3_1 \op q0 .i16 527 regn3_1 \op q0 .i32 528 regn3_1 \op q0 .s32 529 regn3_1 \op q0 .u32 530 regn3_1 \op q0 .i64 531 .endm 532 533 narr_ops vaddhn 534 narr_ops vraddhn 535 narr_ops vsubhn 536 narr_ops vrsubhn 537 538 .macro long_dmac op 539 regl3_1 \op d0 .s16 540 regl3_1 \op d0 .s32 541 regl3_1 \op "d0[0]" .s16 542 regl3_1 \op "d0[0]" .s32 543 .endm 544 545 long_dmac vqdmlal 546 long_dmac vqdmlsl 547 long_dmac vqdmull 548 549 regl3_1 vmull d0 .s8 550 regl3_1 vmull d0 .s16 551 regl3_1 vmull d0 .s32 552 regl3_1 vmull d0 .u8 553 regl3_1 vmull d0 .u16 554 regl3_1 vmull d0 .u32 555 regl3_1 vmull d0 .p8 556 regl3_1 vmull "d0[0]" .s16 557 regl3_1 vmull "d0[0]" .s32 558 regl3_1 vmull "d0[0]" .u16 559 regl3_1 vmull "d0[0]" .u32 560 561 vext.8 q0,q0,q0,0 562 vextq.8 q0,q0,q0,0 563 vext.8 d0,d0,d0,0 564 vext.8 q0,q0,q0,8 565 566 .macro revs op opq vtype 567 \op\vtype q0,q0 568 \opq\vtype q0,q0 569 \op\vtype d0,d0 570 .endm 571 572 revs vrev64 vrev64q .8 573 revs vrev64 vrev64q .16 574 revs vrev64 vrev64q .32 575 revs vrev32 vrev32q .8 576 revs vrev32 vrev32q .16 577 revs vrev16 vrev16q .8 578 579 .macro dups op opq vtype 580 \op\vtype q0,r0 581 \opq\vtype q0,r0 582 \op\vtype d0,r0 583 \op\vtype q0,d0[0] 584 \opq\vtype q0,d0[0] 585 \op\vtype d0,d0[0] 586 .endm 587 588 dups vdup vdupq .8 589 dups vdup vdupq .16 590 dups vdup vdupq .32 591 592 .macro binop_3typ op op1 op2 t1 t2 t3 593 \op\t1 \op1,\op2 594 \op\t2 \op1,\op2 595 \op\t3 \op1,\op2 596 .endm 597 598 binop_3typ vmovl q0 d0 .s8 .s16 .s32 599 binop_3typ vmovl q0 d0 .u8 .u16 .u32 600 binop_3typ vmovn d0 q0 .i16 .i32 .i64 601 vmovn.s32 d0, q0 602 vmovn.u32 d0, q0 603 binop_3typ vqmovn d0 q0 .s16 .s32 .s64 604 binop_3typ vqmovn d0 q0 .u16 .u32 .u64 605 binop_3typ vqmovun d0 q0 .s16 .s32 .s64 606 607 .macro binops op opq vtype="" rhs="0" 608 \op\vtype q0,q\rhs 609 \opq\vtype q0,q\rhs 610 \op\vtype d0,d\rhs 611 .endm 612 613 .macro regs2_sz_32 op opq 614 binops \op \opq .8 1 615 binops \op \opq .16 1 616 binops \op \opq .32 1 617 .endm 618 619 regs2_sz_32 vzip vzipq 620 regs2_sz_32 vuzp vuzpq 621 622 .macro regs2_s_32 op opq 623 binops \op \opq .s8 624 binops \op \opq .s16 625 binops \op \opq .s32 626 .endm 627 628 regs2_s_32 vqabs vqabsq 629 regs2_s_32 vqneg vqnegq 630 631 .macro regs2_su_32 op opq 632 regs2_s_32 \op \opq 633 binops \op \opq .u8 634 binops \op \opq .u16 635 binops \op \opq .u32 636 .endm 637 638 regs2_su_32 vpadal vpadalq 639 regs2_su_32 vpaddl vpaddlq 640 641 binops vrecpe vrecpeq .u32 642 binops vrecpe vrecpeq .f32 643 binops vrsqrte vrsqrteq .u32 644 binops vrsqrte vrsqrteq .f32 645 646 regs2_s_32 vcls vclsq 647 648 .macro regs2_i_32 op opq 649 binops \op \opq .i8 650 binops \op \opq .i16 651 binops \op \opq .i32 652 binops \op \opq .s32 653 binops \op \opq .u32 654 .endm 655 656 regs2_i_32 vclz vclzq 657 658 binops vcnt vcntq .8 659 660 binops vswp vswpq "" 1 661 662 regs2_sz_32 vtrn vtrnq 663 664 vtbl.8 d0,{d0},d0 665 vtbx.8 d0,{d0},d0 666 667
