| /external/arm-neon-tests/ |
| ref_vcle.c | 26 #define INSN_NAME vcle
27 #define TEST_MSG "VCLE/VCLEQ"
|
| Android.mk | 25 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| Makefile | 40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| /external/llvm/test/MC/ARM/ |
| neon-cmp-encoding.s | 105 vcle.s8 d16, d16, #0
111 @ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3]
148 vcle.s8 d16, d16, d17
149 vcle.s16 d16, d16, d17
150 vcle.s32 d16, d16, d17
151 vcle.u8 d16, d16, d17
152 vcle.u16 d16, d16, d17
153 vcle.u32 d16, d16, d17
154 vcle.f32 d16, d16, d17
155 vcle.s8 q8, q8, q
[all...] |
| fullfp16-neon-neg.s | 86 vcle.f16 d2, d3, d4
87 vcle.f16 q2, q3, q4
91 vcle.f16 d2, d3, #0
92 vcle.f16 q2, q3, #0
|
| fullfp16-neon.s | 116 vcle.f16 d2, d3, d4
117 vcle.f16 q2, q3, q4
123 vcle.f16 d2, d3, #0
124 vcle.f16 q2, q3, #0
125 @ ARM: vcle.f16 d2, d3, #0 @ encoding: [0x83,0x25,0xb5,0xf3]
126 @ ARM: vcle.f16 q2, q3, #0 @ encoding: [0xc6,0x45,0xb5,0xf3]
127 @ THUMB: vcle.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x83,0x25]
128 @ THUMB: vcle.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0xc6,0x45]
|
| neon-bitwise-encoding.s | 325 vcle.s16 q5, #0
326 vcle.s16 d5, #0
378 @ CHECK: vcle.s16 q5, q5, #0 @ encoding: [0xca,0xa1,0xb5,0xf3]
379 @ CHECK: vcle.s16 d5, d5, #0 @ encoding: [0x85,0x51,0xb5,0xf3]
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| neon-omit.s | 40 vcle.u32 q7,q8
85 vcle.u32 q7,q8,q3
|
| armv8-2-fp16-simd.s | 28 .irp op, vacge.f16, vacgt.f16, vaclt.f16, vacle.f16, vceq.f16, vcge.f16, vcgt.f16, vcle.f16, vclt.f16
35 .irp op, vceq.f16, vcge.f16, vcgt.f16, vcle.f16, vclt.f16
|
| armv8-2-fp16-simd-warning.l | 35 [^:]*:175: Error: selected processor does not support fp16 instruction -- `vcle.f16 d2,d4,d14'
36 [^:]*:175: Error: selected processor does not support fp16 instruction -- `vcle.f16 q2,q4,q14'
134 [^:]*:224: Error: selected processor does not support fp16 instruction -- `vcle.f16 d14,d2,#0'
135 [^:]*:224: Error: selected processor does not support fp16 instruction -- `vcle.f16 q14,q2,#0'
|
| armv8-2-fp16-simd.d | 144 210: f3b5e582 vcle.f16 d14, d2, #0
145 214: f3f5c5c4 vcle.f16 q14, q2, #0
|
| armv8-2-fp16-simd-thumb.d | 144 210: ffb5 e582 vcle.f16 d14, d2, #0
145 214: fff5 c5c4 vcle.f16 q14, q2, #0
|
| neon-cov.s | 189 regs3_suf_32 vcle vcleq
203 regs2i_sf_0 vcle vcleq
|
| neon-cov.d | [all...] |
| /external/libpng/arm/ |
| filter_neon.S | 182 vcle.u16 q12, q13, q14 @ pa <= pb
183 vcle.u16 q13, q13, q15 @ pa <= pc
184 vcle.u16 q14, q14, q15 @ pb <= pc
|
| /external/pdfium/third_party/libpng16/arm/ |
| filter_neon.S | 182 vcle.u16 q12, q13, q14 @ pa <= pb
183 vcle.u16 q13, q13, q15 @ pa <= pc
184 vcle.u16 q14, q14, q15 @ pb <= pc
|
| /external/capstone/suite/MC/ARM/ |
| neon-bitwise-encoding.s.cs | 121 0xca,0xa1,0xb5,0xf3 = vcle.s16 q5, q5, #0
122 0x85,0x51,0xb5,0xf3 = vcle.s16 d5, d5, #0
|
| neon-cmp-encoding.s.cs | 50 0xa0,0x01,0xf1,0xf3 = vcle.s8 d16, d16, #0
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neon-cmp-encoding.s | 105 vcle.s8 d16, d16, #0
111 @ CHECK: vcle.s8 d16, d16, #0 @ encoding: [0xa0,0x01,0xf1,0xf3]
|
| /external/vixl/test/aarch32/ |
| test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc | 57 M(vcle) \
213 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vcle-a32.h"
|
| test-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc | 57 M(vcle) \
213 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vcle-t32.h"
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| loopfilter_neon.c | 89 *mask = vcle##r##u8(*mask, limit); \
90 t0 = vcle##r##u8(t0, blimit); \
116 *flat = vcle##r##u8(*flat, vdup##r##n_u8(1)); /* flat_mask4() */ \
142 flat2 = vcle##r##u8(flat2, vdup##r##n_u8(1)); \
[all...] |
| /external/valgrind/none/tests/arm/ |
| neon128.stdout.exp | [all...] |
| /external/vixl/src/aarch32/ |
| assembler-aarch32.h | 4086 void vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { function in class:vixl::aarch32::Assembler
4095 void vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { function in class:vixl::aarch32::Assembler
4101 void vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
4107 void vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.h | [all...] |
