| /external/capstone/suite/MC/ARM/ |
| neon-reciprocal-encoding.s.cs | 6 0xb1,0x0f,0x40,0xf2 = vrecps.f32 d16, d16, d17
7 0xf2,0x0f,0x40,0xf2 = vrecps.f32 q8, q8, q9
|
| neont2-reciprocal-encoding.s.cs | 6 0x40,0xef,0xb1,0x0f = vrecps.f32 d16, d16, d17
7 0x40,0xef,0xf2,0x0f = vrecps.f32 q8, q8, q9
|
| /external/llvm/test/MC/ARM/ |
| neon-reciprocal-encoding.s | 11 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
12 vrecps.f32 d16, d16, d17
13 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
14 vrecps.f32 q8, q8, q9
|
| neont2-reciprocal-encoding.s | 13 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x0f]
14 vrecps.f32 d16, d16, d17
15 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x0f]
16 vrecps.f32 q8, q8, q9
|
| fullfp16-neon-neg.s | 170 vrecps.f16 d0, d1, d2
171 vrecps.f16 q0, q1, q2
|
| fullfp16-neon.s | 233 vrecps.f16 d0, d1, d2
234 vrecps.f16 q0, q1, q2
235 @ ARM: vrecps.f16 d0, d1, d2 @ encoding: [0x12,0x0f,0x11,0xf2]
236 @ ARM: vrecps.f16 q0, q1, q2 @ encoding: [0x54,0x0f,0x12,0xf2]
237 @ THUMB: vrecps.f16 d0, d1, d2 @ encoding: [0x11,0xef,0x12,0x0f]
238 @ THUMB: vrecps.f16 q0, q1, q2 @ encoding: [0x12,0xef,0x54,0x0f]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neon-reciprocal-encoding.s | 11 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0xb1,0x0f,0x40,0xf2]
12 vrecps.f32 d16, d16, d17
13 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0xf2,0x0f,0x40,0xf2]
14 vrecps.f32 q8, q8, q9
|
| neont2-reciprocal-encoding.s | 13 @ CHECK: vrecps.f32 d16, d16, d17 @ encoding: [0x40,0xef,0xb1,0x0f]
14 vrecps.f32 d16, d16, d17
15 @ CHECK: vrecps.f32 q8, q8, q9 @ encoding: [0x40,0xef,0xf2,0x0f]
16 vrecps.f32 q8, q8, q9
|
| /external/arm-neon-tests/ |
| Android.mk | 40 vcalt vrecps vrsqrts vcvt
|
| ref_vrecps.c | 35 #define TEST_MSG "VRECPS/VRECPSQ"
40 /* Basic test: y=vrecps(x), then store the result. */
43 vrecps##Q##_##T2##W(VECT_VAR(vector, T1, W, N), \
|
| Makefile | 55 vcalt vrecps vrsqrts vcvt
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| neon-omit.s | 45 vrecps.f d1,d2
90 vrecps.f d1,d30,d2
|
| armv8-2-fp16-simd.d | 95 14c: f21a8f1c vrecps.f16 d8, d10, d12
96 150: f2540ff8 vrecps.f16 q8, q10, q12
99 15c: f2104f58 vrecps.f16 q2, q0, q4
|
| armv8-2-fp16-simd-thumb.d | 95 14c: ef1a 8f1c vrecps.f16 d8, d10, d12
96 150: ef54 0ff8 vrecps.f16 q8, q10, q12
99 15c: ef10 4f58 vrecps.f16 q2, q0, q4
|
| neon-omit.d | 46 0[0-9a-f]+ <[^>]+> f2011f12 vrecps\.f32 d1, d1, d2
88 0[0-9a-f]+ <[^>]+> f20e1f92 vrecps\.f32 d1, d30, d2
|
| armv8-2-fp16-simd.s | 102 .irp op, vrecps.f16, vrsqrts.f16
|
| armv8-2-fp16-simd-warning.l | 85 [^:]*:202: Error: selected processor does not support fp16 instruction -- `vrecps.f16 d8,d10,d12'
86 [^:]*:202: Error: selected processor does not support fp16 instruction -- `vrecps.f16 q8,q10,q12'
|
| neon-cov.s | 317 regs3_1 vrecps vrecpsq .f32
|
| neon-cov.d | [all...] |
| /external/valgrind/none/tests/arm/ |
| neon128.stdout.exp | [all...] |
| /external/vixl/src/aarch32/ |
| assembler-aarch32.h | 5464 void vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) { function in class:vixl::aarch32::Assembler
5470 void vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.h | [all...] |
| assembler-aarch32.cc | 23880 void Assembler::vrecps( function in class:vixl::aarch32::Assembler
23907 void Assembler::vrecps( function in class:vixl::aarch32::Assembler
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | [all...] |
| assembler-arm.cc | 4516 void Assembler::vrecps(QwNeonRegister dst, QwNeonRegister src1, function in class:v8::internal::Assembler
[all...] |
