| /external/mesa3d/src/compiler/glsl/ |
| opt_constant_propagation.cpp | 53 acp_entry(ir_variable *var, unsigned write_mask, ir_constant *constant)
58 this->write_mask = write_mask;
60 this->initial_values = write_mask;
66 this->write_mask = src->write_mask;
73 unsigned write_mask; member in class:__anon29232::acp_entry
86 kill_entry(ir_variable *var, unsigned write_mask)
90 this->write_mask = write_mask;
94 unsigned write_mask; member in class:__anon29232::kill_entry
[all...] |
| opt_vectorize.cpp | 182 this->last_assignment->write_mask = 0;
186 this->last_assignment->write_mask |= 1 << i;
214 single_channel_write_mask(unsigned write_mask)
216 return write_mask != 0 && (write_mask & (write_mask - 1)) == 0;
223 write_mask_to_swizzle(unsigned write_mask)
225 switch (write_mask) {
238 write_mask_matches_swizzle(unsigned write_mask,
241 return ((write_mask == WRITEMASK_X && swz->mask.x == SWIZZLE_X) |
[all...] |
| opt_copy_propagation_elements.cpp | 76 acp_entry(ir_variable *lhs, ir_variable *rhs, int write_mask, int swizzle[4])
81 this->write_mask = write_mask;
87 unsigned int write_mask; member in class:__anon29235::acp_entry
99 kill_entry(ir_variable *var, int write_mask)
102 this->write_mask = write_mask;
106 unsigned int write_mask; member in class:__anon29235::kill_entry
234 k = new(this->lin_ctx) kill_entry(var, ir->write_mask);
311 if (entry->write_mask & (1 << swizzle_chan[c]))
582 int write_mask = ir->write_mask; local
[all...] |
| lower_buffer_access.h | 53 unsigned int packing, unsigned int write_mask);
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| lower_vector_derefs.cpp | 72 ir->write_mask = (1 << new_lhs->type->vector_elements) - 1;
74 ir->write_mask = 1 << old_index_constant->get_int_component(0);
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| opt_dead_code_local.cpp | 57 this->unused = ir->write_mask;
200 ir->write_mask);
211 int remove = entry->unused & ir->write_mask;
215 entry->ir->write_mask,
216 remove, entry->ir->write_mask & ~remove);
227 entry->ir->write_mask &= ~remove;
229 if (entry->ir->write_mask == 0) {
236 * write_mask.
243 if ((entry->ir->write_mask | remove) & (1 << i)) {
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| lower_vector.cpp | 151 unsigned write_mask; local
164 write_mask = 0;
179 write_mask |= (1U << i);
183 assert((write_mask == 0) == (assigned == 0));
194 new(mem_ctx) ir_assignment(lhs, c, NULL, write_mask);
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| lower_variable_index_to_cond_assign.cpp | 191 unsigned int write_mask; member in struct:__anon29221::assignment_generator
199 write_mask(0),
225 ? new(mem_ctx) ir_assignment(element, variable, condition, write_mask)
511 ag.write_mask = orig_assign->write_mask;
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| lower_buffer_access.cpp | 63 unsigned int write_mask)
159 is_write ? write_mask : (1 << deref->type->vector_elements) - 1;
209 if (!is_write || ((1U << i) & write_mask))
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| /external/mesa3d/src/compiler/nir/ |
| nir_lower_vec_to_movs.c | 64 mov->dest.write_mask = (1u << start_idx);
70 if (!(vec->dest.write_mask & (1 << i)))
76 mov->dest.write_mask |= (1 << i);
81 unsigned channels_handled = mov->dest.write_mask;
91 mov->dest.write_mask &= ~(1 << i);
97 if (mov->dest.write_mask) {
180 unsigned write_mask = 0; local
182 if (!(vec->dest.write_mask & (1 << i)))
192 write_mask |= 1 << i;
207 src_alu->dest.write_mask = write_mask
[all...] |
| nir_lower_regs_to_ssa.c | 119 unsigned write_mask = alu->dest.write_mask; local
120 if (write_mask == (1 << reg->num_components) - 1) {
141 if (write_mask & (1 << index))
164 if (!((write_mask >> index) & 1))
176 alu->dest.write_mask = (1 << num_components) - 1;
196 if (write_mask & (1 << i)) {
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| nir_lower_atomics.c | 132 mul->dest.write_mask = 0x1;
140 add->dest.write_mask = 0x1;
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| nir_lower_alu_to_scalar.c | 39 instr->dest.write_mask = (1 << num_components) - 1;
71 assert(instr->dest.write_mask == 1);
83 assert(instr->dest.write_mask != 0);
213 if (!(instr->dest.write_mask & (1 << chan)))
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| nir_lower_locals_to_regs.c | 167 mul->dest.write_mask = 1;
185 add->dest.write_mask = 1;
216 mov->dest.write_mask = (1 << intrin->num_components) - 1;
242 mov->dest.write_mask = nir_intrinsic_write_mask(intrin);
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| nir_opt_copy_prop_vars.c | 222 struct copy_entry *entry, unsigned write_mask)
228 unsigned dead_comps = write_mask & ~entry->comps_may_be_read;
284 unsigned write_mask)
301 remove_dead_writes(state, iter, write_mask);
330 const struct value *value, unsigned write_mask,
333 entry->comps_may_be_read &= ~write_mask;
338 if (write_mask & (1 << i)) {
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| /external/mesa3d/src/gallium/drivers/ilo/core/ |
| ilo_builder_blt.h | 95 gen6_blt_translate_write_mask(enum gen6_blt_mask write_mask)
97 switch (write_mask) {
111 enum gen6_blt_mask write_mask)
128 gen6_blt_translate_write_mask(write_mask) |
153 enum gen6_blt_mask write_mask)
171 gen6_blt_translate_write_mask(write_mask) |
210 enum gen6_blt_mask write_mask)
228 gen6_blt_translate_write_mask(write_mask) |
256 enum gen6_blt_mask write_mask)
275 gen6_blt_translate_write_mask(write_mask) |
[all...] |
| ilo_state_cc.c | 137 if (front_p->write_mask || back_p->write_mask)
141 front_p->write_mask << GEN6_ZS_DW1_STENCIL_WRITE_MASK__SHIFT |
143 back_p->write_mask << GEN6_ZS_DW1_STENCIL1_WRITE_MASK__SHIFT;
212 if (front_p->write_mask || back_p->write_mask)
216 front_p->write_mask << GEN8_ZS_DW2_STENCIL_WRITE_MASK__SHIFT |
218 back_p->write_mask << GEN8_ZS_DW2_STENCIL1_WRITE_MASK__SHIFT;
797 if (front_p->write_mask || back_p->write_mask)
[all...] |
| ilo_state_cc.h | 133 uint8_t write_mask; member in struct:ilo_state_cc_stencil_params_info
|
| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_blitter_blt.c | 133 enum gen6_blt_mask write_mask)
169 width, height, rop, value_mask, write_mask);
242 enum gen6_blt_mask write_mask)
285 dst_box->width, dst_box->height, rop, value_mask, write_mask);
516 enum gen6_blt_mask value_mask, write_mask; local
529 write_mask = GEN6_BLT_MASK_16;
536 write_mask = GEN6_BLT_MASK_32;
543 write_mask = GEN6_BLT_MASK_32_LO;
552 write_mask = GEN6_BLT_MASK_32;
554 write_mask = GEN6_BLT_MASK_32_LO
[all...] |
| ilo_render_gen.h | 367 const uint32_t write_mask = (dw1 & GEN6_PIPE_CONTROL_WRITE__MASK); local
368 struct intel_bo *bo = (write_mask) ? r->workaround_bo : NULL;
372 if (write_mask)
373 assert(write_mask == GEN6_PIPE_CONTROL_WRITE_IMM);
|
| /external/mesa3d/src/gallium/auxiliary/tgsi/ |
| tgsi_util.c | 177 unsigned write_mask = inst->Dst[0].Register.WriteMask; local
250 read_mask = write_mask;
259 read_mask = write_mask & TGSI_WRITEMASK_XY ? TGSI_WRITEMASK_X : 0;
264 read_mask = write_mask & TGSI_WRITEMASK_XYZ ? TGSI_WRITEMASK_X : 0;
|
| /external/mesa3d/src/gallium/drivers/r600/ |
| r600_shader.h | 55 unsigned write_mask; member in struct:r600_shader_io
|
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_fs_vector_splitting.cpp | 177 _mesa_is_pow_two(ir->write_mask) &&
264 if (!(ir->write_mask & (1 << i)))
294 switch (ir->write_mask) {
313 ir->write_mask = (1 << 0);
|
| /external/mesa3d/src/gallium/drivers/svga/svgadump/ |
| svga_shader_dump.c | 404 if (dstreg.write_mask != SVGA3DWRITEMASK_ALL) {
406 if (dstreg.write_mask & SVGA3DWRITEMASK_0)
408 if (dstreg.write_mask & SVGA3DWRITEMASK_1)
410 if (dstreg.write_mask & SVGA3DWRITEMASK_2)
412 if (dstreg.write_mask & SVGA3DWRITEMASK_3)
|
| /external/mesa3d/src/gallium/drivers/i915/ |
| i915_fpc_optimize.c | 163 unsigned write_mask)
165 if ( write_mask & TGSI_WRITEMASK_X && r->Register.SwizzleX != TGSI_SWIZZLE_X)
167 if ( write_mask & TGSI_WRITEMASK_Y && r->Register.SwizzleY != TGSI_SWIZZLE_Y)
169 if ( write_mask & TGSI_WRITEMASK_Z && r->Register.SwizzleZ != TGSI_SWIZZLE_Z)
171 if ( write_mask & TGSI_WRITEMASK_W && r->Register.SwizzleW != TGSI_SWIZZLE_W)
196 unsigned write_mask,
199 if ( write_mask & TGSI_WRITEMASK_X )
204 if ( write_mask & TGSI_WRITEMASK_Y )
209 if ( write_mask & TGSI_WRITEMASK_Z )
214 if ( write_mask & TGSI_WRITEMASK_W
[all...] |
