/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb2/ |
thumb2-ldr_pre.ll | 4 ; RUN: grep {ldrsb.*\\!} | count 1
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/external/vixl/test/aarch32/config/ |
cond-rd-memop-immediate-512-a32.json | 35 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}] ; A1 36 // LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<imm_2> ; A1 37 // LDRSB{<c>}{<q>} <Rt>, [<Rn>{, #{+/-}<imm_2>}]! ; A1
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cond-rd-memop-rs-a32.json | 38 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1 39 // LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1 40 // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1
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/toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
thumb2_relax.s | 34 ls ldrsb
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sp-pc-validations-bad-t.l | 102 [^:]*:162: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]' 103 [^:]*:164: Error: r13 not allowed here -- `ldrsb sp,\[r0,#4\]' 104 [^:]*:165: Error: r15 not allowed here -- `ldrsb pc,\[r0,#-4\]' 105 [^:]*:166: Error: r13 not allowed here -- `ldrsb sp,\[r0,#-4\]' 106 [^:]*:167: Error: r15 not allowed here -- `ldrsb pc,\[r0\],#4' 107 [^:]*:168: Error: r13 not allowed here -- `ldrsb sp,\[r0\],#4' 108 [^:]*:169: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]!' 109 [^:]*:170: Error: r13 not allowed here -- `ldrsb sp,\[r0,#4\]!' 110 [^:]*:173: Error: r15 not allowed here -- `ldrsb pc,label' 111 [^:]*:174: Error: r15 not allowed here -- `ldrsb pc,\[pc,#-0\] [all...] |
sp-pc-validations-bad.l | 63 [^:]*:104: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]' 64 [^:]*:105: Error: r15 not allowed here -- `ldrsb pc,\[r0\],#4' 65 [^:]*:106: Error: r15 not allowed here -- `ldrsb pc,\[r0,#4\]!' 66 [^:]*:109: Error: r15 not allowed here -- `ldrsb pc,label' 67 [^:]*:110: Error: r15 not allowed here -- `ldrsb pc,\[pc,#-0\]' 68 [^:]*:113: Error: r15 not allowed here -- `ldrsb pc,\[r0,r1\]' 69 [^:]*:114: Error: r15 not allowed here -- `ldrsb pc,\[r0,r1\]!' 70 [^:]*:115: Error: r15 not allowed here -- `ldrsb pc,\[r0\],r1' 71 [^:]*:116: Error: cannot use register index with PC-relative addressing -- `ldrsb r0,\[r1,pc\]' 72 [^:]*:117: Error: cannot use register index with PC-relative addressing -- `ldrsb r0,\[r1,pc\]! [all...] |
unpredictable.s | 25 .word 0xe190f0d1 @ ldrsb pc, [r0, r1] 26 .word 0xe010f0d0 @ ldrsb pc, [r0], -r0
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ldst-pc.d | 15 0[0-9a-f]+ <[^>]+> e19f10d2 ldrsb r1, \[pc, r2\]
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t16-bad.l | 140 [^:]*:109: Error: lo register required -- `ldrsb r8,\[r0\]' 141 [^:]*:109: Error: lo register required -- `ldrsb r0,\[r8\]' 142 [^:]*:109: Error: lo register required -- `ldrsb r0,\[r0,r8\]' 143 [^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,#4\]!' 144 [^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],#4' 145 [^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1,-r2\]' 146 [^:]*:109: Error: Thumb does not support this addressing mode -- `ldrsb r0,\[r1\],r2'
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/external/capstone/suite/MC/ARM/ |
arm-memory-instructions.s.cs | 58 0xd0,0x30,0xd4,0xe1 = ldrsb r3, [r4] 59 0xd1,0x21,0xd7,0xe1 = ldrsb r2, [r7, #17] 60 0xdf,0x1f,0xf8,0xe1 = ldrsb r1, [r8, #255]! 61 0xd9,0xc0,0xdd,0xe0 = ldrsb r12, [sp], #9 62 0xd4,0x60,0x95,0xe1 = ldrsb r6, [r5, r4] 63 0xdb,0x30,0xb8,0xe1 = ldrsb r3, [r8, r11]! 64 0xd1,0x10,0x32,0xe1 = ldrsb r1, [r2, -r1]! 65 0xd2,0x90,0x97,0xe0 = ldrsb r9, [r7], r2 66 0xd2,0x40,0x13,0xe0 = ldrsb r4, [r3], -r2
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/external/llvm/test/CodeGen/ARM/ |
fast-isel-fold.ll | 77 ; ARM: ldrsb 80 ; THUMB: ldrsb
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fast-isel-ldrh-strh-arm.ll | 128 ; ARM: ldrsb r0, [r0, #-8] 137 ; ARM: ldrsb r0, [r0, #-255] 148 ; ARM: ldrsb r0, [r0]
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load.ll | 8 ; CHECK: ldrsb r0, [r0, r1] 101 ; CHECK-T2: ldrsb.w r0, [r0] 177 ; CHECK-T1: ldrsb r0, [r0, r1] 178 ; CHECK-T2: ldrsb.w r0, [r0, #31] 262 ; CHECK-T1: ldrsb r0, [r0, r1] 263 ; CHECK-T2: ldrsb.w r0, [r0, #32] 359 ; CHECK-T1: ldrsb r0, [r0, r1] 360 ; CHECK-T2: ldrsb.w r0, [r0, #4095] 463 ; CHECK: ldrsb r0, [r0, r1]
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/external/sonivox/arm-wt-22k/lib_src/ |
ARM-E_interpolate_loop_gnu.s | 85 LDRSB tmp0, [pPhaseAccum] @ tmp0 = x0
86 LDRSB tmp1, [pPhaseAccum, #1] @ tmp1 = x1
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ARM-E_interpolate_noloop_gnu.s | 77 LDRSB tmp0, [pPhaseAccum] @ tmp0 = x0
78 LDRSB tmp1, [pPhaseAccum, #1] @ tmp1 = x1
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/external/valgrind/none/tests/arm64/ |
memory.c | 181 TESTINST2_hide2("ldrsb x21, [x22, #88]", AREA_MID, x21,x22,0); 182 TESTINST2_hide2("ldrsb w21, [x22, #56]", AREA_MID, x21,x22,0); 189 TESTINST2_hide2("ldrsb x21, [x22, #-88]!", AREA_MID, x21,x22,0); 190 TESTINST2_hide2("ldrsb w21, [x22, #-56]!", AREA_MID, x21,x22,0); 195 TESTINST2_hide2("ldrsb x21, [x22], #-88", AREA_MID, x21,x22,0); 196 TESTINST2_hide2("ldrsb w21, [x22], #-56", AREA_MID, x21,x22,0); 203 TESTINST2_hide2("ldrsb x21, [x22, #-88]", AREA_MID, x21,x22,0); 204 TESTINST2_hide2("ldrsb w21, [x22, #-56]", AREA_MID, x21,x22,0); 236 TESTINST3_hide2and3("ldrsb x21, [x22,x23]", AREA_MID, 5, x21,x22,x23,0); 237 TESTINST3_hide2and3("ldrsb x21, [x22,x23, lsl #0]", AREA_MID, 5, x21,x22,x23,0) [all...] |
/external/llvm/test/CodeGen/AArch64/ |
arm64-abi.ll | 10 ; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp, #5] 11 ; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp, #4] 13 ; CHECK-DAG: ldrsb {{w[0-9]+}}, [sp] 15 ; FAST-DAG: ldrsb {{w[0-9]+}}, [sp, #5] 16 ; FAST-DAG: ldrsb {{w[0-9]+}}, [sp, #4] 18 ; FAST-DAG: ldrsb {{w[0-9]+}}, [sp]
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fast-isel-int-ext2.ll | 221 ; CHECK: ldrsb w0, [x0, x1] 249 ; CHECK: ldrsb x0, [x0, x1] 367 ; CHECK: ldrsb w0, [x0, w1, sxtw] 397 ; CHECK: ldrsb x0, [x0, w1, sxtw]
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neon-truncStore-extLoad.ll | 36 ; CHECK: ldrsb
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/external/llvm/test/MC/ARM/ |
arm-memory-instructions.s | 207 @ LDRSB (immediate) 209 ldrsb r3, [r4] 210 ldrsb r2, [r7, #17] 211 ldrsb r1, [r8, #255]! 212 ldrsb r12, [sp], #9 214 @ CHECK: ldrsb r3, [r4] @ encoding: [0xd0,0x30,0xd4,0xe1] 215 @ CHECK: ldrsb r2, [r7, #17] @ encoding: [0xd1,0x21,0xd7,0xe1] 216 @ CHECK: ldrsb r1, [r8, #255]! @ encoding: [0xdf,0x1f,0xf8,0xe1] 217 @ CHECK: ldrsb r12, [sp], #9 @ encoding: [0xd9,0xc0,0xdd,0xe0] 221 @ FIXME: LDRSB (label [all...] |
/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
arm-memory-instructions.s | 200 @ LDRSB (immediate) 202 ldrsb r3, [r4] 203 ldrsb r2, [r7, #17] 204 ldrsb r1, [r8, #255]! 205 ldrsb r12, [sp], #9 207 @ CHECK: ldrsb r3, [r4] @ encoding: [0xd0,0x30,0xd4,0xe1] 208 @ CHECK: ldrsb r2, [r7, #17] @ encoding: [0xd1,0x21,0xd7,0xe1] 209 @ CHECK: ldrsb r1, [r8, #255]! @ encoding: [0xdf,0x1f,0xf8,0xe1] 210 @ CHECK: ldrsb r12, [sp], #9 @ encoding: [0xd9,0xc0,0xdd,0xe0] 214 @ FIXME: LDRSB (label [all...] |
/system/core/libpixelflinger/codeflinger/ |
ARMAssemblerProxy.cpp | 133 // LDRH/LDRSB/LDRSH/STRH 227 void ARMAssemblerProxy::LDRSB(int cc, int Rd, int Rn, uint32_t offset) { 228 mTarget->LDRSB(cc, Rd, Rn, offset);
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMInstrInfo.cpp | 51 return ARM::LDRSB;
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/prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
objdump_test.go | 138 "ldrsb": "ldursb",
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/prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
objdump_test.go | 138 "ldrsb": "ldursb",
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