1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 { 28 "mnemonics": [ 29 "Ldr", // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1 30 // LDR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1 31 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1 32 "Ldrb", // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1 33 // LDRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1 34 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1 35 "Ldrh", // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1 36 // LDRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1 37 // LDRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1 38 "Ldrsb", // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1 39 // LDRSB{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1 40 // LDRSB{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1 41 "Ldrsh", // LDRSH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1 42 // LDRSH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1 43 // LDRSH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1 44 "Str", // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1 45 // STR{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1 46 // STR{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1 47 "Strb", // STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}] ; A1 48 // STRB{<c>}{<q>} <Rt>, [<Rn>], {+/-}<Rm>{, <shift>} ; A1 49 // STRB{<c>}{<q>} <Rt>, [<Rn>, {+/-}<Rm>{, <shift>}]! ; A1 50 "Strh" // STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>] ; A1 51 // STRH{<c>}{<q>} <Rt>, [<Rn>], #{+/-}<Rm> ; A1 52 // STRH{<c>}{<q>} <Rt>, [<Rn>, #{+/-}<Rm>]! ; A1 53 ], 54 "description": { 55 "operands": [ 56 { 57 "name": "cond", 58 "type": "Condition" 59 }, 60 { 61 "name": "rd", 62 "type": "AllRegistersButPC" 63 }, 64 { 65 "name": "memop", 66 "wrapper": "MemOperand", 67 "operands": [ 68 { 69 "name": "rn", 70 "type": "AllRegistersButPC" 71 }, 72 { 73 "name": "sign", 74 "type": "Sign" 75 }, 76 { 77 "name": "rm", 78 "type": "AllRegistersButPC" 79 }, 80 { 81 "name": "addr_mode", 82 "type": "AddressingMode" 83 } 84 ] 85 } 86 ], 87 "inputs": [ 88 { 89 "name": "apsr", 90 "type": "NZCV" 91 }, 92 { 93 "name": "rd", 94 "type": "Register" 95 }, 96 { 97 "name": "rm", 98 "type": "RegisterOffsetLowerThan4096" 99 }, 100 { 101 "name": "memop", 102 "type": "MemOperand" 103 } 104 ] 105 }, 106 "test-files": [ 107 { 108 "type": "assembler", 109 "test-cases": [ 110 { 111 "name": "Registers", 112 "operands": [ 113 "cond", "rd", "rn", "rm" 114 ], 115 "operand-limit": 100 116 }, 117 { 118 "name": "MemOperandsOffset", 119 "operands": [ 120 "rn", "sign", "rm", "addr_mode" 121 ], 122 "operand-filter": "addr_mode == 'Offset'", 123 "operand-limit": 200 124 }, 125 { 126 "name": "MemOperandsWriteBack", 127 "operands": [ 128 "rd", "rn", "sign", "rm", "addr_mode" 129 ], 130 "operand-filter": "addr_mode != 'Offset' and rd != rn", 131 "operand-limit": 400 132 } 133 ] 134 }, 135 { 136 // TODO: The simulator tests do not support the case where `rd` == 137 // `rn`. See `data_types.MemOperand.Epilogue()` for details. 138 "type": "simulator", 139 "test-cases": [ 140 { 141 "name": "Condition", 142 "operands": [ 143 "cond", "rd", "rn", "rm" 144 ], 145 "operand-filter": "rd == 'r0' and rn == 'r1' and rm == 'r8'", 146 "inputs": [ 147 "apsr" 148 ] 149 }, 150 { 151 "name": "PositiveOffset", 152 "operands": [ 153 "rd", "rn", "sign", "rm", "addr_mode" 154 ], 155 "operand-filter": "sign == 'plus' and addr_mode == 'Offset' and rd != rm and rd != rn and rn != rm", 156 "operand-limit": 100, 157 "inputs": [ 158 "memop", "rm" 159 ], 160 "input-limit": 10 161 }, 162 { 163 "name": "NegativeOffset", 164 "operands": [ 165 "rd", "rn", "sign", "rm", "addr_mode" 166 ], 167 "operand-filter": "sign == 'minus' and addr_mode == 'Offset' and rd != rm and rd != rn and rn != rm", 168 "operand-limit": 100, 169 "inputs": [ 170 "memop", "rm" 171 ], 172 "input-limit": 10 173 }, 174 { 175 "name": "PositivePostIndex", 176 "operands": [ 177 "rd", "rn", "sign", "rm", "addr_mode" 178 ], 179 "operand-filter": "sign == 'plus' and addr_mode == 'PostIndex' and rd != rm and rd != rn and rn != rm", 180 "operand-limit": 100, 181 "inputs": [ 182 "memop", "rm" 183 ], 184 "input-limit": 10 185 }, 186 { 187 "name": "NegativePostIndex", 188 "operands": [ 189 "rd", "rn", "sign", "rm", "addr_mode" 190 ], 191 "operand-filter": "sign == 'minus' and addr_mode == 'PostIndex' and rd != rm and rd != rn and rn != rm", 192 "operand-limit": 100, 193 "inputs": [ 194 "memop", "rm" 195 ], 196 "input-limit": 10 197 }, 198 { 199 "name": "PositivePreIndex", 200 "operands": [ 201 "rd", "rn", "sign", "rm", "addr_mode" 202 ], 203 "operand-filter": "sign == 'plus' and addr_mode == 'PreIndex' and rd != rm and rd != rn and rn != rm", 204 "operand-limit": 100, 205 "inputs": [ 206 "memop", "rm" 207 ], 208 "input-limit": 10 209 }, 210 { 211 "name": "NegativePreIndex", 212 "operands": [ 213 "rd", "rn", "sign", "rm", "addr_mode" 214 ], 215 "operand-filter": "sign == 'minus' and addr_mode == 'PreIndex' and rd != rm and rd != rn and rn != rm", 216 "operand-limit": 100, 217 "inputs": [ 218 "memop", "rm" 219 ], 220 "input-limit": 10 221 } 222 ] 223 } 224 ] 225 } 226
