| /external/v8/src/ic/ |
| keyed-store-generic.cc | 470 // Out-of-capacity accesses (index >= capacity) jump here. Additionally,
[all...] |
| /external/valgrind/docs/html/ |
| dh-manual.html | 237 <p>Really, what we want is to measure only memory accesses in
246 size, and which are 4096 bytes or smaller, DHAT counts accesses
|
| /external/valgrind/exp-dhat/docs/ |
| dh-manual.xml | 260 <para>Really, what we want is to measure only memory accesses in
272 size, and which are 4096 bytes or smaller, DHAT counts accesses
|
| /frameworks/base/core/java/android/os/ |
| ZygoteProcess.java | 169 * Proportion of hidden API accesses that should be logged to the event log; 0 - 0x10000.
490 * Set the precentage of detected hidden API accesses that are logged to the event log.
|
| /libcore/ojluni/src/main/java/java/lang/ |
| ThreadLocal.java | 34 * their normal counterparts in that each thread that accesses one (via its
111 * time a thread accesses the variable with the {@link #get}
|
| /packages/apps/ExactCalculator/src/com/android/calculator2/ |
| ExpressionDB.java | 211 // All calls that create background database accesses are made from the UI thread, and
348 * Erase the entire database. Assumes no other accesses to the database are
|
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/lib/gcc/x86_64-w64-mingw32/4.8.3/plugin/include/config/i386/ |
| i386.h | [all...] |
| /prebuilts/gdb/darwin-x86/lib/python2.7/ |
| rexec.py | 175 system accesses made to import a module, without changing the
176 actual algorithm that controls the order in which those accesses are
|
| /prebuilts/gdb/linux-x86/lib/python2.7/ |
| rexec.py | 175 system accesses made to import a module, without changing the
176 actual algorithm that controls the order in which those accesses are
|
| /prebuilts/python/darwin-x86/2.7.5/lib/python2.7/ |
| rexec.py | 175 system accesses made to import a module, without changing the
176 actual algorithm that controls the order in which those accesses are
|
| /prebuilts/python/linux-x86/2.7.5/lib/python2.7/ |
| rexec.py | 175 system accesses made to import a module, without changing the
176 actual algorithm that controls the order in which those accesses are
|
| /system/sepolicy/prebuilts/api/26.0/private/ |
| app.te | 75 # App sandbox file accesses.
227 # accesses to the underlying FS.
|
| /system/sepolicy/prebuilts/api/27.0/private/ |
| app.te | 72 # App sandbox file accesses.
240 # accesses to the underlying FS.
|
| /system/sepolicy/prebuilts/api/28.0/public/ |
| app.te | 68 # App sandbox file accesses.
263 # accesses to the underlying FS.
|
| /system/sepolicy/public/ |
| app.te | 68 # App sandbox file accesses.
263 # accesses to the underlying FS.
|
| /external/valgrind/docs/ |
| valgrind.1 | [all...] |
| /external/swiftshader/third_party/LLVM/docs/ |
| AliasAnalysis.html | 156 <tt>C[0]</tt> and <tt>C[1]</tt> because they are accesses to two distinct
157 locations one byte apart, and the accesses are each one byte. In this case, the
177 that the accesses alias.</p>
207 freed and reallocated between accesses through one pointer and accesses through
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| BasicAliasAnalysis.cpp | 755 // Since memset is 'accesses arguments' only, the AliasAnalysis base class
[all...] |
| /toolchain/binutils/binutils-2.27/gas/config/ |
| tc-d10v.c | 723 modifies the same register. Accesses to control registers and memory
724 are treated as accesses to a single register. So if both instructions
859 instruction has completed). Accesses to control registers, PSW,
860 and memory are treated as accesses to a single register. So if
[all...] |
| /external/valgrind/helgrind/ |
| libhb_core.c | 159 'Thr_n_RCEC', which records information about old accesses, packs
607 static UWord stats__cache_totrefs = 0; // # total accesses
626 static UWord stats__cline_64to32splits = 0; // # 64-bit accesses split
627 static UWord stats__cline_32to16splits = 0; // # 32-bit accesses split
628 static UWord stats__cline_16to8splits = 0; // # 16-bit accesses split
[all...] |
| /art/runtime/gc/collector/ |
| concurrent_copying.cc | [all...] |
| /external/libxml2/ |
| xmlIO.c | 567 * Standard I/O for file accesses *
1044 * I/O for compressed file accesses *
1249 * I/O for compressed file accesses *
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | 241 // Accesses via GEPs that are consistent with element access of a vector
246 // Accesses via vector operations and GEPs that are consistent with the
337 /// Here we turn element accesses into insert/extract element operations.
361 // Full width accesses can be ignored, because they can always be turned
406 /// its accesses to a single vector type, return true and set VecTy to
[all...] |
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/ |
| NonDiscoverablePciDeviceIo.c | 247 // Only allow accesses to the BARs we emulate
334 // Only allow accesses to the BARs we emulate
470 // Read all zeroes for config space accesses beyond the first
[all...] |
| /external/kernel-headers/original/uapi/drm/ |
| i915_drm.h | 67 * surface data and the coherency for this data wrt. CPU vs. GPU accesses.
71 * Not cached anywhere, coherency between CPU and GPU accesses is
83 * Coherency between CPU and GPU accesses to the surface is not
[all...] |
