| /external/llvm/include/llvm/IR/ |
| Intrinsics.td | 41 // IntrArgMemOnly - This intrinsic only accesses memory that its pointer-typed
325 // with respect to nearby accesses to the same memory.
436 // None of these intrinsics accesses memory at all.
448 // None of these intrinsics accesses memory at all...but that doesn't mean the
[all...] |
| /external/llvm/lib/Analysis/ |
| LoopUnrollAnalyzer.cpp | 126 // FIXME: For now we conservatively ignore out of bound accesses, but
|
| ScopedNoAliasAA.cpp | 31 // accesses are assumed not to alias.
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64Subtarget.h | 72 // StrictAlign - Disallow unaligned memory accesses.
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| /external/llvm/lib/Target/AMDGPU/ |
| SIMachineFunctionInfo.h | 264 /// descriptor for scratch accesses.
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCSubtarget.cpp | 149 /// Return true if accesses to the specified global have to go through a dyld
|
| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86IntelInstPrinter.cpp | 225 // DI accesses are always ES-based.
|
| /external/llvm/lib/Target/X86/ |
| X86MachineFunctionInfo.h | 80 /// NumLocalDynamics - Number of local-dynamic TLS accesses.
|
| /external/llvm/lib/Transforms/Instrumentation/ |
| EfficiencySanitizer.cpp | 16 // - Optimizations may apply to avoid instrumenting some of the accesses.
81 "Number of accesses with a size outside our targeted callout sizes");
86 "Number of accesses assumed to be intra-cache-line");
577 // We'd like to know about cache fragmentation in vtable accesses and
[all...] |
| /external/llvm/test/CodeGen/AMDGPU/ |
| flat-address-space.ll | 7 ; specialize away generic pointer accesses.
|
| /external/llvm/test/CodeGen/SystemZ/ |
| frame-09.ll | 22 ; Make sure that frame accesses after the initial allocation are relative
|
| /external/llvm/test/Transforms/LoopVectorize/X86/ |
| parallel-loops.ll | 75 ; accesses refer to a different loop's identifier.
|
| /external/mesa3d/docs/relnotes/ |
| 11.1.4.html | 91 <li>vc4: Fix subimage accesses to LT textures.</li>
|
| 11.2.2.html | 101 <li>vc4: Fix subimage accesses to LT textures.</li>
|
| 17.0.2.html | 171 <li>i965/fs: detect different bit size accesses to uniforms to push them in proper locations</li>
|
| /external/mesa3d/src/compiler/glsl/ |
| lower_if_to_cond_assign.cpp | 138 /* Lowering branches with TCS output accesses breaks many piglit tests,
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_clip.c | 72 * This program accesses the entire VUE, so nr_regs needs to be the size of
|
| /external/pcre/dist2/src/ |
| pcre2_serialize.c | 183 hardware such as Sparc-64 that doesn't like unaligned memory accesses. The type
|
| /external/python/cpython2/Modules/_ctypes/libffi/src/cris/ |
| sysv.S | 211 just symbols, avoiding memory contents and memory accesses, but the
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| /external/python/cpython3/Modules/_ctypes/libffi/src/cris/ |
| sysv.S | 211 just symbols, avoiding memory contents and memory accesses, but the
|
| /external/skia/include/gpu/ |
| GrShaderCaps.h | 210 * Given a texture's config, this determines what swizzle must be appended to accesses to the
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| /external/skqp/include/gpu/ |
| GrShaderCaps.h | 228 * Given a texture's config, this determines what swizzle must be appended to accesses to the
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMSubtarget.cpp | 36 cl::desc("Disallow all unaligned memory accesses"));
|
| ARMSubtarget.h | 138 /// accesses for some types. For details, see
|
| /external/swiftshader/third_party/subzero/docs/ |
| ALLOCATION.rst | 115 design calls for all shared accesses to go through the GlobalContext, which adds
|
