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  /external/google-breakpad/src/testing/gtest/src/
gtest-printers.cc 308 // memory accesses. MSVC defines _NATIVE_WCHAR_T_DEFINED symbol when
  /external/guava/guava/src/com/google/common/cache/
Striped64.java 88 * Padded variant of AtomicLong supporting only raw accesses plus CAS.
  /external/icu/icu4c/source/tools/toolutil/
ucm.h 111 /* simple accesses ---------------------------------------------------------- */
  /external/jsr305/javadoc/javax/annotation/concurrent/
ThreadSafe.html 102 no sequences of accesses (reads and writes to public fields, calls to public
  /external/kernel-headers/original/uapi/drm/
vc4_drm.h 78 * do validation of memory accesses by the GPU commands. If we were to store
  /external/kernel-headers/original/uapi/linux/
fd.h 226 /* Prevent "aliased" accesses. */
  /external/libhevc/decoder/
ihevcd_bitstream.c 99 * accesses will be unaligned and hence costlier. Since this is codec memory
  /external/libmojo/mojo/edk/js/tests/
js_to_cpp_tests.cc 147 // messages. The values don't matter so long as all accesses are within
  /external/libpcap/
aclocal.m4 803 dnl Checks to see if unaligned memory accesses fail
814 [AC_MSG_CHECKING(if unaligned accesses fail)
830 # comment) doesn't fault on unaligned accesses, but doesn't
840 # file and conclude that unaligned accesses don't work).
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  /external/libunwind/doc/
libunwind-ia64.man 243 This register index accesses the
  /external/libxml2/doc/
threads.html 24 <li>entities lookup/accesses</li>
  /external/libxml2/os400/libxmlrpg/
xmlIO.rpgle 375 * A predefined entity loader disabling network accesses
  /external/llvm/lib/Target/NVPTX/
NVPTXFavorNonGenericAddrSpaces.cpp 13 // When a load/store accesses the generic address space, checks whether the
  /external/llvm/lib/Target/PowerPC/
PPCSubtarget.h 218 /// hasLazyResolverStub - Return true if accesses to the specified global have
  /external/llvm/lib/Target/SystemZ/
SystemZPatterns.td 125 // The other operand is a load of type LOAD, which accesses LENGTH bytes.
  /external/llvm/lib/Target/X86/
X86Subtarget.cpp 198 // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of
  /external/llvm/test/CodeGen/ARM/
vpadd.ll 1 ; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s
  /external/llvm/test/CodeGen/SystemZ/
bswap-02.ll 89 ; Check that volatile accesses do not use LRV, which might access the
bswap-03.ll 89 ; Check that volatile accesses do not use LRVG, which might access the
  /external/llvm/test/CodeGen/X86/
vec_loadsingles.ll 59 ; If the target has slow 32-byte accesses, we should still generate
  /external/llvm/test/Transforms/LICM/
scalar_promote.ll 100 ; Should have promoted 'handle2' accesses.
  /external/llvm/test/Transforms/LoopVectorize/
interleaved-accesses-pred-stores.ll 1 ; RUN: opt -S -loop-vectorize -instcombine -force-vector-width=2 -force-vector-interleave=1 -enable-interleaved-mem-accesses -vectorize-num-stores-pred=1 -enable-cond-stores-vec < %s | FileCheck %s
memdep.ll 93 ; accesses).
  /external/llvm/utils/unittest/googletest/src/
gtest-printers.cc 316 // memory accesses. MSVC defines _NATIVE_WCHAR_T_DEFINED symbol when
  /external/ltp/include/
tst_atomic.h 27 * (1) Removal or reordering of accesses by the compiler.

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