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  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/
s_d-n64.d 23 [0-9a-f]+ <[^>]*> daddu at,at,a1
27 [0-9a-f]+ <[^>]*> daddu at,at,a1
30 [0-9a-f]+ <[^>]*> daddu at,at,a1
718 [0-9a-f]+ <[^>]*> daddu at,at,a1
737 [0-9a-f]+ <[^>]*> daddu at,at,a1
742 [0-9a-f]+ <[^>]*> daddu at,a1,gp
761 [0-9a-f]+ <[^>]*> daddu at,at,a1
766 [0-9a-f]+ <[^>]*> daddu at,a1,gp
    [all...]
sd-n64.d 23 [0-9a-f]+ <[^>]*> daddu at,at,a1
27 [0-9a-f]+ <[^>]*> daddu at,at,a1
30 [0-9a-f]+ <[^>]*> daddu at,at,a1
718 [0-9a-f]+ <[^>]*> daddu at,at,a1
737 [0-9a-f]+ <[^>]*> daddu at,at,a1
742 [0-9a-f]+ <[^>]*> daddu at,a1,gp
761 [0-9a-f]+ <[^>]*> daddu at,at,a1
766 [0-9a-f]+ <[^>]*> daddu at,a1,gp
    [all...]
  /external/compiler-rt/lib/builtins/
clear_cache.c 50 "daddu %[Size], %[Addr], %[Size]\n" /* Calculate end address + 1 */
60 "daddu %[Addr], %[Addr], $v0\n" /* Add step size. */
  /external/llvm/test/CodeGen/Mips/
eh-return64.ll 49 ; CHECK: daddu $sp, $sp, $3
91 ; CHECK: daddu $sp, $sp, $3
mips64muldiv.ll 36 ; ALL: daddu $2, $[[T1]], $2
longbranch.ll 88 ; N64: daddu $[[R1:[0-9]+]], $[[R0]], $25
98 ; N64-NEXT: daddu $1, $ra, $1
  /external/llvm/test/MC/Mips/
mips64-expansions.s 150 # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
163 # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
174 # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
187 # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
237 # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
248 # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
258 # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
269 # CHECK: daddu $1, $1, $9 # encoding: [0x2d,0x08,0x29,0x00]
  /external/v8/src/mips64/
code-stubs-mips64.cc 27 __ Daddu(t9, sp, t9);
31 __ Daddu(a0, a0, 3);
    [all...]
macro-assembler-mips64.cc 119 Daddu(fp, sp, Operand(kPointerSize));
142 Daddu(fp, sp, Operand(offset));
162 Daddu(sp, sp, Operand(num_unsaved * kPointerSize));
234 Daddu(dst, object, Operand(offset - kHeapObjectTag));
302 Daddu(dst, object, Operand(HeapObject::kMapOffset - kHeapObjectTag));
427 Daddu(scratch, js_function, Operand(offset - kHeapObjectTag));
443 Daddu(dst, js_function, Operand(offset - kHeapObjectTag));
492 Daddu(scratch, scratch, kPointerSize);
580 void MacroAssembler::Daddu(Register rd, Register rs, const Operand& rt) {
582 daddu(rd, rs, rt.rm())
    [all...]
  /external/pcre/dist2/src/sljit/
sljitNativeMIPS_64.c 170 return push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src2) | TA(0) | D(dst), DR(dst));
231 FAIL_IF(push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src2) | TA(0) | D(TMP_REG1), DR(TMP_REG1)));
241 return push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(dst) | TA(0) | DA(EQUAL_FLAG), EQUAL_FLAG);
271 FAIL_IF(push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src1) | T(src2) | DA(EQUAL_FLAG), EQUAL_FLAG));
276 FAIL_IF(push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src1) | T(src2) | D(dst), DR(dst)));
304 FAIL_IF(push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(src1) | T(src2) | D(dst), DR(dst)));
309 FAIL_IF(push_inst(compiler, SELECT_OP(DADDU, ADDU) | S(dst) | TA(ULESS_FLAG) | D(dst), DR(dst)));
  /toolchain/binutils/binutils-2.27/opcodes/
mips16-opc.c 238 {"daddu", "z,v,y", 0xe000, 0xf803, WR_1|RD_2|RD_3, 0, I3, 0, 0 },
239 {"daddu", "y,x,4", 0x4010, 0xf810, WR_1|RD_2, 0, I3, 0, 0 },
240 {"daddu", "y,j", 0xfd00, 0xff00, MOD_1, 0, I3, 0, 0 },
241 {"daddu", "S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
242 {"daddu", "S,S,K", 0xfb00, 0xff00, 0, MOD_SP, I3, 0, 0 },
243 {"daddu", "y,P,W", 0xfe00, 0xff00, WR_1, RD_PC, I3, 0, 0 },
244 {"daddu", "y,S,W", 0xff00, 0xff00, WR_1, RD_SP, I3, 0, 0 },
  /art/runtime/interpreter/mterp/mips64/
header.S 158 daddu rPC, rPC, (\count) * 2
168 daddu rPC, rPC, \reg
207 daddu AT, rIBASE, AT
  /external/llvm/test/MC/Mips/mips2/
invalid-mips3.s 17 daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
18 daddu $24,$2,18079 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
19 daddu $19,26943 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/llvm/lib/Target/Mips/MCTargetDesc/
MipsABIInfo.cpp 91 return ArePtrs64bit() ? Mips::DADDu : Mips::ADDu;
  /external/llvm/test/CodeGen/Mips/llvm-ir/
mul.ll 240 ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
241 ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]]
247 ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]]
248 ; 64R6: daddu $2, $[[T1]], $[[T0]]
  /external/valgrind/none/tests/mips64/
arithmetic_instruction.c 8 DADDIU, DADDU, DCLO, DCLZ,
112 case DADDU:
115 TEST1("daddu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
117 TEST1("daddu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
  /system/core/libpixelflinger/codeflinger/
MIPS64Assembler.cpp 435 mMips->DADDU(Rd, Rn, src);
778 mMips->DADDU(R_at, Rn, amode.reg);
806 mMips->DADDU(R_at, Rn, amode.reg);
843 mMips->DADDU(R_at, Rn, amode.reg);
871 mMips->DADDU(R_at, Rn, amode.reg);
896 mMips->DADDU(R_at, Rn, amode.reg);
940 mMips->DADDU(R_at, Rn, amode.reg);
    [all...]
  /external/v8/src/crankshaft/mips64/
lithium-codegen-mips64.cc 146 __ Daddu(a0, sp, Operand(slots * kPointerSize));
365 __ Daddu(t9, t9, Operand(at));
    [all...]
  /external/v8/src/compiler/mips64/
code-generator-mips64.cc 256 __ Daddu(scratch1_, object_, index_);
419 __ Daddu(kScratchReg, i.InputRegister(2), kScratchReg); \
438 __ Daddu(kScratchReg, i.InputRegister(2), kScratchReg); \
460 __ Daddu(kScratchReg, i.InputRegister(3), kScratchReg); \
482 __ Daddu(kScratchReg, i.InputRegister(3), kScratchReg); \
630 masm->Daddu(sp, sp, -stack_slot_delta * kPointerSize);
    [all...]
  /external/llvm/test/MC/Mips/micromips64r6/
valid.s 222 daddu $26, $1, $11 # CHECK: daddu $26, $1, $11 # encoding: [0x59,0x61,0xd1,0x50]
223 daddu $19, $1, $ra # CHECK: daddu $19, $1, $ra # encoding: [0x5b,0xe1,0x99,0x50]
224 daddu $9, $6, $7 # CHECK: daddu $9, $6, $7 # encoding: [0x58,0xe6,0x49,0x50]
225 daddu $9, $3 # CHECK: daddu $9, $9, $3 # encoding: [0x58,0x69,0x49,0x50]
226 daddu $9, $6, -15001 # CHECK: daddiu $9, $6, -15001 # encoding: [0x5d,0x26,0xc5,0x67]
227 daddu $9, 10 # CHECK: daddiu $9, $9, 10 # encoding: [0x5d,0x29,0x00,0x0a
    [all...]
  /external/llvm/test/MC/Mips/mips1/
invalid-mips3.s 21 daddu $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
22 daddu $24,$2,18079 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
23 daddu $19,26943 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
  /external/protobuf/src/google/protobuf/stubs/
atomicops_internals_mips_gcc.h 236 "daddu %1, %0, %3\n" // temp2 = temp + increment
239 "daddu %1, %0, %3\n" // temp2 = temp + increment
  /prebuilts/tools/darwin-x86_64/protoc/include/google/protobuf/stubs/
atomicops_internals_mips_gcc.h 236 "daddu %1, %0, %3\n" // temp2 = temp + increment
239 "daddu %1, %0, %3\n" // temp2 = temp + increment
  /bionic/libc/private/
bionic_asm_mips.h 153 #define PTR_ADDU daddu
  /external/capstone/suite/MC/Mips/
mips64-alu-instructions.s.cs 37 0x2d,0x48,0xc7,0x00 = daddu $9, $6, $7

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