1 #include <stdio.h> 2 #include "const.h" 3 #include "macro_int.h" 4 5 typedef enum { 6 ADD=0, ADDI, ADDIU, ADDU, 7 CLO, CLZ, DADD, DADDI, 8 DADDIU, DADDU, DCLO, DCLZ, 9 DDIV, DDIVU, DIV, DIVU, 10 DMULT, DMULTU, DSUB, DSUBU, 11 MADD, MADDU, MSUB, MSUBU, 12 MUL, MULT, MULTU, MOVN, 13 MOVZ, SEB, SEH, SLT, 14 SLTI, SLTIU, SLTU, SUB, 15 SUBU 16 } arithmetic_op; 17 18 int main() 19 { 20 arithmetic_op op; 21 int i; 22 init_reg_val2(); 23 24 for (op = ADD; op <= SUBU; op++) { 25 for (i = 0; i < N; i++) { 26 switch(op) { 27 case ADD: 28 /* If either GPR rt or GPR rs does not contain sign-extended 29 32-bit values (bits 63..31 equal), then the result of the 30 operation is UNPREDICTABLE. */ 31 TEST1("add $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 32 t0, t1, t2); 33 break; 34 35 case ADDI: 36 /* If GPR rs does not contain a sign-extended 32-bit 37 value (bits 63..31 equal), then the result of the operation 38 is UNPREDICTABLE. */ 39 TEST2("addi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 40 TEST2("addi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 41 TEST2("addi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 42 TEST2("addi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); 43 break; 44 45 case ADDIU: 46 /* If GPR rs does not contain a sign-extended 32-bit 47 value (bits 63..31 equal), then the result of the operation 48 is UNPREDICTABLE. */ 49 TEST2("addiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 50 TEST2("addiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 51 TEST2("addiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 52 TEST2("addiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); 53 break; 54 55 case ADDU: 56 /* If either GPR rt or GPR rs does not contain sign-extended 57 32-bit values (bits 63..31 equal), then the result of the 58 operation is UNPREDICTABLE. */ 59 TEST1("addu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 60 t0, t1, t2); 61 break; 62 63 case CLO: 64 /* If GPR rs does not contain a sign-extended 32-bit 65 value (bits 63..31 equal), then the results of the operation 66 are UNPREDICTABLE. */ 67 TEST3("clo $t0, $t1", reg_val1[i], t0, t1); 68 break; 69 70 case CLZ: 71 /* If GPR rs does not contain a sign-extended 32-bit 72 value (bits 63..31 equal), then the results of the operation 73 are UNPREDICTABLE. */ 74 TEST3("clz $t0, $t1", reg_val1[i], t0, t1); 75 break; 76 77 case DADD: 78 /* If the addition results in 64-bit 2s complement arithmetic 79 overflow, then the destination register is not modified and 80 an IntegerOverflow exception occurs. */ 81 TEST1("dadd $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 82 t0, t1, t2); 83 break; 84 85 case DADDI: 86 /* If the addition results in 64-bit 2s complement arithmetic 87 overflow, then the destination register is not modified and 88 an Integer Overflow exception occurs. */ 89 TEST2("daddi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 90 TEST2("daddi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 91 TEST2("daddi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 92 TEST2("daddi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); 93 TEST2("daddi $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); 94 TEST2("daddi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); 95 TEST2("daddi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); 96 TEST2("daddi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); 97 break; 98 99 case DADDIU: 100 /* No Integer Overflow exception occurs under any 101 circumstances. */ 102 TEST2("daddiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 103 TEST2("daddiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 104 TEST2("daddiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 105 TEST2("daddiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); 106 TEST2("daddiu $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); 107 TEST2("daddiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); 108 TEST2("daddiu $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); 109 TEST2("daddiu $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); 110 break; 111 112 case DADDU: 113 /* No Integer Overflow exception occurs under any 114 circumstances. */ 115 TEST1("daddu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 116 t0, t1, t2); 117 TEST1("daddu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], 118 s0, s1, s2); 119 break; 120 121 case DCLO: 122 /* No arithmetic exception occurs under any circumstances. */ 123 TEST3("dclo $t0, $t1", reg_val1[i], t0, t1); 124 TEST3("dclo $v0, $v1", reg_val2[i], v0, v1); 125 break; 126 127 case DCLZ: 128 /* No arithmetic exception occurs under any circumstances. */ 129 TEST3("dclz $t0, $t1", reg_val1[i], t0, t1); 130 TEST3("dclz $v0, $v1", reg_val2[i], v0, v1); 131 break; 132 133 case DDIV: 134 /* If the divisor in GPR rt is zero, the arithmetic result value 135 is UNPREDICTABLE. */ 136 if (reg_val1[N-i-1] != 0) 137 TEST4("ddiv $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 138 139 if (reg_val2[N-i-1] != 0) 140 TEST4("ddiv $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); 141 142 break; 143 144 case DDIVU: 145 /* If the divisor in GPR rt is zero, the arithmetic result value 146 is UNPREDICTABLE. */ 147 if (reg_val1[N-i-1] != 0) 148 TEST4("ddivu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 149 150 if (reg_val2[N-i-1] != 0) 151 TEST4("ddivu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); 152 153 break; 154 155 case DIV: 156 /* If either GPR rt or GPR rs does not contain sign-extended 157 32-bit values (bits 63..31 equal), then the result of the 158 operation is UNPREDICTABLE. 159 If the divisor in GPR rt is zero, the arithmetic result 160 value is UNPREDICTABLE. */ 161 if (reg_val1[N-i-1] != 0) 162 TEST4("div $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 163 164 break; 165 166 case DIVU: 167 /* If either GPR rt or GPR rs does not contain sign-extended 168 32-bit values (bits 63..31 equal), then the result of the 169 operation is UNPREDICTABLE. 170 If the divisor in GPR rt is zero, the arithmetic result 171 value is UNPREDICTABLE. */ 172 if (reg_val1[N-i-1] != 0) 173 TEST4("divu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 174 175 break; 176 177 case DMULT: 178 /* No arithmetic exception occurs under any circumstances. */ 179 TEST4("dmult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 180 TEST4("dmult $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); 181 break; 182 183 case DMULTU: 184 /* No arithmetic exception occurs under any circumstances. */ 185 TEST4("dmultu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 186 TEST4("dmultu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1); 187 break; 188 189 case DSUB: 190 /* If the subtraction results in 64-bit 2s complement 191 arithmetic overflow, then the destination register is not 192 modified and an Integer Overflow exception occurs. */ 193 TEST1("dsub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 194 t0, t1, t2); 195 break; 196 197 case DSUBU: 198 /* No Integer Overflow exception occurs under any 199 circumstances. */ 200 TEST1("dsubu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 201 t0, t1, t2); 202 TEST1("dsubu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], 203 s0, s1, s2); 204 break; 205 206 case MADD: 207 /* If GPRs rs or rt do not contain sign-extended 32-bit 208 values (bits 63..31 equal), then the results of the operation 209 are UNPREDICTABLE. */ 210 TEST5("madd $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 211 break; 212 213 case MADDU: 214 /* If GPRs rs or rt do not contain sign-extended 32-bit 215 values (bits 63..31 equal), then the results of the operation 216 are UNPREDICTABLE. */ 217 TEST5("maddu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 218 break; 219 220 case MSUB: 221 /* If GPR rs or rt do not contain a sign-extended 32-bit 222 value (bits 63..31 equal), then the results of the operation 223 are UNPREDICTABLE. */ 224 TEST5("msub $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 225 break; 226 227 case MSUBU: 228 /* If GPRs rs or rt do not contain sign-extended 32-bit 229 values (bits 63..31 equal), then the results of the operation 230 are UNPREDICTABLE. 231 This instruction does not provide the capability of writing 232 directly to a target GPR. */ 233 TEST5("msubu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 234 break; 235 236 case MUL: 237 /* On 64-bit processors, if either GPR rt or GPR rs does not 238 contain sign-extended 32-bit values (bits 63..31 equal), then 239 the result of the operation is UNPREDICTABLE. */ 240 TEST1("mul $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 241 t0, t1, t2); 242 break; 243 244 case MULT: 245 /* On 64-bit processors, if either GPR rt or GPR rs does not 246 contain sign-extended 32-bit values (bits 63..31 equal), then 247 the result of the operation is UNPREDICTABLE. */ 248 TEST4("mult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 249 break; 250 251 case MULTU: 252 /* On 64-bit processors, if either GPR rt or GPR rs does not 253 contain sign-extended 32-bit values (bits 63..31 equal), then 254 the result of the operation is UNPREDICTABLE. */ 255 TEST4("multu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1); 256 break; 257 258 case MOVN: 259 /* The arithmetic comparison does not cause an Integer Overflow 260 exception. */ 261 TEST1("movn $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 262 t0, t1, t2); 263 TEST1("movn $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], 264 s0, s1, s2); 265 break; 266 267 case MOVZ: 268 /* The arithmetic comparison does not cause an Integer Overflow 269 exception. */ 270 TEST1("movz $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 271 t0, t1, t2); 272 TEST1("movz $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], 273 s0, s1, s2); 274 break; 275 276 case SEB: 277 #if (__mips==64) && (__mips_isa_rev>=2) 278 /* If GPR rt does not contain a sign-extended 32-bit 279 value (bits 63..31 equal), then the result of the operation 280 is UNPREDICTABLE. */ 281 TEST3("seb $t0, $t1", reg_val1[i], t0, t1); 282 #endif 283 break; 284 285 case SEH: 286 #if (__mips==64) && (__mips_isa_rev>=2) 287 /* If GPR rt does not contain a sign-extended 32-bit 288 value (bits 63..31 equal), then the result of the operation 289 is UNPREDICTABLE. */ 290 TEST3("seh $t0, $t1", reg_val1[i], t0, t1); 291 #endif 292 break; 293 294 case SLT: 295 /* The arithmetic comparison does not cause an Integer Overflow 296 exception. */ 297 TEST1("slt $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 298 t0, t1, t2); 299 break; 300 301 case SLTI: 302 /* The arithmetic comparison does not cause an Integer Overflow 303 exception. */ 304 TEST2("slti $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 305 TEST2("slti $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 306 TEST2("slti $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 307 TEST2("slti $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); 308 TEST2("slti $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); 309 TEST2("slti $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); 310 TEST2("slti $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); 311 TEST2("slti $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); 312 break; 313 314 case SLTIU: 315 /* The arithmetic comparison does not cause an Integer Overflow 316 exception. */ 317 TEST2("sltiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1); 318 TEST2("sltiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3); 319 TEST2("sltiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1); 320 TEST2("sltiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1); 321 TEST2("sltiu $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1); 322 TEST2("sltiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3); 323 TEST2("sltiu $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1); 324 TEST2("sltiu $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1); 325 break; 326 327 case SLTU: 328 /* The arithmetic comparison does not cause an Integer Overflow 329 exception. */ 330 TEST1("sltu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 331 t0, t1, t2); 332 TEST1("sltu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1], 333 s0, s1, s2); 334 break; 335 336 case SUB: 337 /* On 64-bit processors, if either GPR rt or GPR rs does not 338 contain sign-extended 32-bit values (bits 63..31 equal), then 339 the result of the operation is UNPREDICTABLE. */ 340 if (i < 8 || (i > 15 && i < 22)) 341 TEST1("sub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 342 t0, t1, t2); 343 break; 344 345 case SUBU: 346 /* On 64-bit processors, if either GPR rt or GPR rs does not 347 contain sign-extended 32-bit values (bits 63..31 equal), then 348 the result of the operation is UNPREDICTABLE. */ 349 TEST1("subu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1], 350 t0, t1, t2); 351 break; 352 353 default: 354 printf("Error!\n"); 355 break; 356 } 357 } 358 } 359 return 0; 360 } 361
