| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/Transforms/InstCombine/ |
| InstCombineWorklist.h | 60 DEBUG(dbgs() << "IC: ADDING: " << List.size() << " instrs to worklist\n");
|
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/Transforms/InstCombine/ |
| InstCombineWorklist.h | 60 DEBUG(dbgs() << "IC: ADDING: " << List.size() << " instrs to worklist\n");
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedVulcan.td | 240 def : InstRW<[WriteI], (instrs COPY)>;
412 def : InstRW<[VulcanWrite_23Cyc_F01], (instrs FDIVDrr, FSQRTDr)>;
441 def : InstRW<[VulcanWrite_5Cyc_F01], (instrs FMOVXDHighr, FMOVDXHighr)>;
488 def : InstRW<[VulcanWrite_5Cyc_F01], (instrs PMULLv8i8, PMULLv16i8)>;
519 def : InstRW<[VulcanWrite_16Cyc_F01], (instrs FDIVv2f32)>;
522 def : InstRW<[VulcanWrite_16Cyc_F01], (instrs FDIVv4f32)>;
525 def : InstRW<[VulcanWrite_23Cyc_F01], (instrs FDIVv2f64)>;
839 def : InstRW<[VulcanWrite_5Cyc_F1], (instrs PMULLv1i64, PMULLv2i64)>;
|
| /external/llvm/utils/TableGen/ |
| CodeGenSchedule.cpp | 34 // (instrs a, b, ...) Evaluate and union all arguments. Identical to AddOp.
45 // instruction names using lower_bound. Note that the predefined instrs must be
86 Sets.addFieldExpander("InstRW", "Instrs");
89 // (instrs Op1, Op1...)
90 Sets.addOperator("instrs", llvm::make_unique<InstrsOp>());
673 // ClassInstrs will hold an entry for each subset of Instrs in InstRWDef that
674 // intersects with an existing class via a previous InstRWDef. Instrs that do
678 // Sort Instrs into sets.
699 // For each set of Instrs, create a new class if necessary, and map or remap
700 // the Instrs to it
[all...] |
| AsmWriterEmitter.cpp | 216 std::string Instrs = InstrsForCase[i];
217 if (Instrs.size() > 70) {
218 Instrs.erase(Instrs.begin()+70, Instrs.end());
219 Instrs += "...";
222 if (!Instrs.empty())
223 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
[all...] |
| /external/mesa3d/src/compiler/spirv/ |
| spirv_to_nir.c | 1706 nir_tex_instr *instrs[4] = {instr, NULL, NULL, NULL}; local
[all...] |
| /external/llvm/lib/CodeGen/ |
| MachineCombiner.cpp | 80 void instr2instrSC(SmallVectorImpl<MachineInstr *> &Instrs,
292 SmallVectorImpl<MachineInstr *> &Instrs,
294 for (auto *InstrPtr : Instrs) {
|
| /toolchain/binutils/binutils-2.27/include/opcode/ |
| sparc.h | 171 #define HWCAP2_FJATHHPC 0x00001000 /* Fujitsu HPC instrs */
172 #define HWCAP2_FJDES 0x00002000 /* Fujitsu DES instrs */
173 #define HWCAP2_FJAES 0x00010000 /* Fujitsu AES instrs */
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| AsmWriterEmitter.cpp | 206 std::string Instrs = InstrsForCase[i];
207 if (Instrs.size() > 70) {
208 Instrs.erase(Instrs.begin()+70, Instrs.end());
209 Instrs += "...";
212 if (!Instrs.empty())
213 UniqueOperandCommands[i] = " // " + Instrs + "\n" +
[all...] |
| /external/llvm/include/llvm/IR/ |
| Instruction.def | 149 HANDLE_MEMORY_INST(30, Load , LoadInst ) // Memory manipulation instrs
|
| /external/llvm/include/llvm/Transforms/Vectorize/ |
| SLPVectorizer.h | 74 /// \brief Try to vectorize a chain that starts at two arithmetic instrs.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 108 /// (which do not go into the machine instrs.)
|
| /external/mesa3d/src/gallium/drivers/freedreno/a2xx/ |
| ir-a2xx.c | 105 struct ir2_instruction *instr = cf->exec.instrs[j];
173 ret = instr_emit(cf->exec.instrs[j], ptr, idx++, info);
267 assert(cf->exec.instrs_count < ARRAY_SIZE(cf->exec.instrs));
268 cf->exec.instrs[cf->exec.instrs_count++] = instr;
|
| /external/swiftshader/third_party/LLVM/include/llvm/ |
| Instruction.def | 134 HANDLE_MEMORY_INST(28, Load , LoadInst ) // Memory manipulation instrs
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.h | 105 /// (which do not go into the machine instrs.)
|
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| IRBuilder.cpp | 1 //===---- IRBuilder.cpp - Builder for LLVM Instrs -------------------------===//
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| pr3495.ll | 3 ; RUN: llc < %s -march=x86 -stats -regalloc=linearscan -enable-lsr-nested |& grep {Number of machine instrs printed} | grep 34
|
| /external/swiftshader/third_party/llvm-subzero/include/llvm/IR/ |
| Instruction.def | 149 HANDLE_MEMORY_INST(30, Load , LoadInst ) // Memory manipulation instrs
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/IR/ |
| Instruction.def | 149 HANDLE_MEMORY_INST(30, Load , LoadInst ) // Memory manipulation instrs
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Transforms/Vectorize/ |
| SLPVectorizer.h | 74 /// \brief Try to vectorize a chain that starts at two arithmetic instrs.
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/IR/ |
| Instruction.def | 153 HANDLE_MEMORY_INST(30, Load , LoadInst ) // Memory manipulation instrs
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/Transforms/Vectorize/ |
| SLPVectorizer.h | 76 /// \brief Try to vectorize a chain that starts at two arithmetic instrs.
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/IR/ |
| Instruction.def | 153 HANDLE_MEMORY_INST(30, Load , LoadInst ) // Memory manipulation instrs
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/Transforms/Vectorize/ |
| SLPVectorizer.h | 76 /// \brief Try to vectorize a chain that starts at two arithmetic instrs.
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/IR/ |
| Instruction.def | 153 HANDLE_MEMORY_INST(30, Load , LoadInst ) // Memory manipulation instrs
|
