1 //===---- InstrEmitter.h - Emit MachineInstrs for the SelectionDAG class ---==// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This declares the Emit routines for the SelectionDAG class, which creates 11 // MachineInstrs based on the decisions of the SelectionDAG instruction 12 // selection. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef INSTREMITTER_H 17 #define INSTREMITTER_H 18 19 #include "llvm/CodeGen/SelectionDAG.h" 20 #include "llvm/CodeGen/MachineBasicBlock.h" 21 #include "llvm/ADT/DenseMap.h" 22 23 namespace llvm { 24 25 class MCInstrDesc; 26 class SDDbgValue; 27 28 class InstrEmitter { 29 MachineFunction *MF; 30 MachineRegisterInfo *MRI; 31 const TargetMachine *TM; 32 const TargetInstrInfo *TII; 33 const TargetRegisterInfo *TRI; 34 const TargetLowering *TLI; 35 36 MachineBasicBlock *MBB; 37 MachineBasicBlock::iterator InsertPos; 38 39 /// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an 40 /// implicit physical register output. 41 void EmitCopyFromReg(SDNode *Node, unsigned ResNo, 42 bool IsClone, bool IsCloned, 43 unsigned SrcReg, 44 DenseMap<SDValue, unsigned> &VRBaseMap); 45 46 /// getDstOfCopyToRegUse - If the only use of the specified result number of 47 /// node is a CopyToReg, return its destination register. Return 0 otherwise. 48 unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, 49 unsigned ResNo) const; 50 51 void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI, 52 const MCInstrDesc &II, 53 bool IsClone, bool IsCloned, 54 DenseMap<SDValue, unsigned> &VRBaseMap); 55 56 /// getVR - Return the virtual register corresponding to the specified result 57 /// of the specified node. 58 unsigned getVR(SDValue Op, 59 DenseMap<SDValue, unsigned> &VRBaseMap); 60 61 /// AddRegisterOperand - Add the specified register as an operand to the 62 /// specified machine instr. Insert register copies if the register is 63 /// not in the required register class. 64 void AddRegisterOperand(MachineInstr *MI, SDValue Op, 65 unsigned IIOpNum, 66 const MCInstrDesc *II, 67 DenseMap<SDValue, unsigned> &VRBaseMap, 68 bool IsDebug, bool IsClone, bool IsCloned); 69 70 /// AddOperand - Add the specified operand to the specified machine instr. II 71 /// specifies the instruction information for the node, and IIOpNum is the 72 /// operand number (in the II) that we are adding. IIOpNum and II are used for 73 /// assertions only. 74 void AddOperand(MachineInstr *MI, SDValue Op, 75 unsigned IIOpNum, 76 const MCInstrDesc *II, 77 DenseMap<SDValue, unsigned> &VRBaseMap, 78 bool IsDebug, bool IsClone, bool IsCloned); 79 80 /// ConstrainForSubReg - Try to constrain VReg to a register class that 81 /// supports SubIdx sub-registers. Emit a copy if that isn't possible. 82 /// Return the virtual register to use. 83 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx, 84 EVT VT, DebugLoc DL); 85 86 /// EmitSubregNode - Generate machine code for subreg nodes. 87 /// 88 void EmitSubregNode(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, 89 bool IsClone, bool IsCloned); 90 91 /// EmitCopyToRegClassNode - Generate machine code for COPY_TO_REGCLASS nodes. 92 /// COPY_TO_REGCLASS is just a normal copy, except that the destination 93 /// register is constrained to be in a particular register class. 94 /// 95 void EmitCopyToRegClassNode(SDNode *Node, 96 DenseMap<SDValue, unsigned> &VRBaseMap); 97 98 /// EmitRegSequence - Generate machine code for REG_SEQUENCE nodes. 99 /// 100 void EmitRegSequence(SDNode *Node, DenseMap<SDValue, unsigned> &VRBaseMap, 101 bool IsClone, bool IsCloned); 102 public: 103 /// CountResults - The results of target nodes have register or immediate 104 /// operands first, then an optional chain, and optional flag operands 105 /// (which do not go into the machine instrs.) 106 static unsigned CountResults(SDNode *Node); 107 108 /// CountOperands - The inputs to target nodes have any actual inputs first, 109 /// followed by an optional chain operand, then flag operands. Compute 110 /// the number of actual operands that will go into the resulting 111 /// MachineInstr. 112 static unsigned CountOperands(SDNode *Node); 113 114 /// EmitDbgValue - Generate machine instruction for a dbg_value node. 115 /// 116 MachineInstr *EmitDbgValue(SDDbgValue *SD, 117 DenseMap<SDValue, unsigned> &VRBaseMap); 118 119 /// EmitNode - Generate machine code for a node and needed dependencies. 120 /// 121 void EmitNode(SDNode *Node, bool IsClone, bool IsCloned, 122 DenseMap<SDValue, unsigned> &VRBaseMap) { 123 if (Node->isMachineOpcode()) 124 EmitMachineNode(Node, IsClone, IsCloned, VRBaseMap); 125 else 126 EmitSpecialNode(Node, IsClone, IsCloned, VRBaseMap); 127 } 128 129 /// getBlock - Return the current basic block. 130 MachineBasicBlock *getBlock() { return MBB; } 131 132 /// getInsertPos - Return the current insertion position. 133 MachineBasicBlock::iterator getInsertPos() { return InsertPos; } 134 135 /// InstrEmitter - Construct an InstrEmitter and set it to start inserting 136 /// at the given position in the given block. 137 InstrEmitter(MachineBasicBlock *mbb, MachineBasicBlock::iterator insertpos); 138 139 private: 140 void EmitMachineNode(SDNode *Node, bool IsClone, bool IsCloned, 141 DenseMap<SDValue, unsigned> &VRBaseMap); 142 void EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, 143 DenseMap<SDValue, unsigned> &VRBaseMap); 144 }; 145 146 } 147 148 #endif 149
