| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/testdata/ |
| cases.txt | 112 36ffdf08| gnu ldarb w22, [x25] [all...] |
| /external/vixl/test/aarch64/ |
| test-trace-aarch64.cc | 154 __ ldarb(w5, MemOperand(x0)); 155 __ ldarb(x6, MemOperand(x0)); [all...] |
| /external/capstone/arch/AArch64/ |
| AArch64GenAsmWriter.inc | 948 26485304U, // LDARB [all...] |
| AArch64Mapping.c | [all...] |
| AArch64GenDisassemblerTables.inc | 52 /* 94 */ MCD_OPC_Decode, 163, 7, 0, // Opcode: LDARB [all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | 1723 void Assembler::ldarb(const Register& rt, const Register& rn) { function in class:v8::internal::Assembler [all...] |
| assembler-arm64.h | [all...] |
| /external/valgrind/none/tests/arm64/ |
| memory.c | 279 TESTINST2_hide2("ldarb w21, [x22]", AREA_MID, x21,x22,0); [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| assembler-aarch64.cc | 1372 void Assembler::ldarb(const Register& rt, const MemOperand& src) { function in class:vixl::aarch64::Assembler [all...] |
| disasm-aarch64.cc | [all...] |
| /art/compiler/optimizing/ |
| code_generator_arm64.cc | [all...] |
| /external/vixl/test/test-trace-reference/ |
| log-disasm | 100 0x~~~~~~~~~~~~~~~~ 08dffc05 ldarb w5, [x0] 101 0x~~~~~~~~~~~~~~~~ 08dffc06 ldarb w6, [x0] [all...] |
| log-disasm-colour | 100 0x~~~~~~~~~~~~~~~~ 08dffc05 ldarb w5, [x0] 101 0x~~~~~~~~~~~~~~~~ 08dffc06 ldarb w6, [x0] [all...] |
| log-all | 264 0x~~~~~~~~~~~~~~~~ 08dffc05 ldarb w5, [x0] 266 0x~~~~~~~~~~~~~~~~ 08dffc06 ldarb w6, [x0] [all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| aarch64-dis-2.c | 559 ldarb. */ [all...] |
| aarch64-tbl.h | [all...] |
| /prebuilts/go/darwin-x86/pkg/darwin_amd64/cmd/vendor/golang.org/x/arch/arm64/ |
| arm64asm.a | 147 ADDHN2 @%ADDP @%ADDS @%ADDV @%ADR @%ADRP @%AESD @%AESE @%AESIMC @% AESMC @%AND @% ANDS @%"ASR @%|SASRV @%&AT @%(B @%*BFI @%,BFM @%. BFXIL @%0BIC @%2BICS @%4BIF @%6BIT @%8BL @%:BLR @%<BR @%>BRK @%@BSL @%BCBNZ @%DCBZ @%FCCMN @%HCCMP @%JCINC @%LCINV @%N CLREX @%PCLS @%RCLZ @%TCMEQ @%VCMGE @%XCMGT @%ZCMHI @%\CMHS @%^CMLE @%`CMLT @%bCMN @%dCMP @%f CMTST @%hCNEG @%jCNT @%lCRC32B @%n
CRC32CB @%p
CRC32CH @%r
CRC32CW @%t
CRC32CX @%vCRC32H @%xCRC32W @%zCRC32X @%||CSEL @%~CSET @%? CSETM @%? CSINC @%? CSINV @%? CSNEG @%?DC @%? DCPS1 @%? DCPS2 @%? DCPS3 @%?DMB @%?DRPS @%?DSB @%?DUP @%?EON @%?EOR @%?ERET @%?EXT @%?EXTR @%?FABD @%?FABS @%? FACGE @%? FACGT @%?FADD @%? FADDP @%? FCCMP @%?FCCMPE @%? FCMEQ @%? FCMGE @%? FCMGT @%? FCMLE @%? FCMLT @%?FCMP @%? FCMPE @%? FCSEL @%?FCVT @%?FCVTAS @%?FCVTAU @%? FCVTL @%?FCVTL2 @%?FCVTMS @%?FCVTMU @%? FCVTN @%?FCVTN2 @%?FCVTNS @%?FCVTNU @%?FCVTPS @%?FCVTPU @%?FCVTXN @%?
FCVTXN2 @%?FCVTZS @%?FCVTZU @%?FDIV @%? FMADD @%?FMAX @%?FMAXNM @%?
FMAXNMP @%?
FMAXNMV @%? FMAXP @%? FMAXV @%?FMIN @%?FMINNM @%?
FMINNMP @%?
FMINNMV @%? FMINP @%? FMINV @%?FMLA @%?FMLS @%?FMOV @%? FMSUB @%?FMUL @%? FMULX @%?FNEG @%?FNMADD @%?FNMSUB @%? FNMUL @%?FRECPE @%?FRECPS @%?FRECPX @%?FRINTA @%?FRINTI @%?FRINTM @%?FRINTN @%?FRINTP @%?FRINTX @%?FRINTZ @%?
FRSQRTE @%?
FRSQRTS @%? FSQRT @%?FSUB @%?HINT @%?HLT @%?HVC @%?IC @%?INS @%?ISB @%?LD1 @%?LD1R @%?LD2 @%?LD2R @%?LD3 @%?LD3R @%?LD4 @%?LD4R @%?LDAR @%? LDARB |