| /external/tremolo/Tremolo/ |
| mdctARM.s | 1006 LDRB r7, [r6, r4, LSR #6]
1008 LDRB r8, [r6, r8]
[all...] |
| /external/vixl/src/aarch32/ |
| disasm-aarch32.h | 836 void ldrb(Condition cond,
841 void ldrb(Condition cond, Register rt, Location* location);
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| Arm64Assembler.cpp | 645 void ArmToArm64Assembler::LDRB(int cc, int Rd, int Rn, uint32_t op_type)
989 "LDR","LDRB","LDRH","STR","STRB","STRH"
[all...] |
| /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/ |
| tegra_helpers.S | 277 ldrb w3, [x1], #1
|
| /external/boringssl/src/crypto/fipsmodule/aes/asm/ |
| bsaes-armv7.pl | [all...] |
| /external/libxaac/decoder/armv7/ |
| ixheaacd_mps_complex_fft_64_asm.s | 27 LDRB r10, [r12, r0, LSR #2]
|
| /external/llvm/lib/Target/ARM/ |
| ARMScheduleSwift.td | 341 (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
[all...] |
| /external/llvm/test/Transforms/LoopStrengthReduce/ARM/ |
| ivchain-ARM.ll | 142 ; A9: ldrb{{(.w)?}} {{r[0-9]|lr}}, [{{r[0-9]|lr}}, #3]
|
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerARM32.h | 753 // Emit ldr/ldrb/str/strb instruction with given address.
[all...] |
| /prebuilts/vndk/v27/arm64/arch-arm-armv7-a-neon/shared/vndk-core/ |
| libvixl-arm64.so | |
| /art/runtime/arch/arm/ |
| quick_entrypoints_arm.S | 634 ldrb r4, [r4, #0] @ load return type
[all...] |
| /external/boringssl/src/crypto/curve25519/asm/ |
| x25519-asm-arm.S | 74 ldrb r6,[r1] label
77 ldrb r6,[r1,#31] label
233 ldrb r2,[r1,r2] label
[all...] |
| /external/v8/src/compiler/arm/ |
| code-generator-arm.cc | [all...] |
| /external/libjpeg-turbo/simd/ |
| jsimd_arm64_neon.S | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| inst.json | 158 {"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
159 {"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
160 {"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
161 {"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Extended register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
162 {"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"Shifted register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""}
[all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| inst.json | 158 {"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|0|1|Rn:5|Rt:5","Arch":"Post-index Post-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>], #<simm>","Code":"","Alias":""},
159 {"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|0|0|1|0|imm9:9|1|1|Rn:5|Rt:5","Arch":"Pre-index Pre-index variant","Syntax":"LDRB <Wt>, [<Xn|SP>, #<simm>]!","Code":"","Alias":""},
160 {"Name":"LDRB (immediate)","Bits":"0|0|1|1|1|0|0|1|0|1|imm12:12|Rn:5|Rt:5","Arch":"Unsigned offset Unsigned offset variant","Syntax":"LDRB <Wt>, [<Xn|SP>{, #<pimm>}]","Code":"","Alias":""},
161 {"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|option:3|S|1|0|Rn:5|Rt:5","Arch":"Extended register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}]","Code":"","Alias":""},
162 {"Name":"LDRB (register)","Bits":"0|0|1|1|1|0|0|0|0|1|1|Rm:5|011:3|S|1|0|Rn:5|Rt:5","Arch":"Shifted register variant","Syntax":"LDRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}]","Code":"","Alias":""}
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrThumb2.td | [all...] |
| /external/vixl/test/test-trace-reference/ |
| log-disasm | 129 0x~~~~~~~~~~~~~~~~ 39400003 ldrb w3, [x0]
130 0x~~~~~~~~~~~~~~~~ 38401423 ldrb w3, [x1], #1
131 0x~~~~~~~~~~~~~~~~ 38401c23 ldrb w3, [x1, #1]!
132 0x~~~~~~~~~~~~~~~~ 39400004 ldrb w4, [x0]
133 0x~~~~~~~~~~~~~~~~ 38401424 ldrb w4, [x1], #1
134 0x~~~~~~~~~~~~~~~~ 38401c24 ldrb w4, [x1, #1]!
[all...] |
| log-disasm-colour | 129 0x~~~~~~~~~~~~~~~~ 39400003 ldrb w3, [x0]
130 0x~~~~~~~~~~~~~~~~ 38401423 ldrb w3, [x1], #1
131 0x~~~~~~~~~~~~~~~~ 38401c23 ldrb w3, [x1, #1]!
132 0x~~~~~~~~~~~~~~~~ 39400004 ldrb w4, [x0]
133 0x~~~~~~~~~~~~~~~~ 38401424 ldrb w4, [x1], #1
134 0x~~~~~~~~~~~~~~~~ 38401c24 ldrb w4, [x1, #1]!
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| aarch64-dis-2.c | [all...] |
| aarch64-opc.c | [all...] |
| aarch64-tbl.h | [all...] |
| /external/swiftshader/third_party/subzero/src/DartARM32/ |
| assembler_arm.h | 561 void ldrb(Register rd, Address ad, Condition cond = AL);
[all...] |
| /external/v8/src/arm64/ |
| disasm-arm64.cc | 747 V(LDRB_w, "ldrb", "'Wt") \
[all...] |
| macro-assembler-arm64-inl.h | [all...] |
