1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Thumb2 instruction set. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // IT block predicate field 15 def it_pred_asmoperand : AsmOperandClass { 16 let Name = "ITCondCode"; 17 let ParserMethod = "parseITCondCode"; 18 } 19 def it_pred : Operand<i32> { 20 let PrintMethod = "printMandatoryPredicateOperand"; 21 let ParserMatchClass = it_pred_asmoperand; 22 } 23 24 // IT block condition mask 25 def it_mask_asmoperand : AsmOperandClass { let Name = "ITMask"; } 26 def it_mask : Operand<i32> { 27 let PrintMethod = "printThumbITMask"; 28 let ParserMatchClass = it_mask_asmoperand; 29 } 30 31 // t2_shift_imm: An integer that encodes a shift amount and the type of shift 32 // (asr or lsl). The 6-bit immediate encodes as: 33 // {5} 0 ==> lsl 34 // 1 asr 35 // {4-0} imm5 shift amount. 36 // asr #32 not allowed 37 def t2_shift_imm : Operand<i32> { 38 let PrintMethod = "printShiftImmOperand"; 39 let ParserMatchClass = ShifterImmAsmOperand; 40 let DecoderMethod = "DecodeT2ShifterImmOperand"; 41 } 42 43 // Shifted operands. No register controlled shifts for Thumb2. 44 // Note: We do not support rrx shifted operands yet. 45 def t2_so_reg : Operand<i32>, // reg imm 46 ComplexPattern<i32, 2, "SelectT2ShifterOperandReg", 47 [shl,srl,sra,rotr]> { 48 let EncoderMethod = "getT2SORegOpValue"; 49 let PrintMethod = "printT2SOOperand"; 50 let DecoderMethod = "DecodeSORegImmOperand"; 51 let ParserMatchClass = ShiftedImmAsmOperand; 52 let MIOperandInfo = (ops rGPR, i32imm); 53 } 54 55 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value 56 def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{ 57 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 58 }]>; 59 60 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value 61 def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{ 62 return CurDAG->getTargetConstant(-((int)N->getZExtValue()), MVT::i32); 63 }]>; 64 65 // t2_so_imm - Match a 32-bit immediate operand, which is an 66 // 8-bit immediate rotated by an arbitrary number of bits, or an 8-bit 67 // immediate splatted into multiple bytes of the word. 68 def t2_so_imm_asmoperand : AsmOperandClass { let Name = "T2SOImm"; } 69 def t2_so_imm : Operand<i32>, ImmLeaf<i32, [{ 70 return ARM_AM::getT2SOImmVal(Imm) != -1; 71 }]> { 72 let ParserMatchClass = t2_so_imm_asmoperand; 73 let EncoderMethod = "getT2SOImmOpValue"; 74 let DecoderMethod = "DecodeT2SOImm"; 75 } 76 77 // t2_so_imm_not - Match an immediate that is a complement 78 // of a t2_so_imm. 79 def t2_so_imm_not : Operand<i32>, 80 PatLeaf<(imm), [{ 81 return ARM_AM::getT2SOImmVal(~((uint32_t)N->getZExtValue())) != -1; 82 }], t2_so_imm_not_XFORM>; 83 84 // t2_so_imm_neg - Match an immediate that is a negation of a t2_so_imm. 85 def t2_so_imm_neg : Operand<i32>, 86 PatLeaf<(imm), [{ 87 return ARM_AM::getT2SOImmVal(-((uint32_t)N->getZExtValue())) != -1; 88 }], t2_so_imm_neg_XFORM>; 89 90 /// imm0_4095 predicate - True if the 32-bit immediate is in the range [0.4095]. 91 def imm0_4095 : Operand<i32>, 92 ImmLeaf<i32, [{ 93 return Imm >= 0 && Imm < 4096; 94 }]>; 95 96 def imm0_4095_neg : PatLeaf<(i32 imm), [{ 97 return (uint32_t)(-N->getZExtValue()) < 4096; 98 }], imm_neg_XFORM>; 99 100 def imm0_255_neg : PatLeaf<(i32 imm), [{ 101 return (uint32_t)(-N->getZExtValue()) < 255; 102 }], imm_neg_XFORM>; 103 104 def imm0_255_not : PatLeaf<(i32 imm), [{ 105 return (uint32_t)(~N->getZExtValue()) < 255; 106 }], imm_comp_XFORM>; 107 108 def lo5AllOne : PatLeaf<(i32 imm), [{ 109 // Returns true if all low 5-bits are 1. 110 return (((uint32_t)N->getZExtValue()) & 0x1FUL) == 0x1FUL; 111 }]>; 112 113 // Define Thumb2 specific addressing modes. 114 115 // t2addrmode_imm12 := reg + imm12 116 def t2addrmode_imm12_asmoperand : AsmOperandClass {let Name="MemUImm12Offset";} 117 def t2addrmode_imm12 : Operand<i32>, 118 ComplexPattern<i32, 2, "SelectT2AddrModeImm12", []> { 119 let PrintMethod = "printAddrModeImm12Operand"; 120 let EncoderMethod = "getAddrModeImm12OpValue"; 121 let DecoderMethod = "DecodeT2AddrModeImm12"; 122 let ParserMatchClass = t2addrmode_imm12_asmoperand; 123 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 124 } 125 126 // t2ldrlabel := imm12 127 def t2ldrlabel : Operand<i32> { 128 let EncoderMethod = "getAddrModeImm12OpValue"; 129 let PrintMethod = "printT2LdrLabelOperand"; 130 } 131 132 133 // ADR instruction labels. 134 def t2adrlabel : Operand<i32> { 135 let EncoderMethod = "getT2AdrLabelOpValue"; 136 } 137 138 139 // t2addrmode_posimm8 := reg + imm8 140 def MemPosImm8OffsetAsmOperand : AsmOperandClass {let Name="MemPosImm8Offset";} 141 def t2addrmode_posimm8 : Operand<i32> { 142 let PrintMethod = "printT2AddrModeImm8Operand"; 143 let EncoderMethod = "getT2AddrModeImm8OpValue"; 144 let DecoderMethod = "DecodeT2AddrModeImm8"; 145 let ParserMatchClass = MemPosImm8OffsetAsmOperand; 146 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 147 } 148 149 // t2addrmode_negimm8 := reg - imm8 150 def MemNegImm8OffsetAsmOperand : AsmOperandClass {let Name="MemNegImm8Offset";} 151 def t2addrmode_negimm8 : Operand<i32>, 152 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 153 let PrintMethod = "printT2AddrModeImm8Operand"; 154 let EncoderMethod = "getT2AddrModeImm8OpValue"; 155 let DecoderMethod = "DecodeT2AddrModeImm8"; 156 let ParserMatchClass = MemNegImm8OffsetAsmOperand; 157 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 158 } 159 160 // t2addrmode_imm8 := reg +/- imm8 161 def MemImm8OffsetAsmOperand : AsmOperandClass { let Name = "MemImm8Offset"; } 162 def t2addrmode_imm8 : Operand<i32>, 163 ComplexPattern<i32, 2, "SelectT2AddrModeImm8", []> { 164 let PrintMethod = "printT2AddrModeImm8Operand"; 165 let EncoderMethod = "getT2AddrModeImm8OpValue"; 166 let DecoderMethod = "DecodeT2AddrModeImm8"; 167 let ParserMatchClass = MemImm8OffsetAsmOperand; 168 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 169 } 170 171 def t2am_imm8_offset : Operand<i32>, 172 ComplexPattern<i32, 1, "SelectT2AddrModeImm8Offset", 173 [], [SDNPWantRoot]> { 174 let PrintMethod = "printT2AddrModeImm8OffsetOperand"; 175 let EncoderMethod = "getT2AddrModeImm8OffsetOpValue"; 176 let DecoderMethod = "DecodeT2Imm8"; 177 } 178 179 // t2addrmode_imm8s4 := reg +/- (imm8 << 2) 180 def MemImm8s4OffsetAsmOperand : AsmOperandClass {let Name = "MemImm8s4Offset";} 181 def t2addrmode_imm8s4 : Operand<i32> { 182 let PrintMethod = "printT2AddrModeImm8s4Operand"; 183 let EncoderMethod = "getT2AddrModeImm8s4OpValue"; 184 let DecoderMethod = "DecodeT2AddrModeImm8s4"; 185 let ParserMatchClass = MemImm8s4OffsetAsmOperand; 186 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 187 } 188 189 def t2am_imm8s4_offset_asmoperand : AsmOperandClass { let Name = "Imm8s4"; } 190 def t2am_imm8s4_offset : Operand<i32> { 191 let PrintMethod = "printT2AddrModeImm8s4OffsetOperand"; 192 let EncoderMethod = "getT2Imm8s4OpValue"; 193 let DecoderMethod = "DecodeT2Imm8S4"; 194 } 195 196 // t2addrmode_imm0_1020s4 := reg + (imm8 << 2) 197 def MemImm0_1020s4OffsetAsmOperand : AsmOperandClass { 198 let Name = "MemImm0_1020s4Offset"; 199 } 200 def t2addrmode_imm0_1020s4 : Operand<i32> { 201 let PrintMethod = "printT2AddrModeImm0_1020s4Operand"; 202 let EncoderMethod = "getT2AddrModeImm0_1020s4OpValue"; 203 let DecoderMethod = "DecodeT2AddrModeImm0_1020s4"; 204 let ParserMatchClass = MemImm0_1020s4OffsetAsmOperand; 205 let MIOperandInfo = (ops GPRnopc:$base, i32imm:$offsimm); 206 } 207 208 // t2addrmode_so_reg := reg + (reg << imm2) 209 def t2addrmode_so_reg_asmoperand : AsmOperandClass {let Name="T2MemRegOffset";} 210 def t2addrmode_so_reg : Operand<i32>, 211 ComplexPattern<i32, 3, "SelectT2AddrModeSoReg", []> { 212 let PrintMethod = "printT2AddrModeSoRegOperand"; 213 let EncoderMethod = "getT2AddrModeSORegOpValue"; 214 let DecoderMethod = "DecodeT2AddrModeSOReg"; 215 let ParserMatchClass = t2addrmode_so_reg_asmoperand; 216 let MIOperandInfo = (ops GPR:$base, rGPR:$offsreg, i32imm:$offsimm); 217 } 218 219 // Addresses for the TBB/TBH instructions. 220 def addrmode_tbb_asmoperand : AsmOperandClass { let Name = "MemTBB"; } 221 def addrmode_tbb : Operand<i32> { 222 let PrintMethod = "printAddrModeTBB"; 223 let ParserMatchClass = addrmode_tbb_asmoperand; 224 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 225 } 226 def addrmode_tbh_asmoperand : AsmOperandClass { let Name = "MemTBH"; } 227 def addrmode_tbh : Operand<i32> { 228 let PrintMethod = "printAddrModeTBH"; 229 let ParserMatchClass = addrmode_tbh_asmoperand; 230 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm); 231 } 232 233 //===----------------------------------------------------------------------===// 234 // Multiclass helpers... 235 // 236 237 238 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin, 239 string opc, string asm, list<dag> pattern> 240 : T2I<oops, iops, itin, opc, asm, pattern> { 241 bits<4> Rd; 242 bits<12> imm; 243 244 let Inst{11-8} = Rd; 245 let Inst{26} = imm{11}; 246 let Inst{14-12} = imm{10-8}; 247 let Inst{7-0} = imm{7-0}; 248 } 249 250 251 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin, 252 string opc, string asm, list<dag> pattern> 253 : T2sI<oops, iops, itin, opc, asm, pattern> { 254 bits<4> Rd; 255 bits<4> Rn; 256 bits<12> imm; 257 258 let Inst{11-8} = Rd; 259 let Inst{26} = imm{11}; 260 let Inst{14-12} = imm{10-8}; 261 let Inst{7-0} = imm{7-0}; 262 } 263 264 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin, 265 string opc, string asm, list<dag> pattern> 266 : T2I<oops, iops, itin, opc, asm, pattern> { 267 bits<4> Rn; 268 bits<12> imm; 269 270 let Inst{19-16} = Rn; 271 let Inst{26} = imm{11}; 272 let Inst{14-12} = imm{10-8}; 273 let Inst{7-0} = imm{7-0}; 274 } 275 276 277 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 278 string opc, string asm, list<dag> pattern> 279 : T2I<oops, iops, itin, opc, asm, pattern> { 280 bits<4> Rd; 281 bits<12> ShiftedRm; 282 283 let Inst{11-8} = Rd; 284 let Inst{3-0} = ShiftedRm{3-0}; 285 let Inst{5-4} = ShiftedRm{6-5}; 286 let Inst{14-12} = ShiftedRm{11-9}; 287 let Inst{7-6} = ShiftedRm{8-7}; 288 } 289 290 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 291 string opc, string asm, list<dag> pattern> 292 : T2sI<oops, iops, itin, opc, asm, pattern> { 293 bits<4> Rd; 294 bits<12> ShiftedRm; 295 296 let Inst{11-8} = Rd; 297 let Inst{3-0} = ShiftedRm{3-0}; 298 let Inst{5-4} = ShiftedRm{6-5}; 299 let Inst{14-12} = ShiftedRm{11-9}; 300 let Inst{7-6} = ShiftedRm{8-7}; 301 } 302 303 class T2OneRegCmpShiftedReg<dag oops, dag iops, InstrItinClass itin, 304 string opc, string asm, list<dag> pattern> 305 : T2I<oops, iops, itin, opc, asm, pattern> { 306 bits<4> Rn; 307 bits<12> ShiftedRm; 308 309 let Inst{19-16} = Rn; 310 let Inst{3-0} = ShiftedRm{3-0}; 311 let Inst{5-4} = ShiftedRm{6-5}; 312 let Inst{14-12} = ShiftedRm{11-9}; 313 let Inst{7-6} = ShiftedRm{8-7}; 314 } 315 316 class T2TwoReg<dag oops, dag iops, InstrItinClass itin, 317 string opc, string asm, list<dag> pattern> 318 : T2I<oops, iops, itin, opc, asm, pattern> { 319 bits<4> Rd; 320 bits<4> Rm; 321 322 let Inst{11-8} = Rd; 323 let Inst{3-0} = Rm; 324 } 325 326 class T2sTwoReg<dag oops, dag iops, InstrItinClass itin, 327 string opc, string asm, list<dag> pattern> 328 : T2sI<oops, iops, itin, opc, asm, pattern> { 329 bits<4> Rd; 330 bits<4> Rm; 331 332 let Inst{11-8} = Rd; 333 let Inst{3-0} = Rm; 334 } 335 336 class T2TwoRegCmp<dag oops, dag iops, InstrItinClass itin, 337 string opc, string asm, list<dag> pattern> 338 : T2I<oops, iops, itin, opc, asm, pattern> { 339 bits<4> Rn; 340 bits<4> Rm; 341 342 let Inst{19-16} = Rn; 343 let Inst{3-0} = Rm; 344 } 345 346 347 class T2TwoRegImm<dag oops, dag iops, InstrItinClass itin, 348 string opc, string asm, list<dag> pattern> 349 : T2I<oops, iops, itin, opc, asm, pattern> { 350 bits<4> Rd; 351 bits<4> Rn; 352 bits<12> imm; 353 354 let Inst{11-8} = Rd; 355 let Inst{19-16} = Rn; 356 let Inst{26} = imm{11}; 357 let Inst{14-12} = imm{10-8}; 358 let Inst{7-0} = imm{7-0}; 359 } 360 361 class T2sTwoRegImm<dag oops, dag iops, InstrItinClass itin, 362 string opc, string asm, list<dag> pattern> 363 : T2sI<oops, iops, itin, opc, asm, pattern> { 364 bits<4> Rd; 365 bits<4> Rn; 366 bits<12> imm; 367 368 let Inst{11-8} = Rd; 369 let Inst{19-16} = Rn; 370 let Inst{26} = imm{11}; 371 let Inst{14-12} = imm{10-8}; 372 let Inst{7-0} = imm{7-0}; 373 } 374 375 class T2TwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 376 string opc, string asm, list<dag> pattern> 377 : T2I<oops, iops, itin, opc, asm, pattern> { 378 bits<4> Rd; 379 bits<4> Rm; 380 bits<5> imm; 381 382 let Inst{11-8} = Rd; 383 let Inst{3-0} = Rm; 384 let Inst{14-12} = imm{4-2}; 385 let Inst{7-6} = imm{1-0}; 386 } 387 388 class T2sTwoRegShiftImm<dag oops, dag iops, InstrItinClass itin, 389 string opc, string asm, list<dag> pattern> 390 : T2sI<oops, iops, itin, opc, asm, pattern> { 391 bits<4> Rd; 392 bits<4> Rm; 393 bits<5> imm; 394 395 let Inst{11-8} = Rd; 396 let Inst{3-0} = Rm; 397 let Inst{14-12} = imm{4-2}; 398 let Inst{7-6} = imm{1-0}; 399 } 400 401 class T2ThreeReg<dag oops, dag iops, InstrItinClass itin, 402 string opc, string asm, list<dag> pattern> 403 : T2I<oops, iops, itin, opc, asm, pattern> { 404 bits<4> Rd; 405 bits<4> Rn; 406 bits<4> Rm; 407 408 let Inst{11-8} = Rd; 409 let Inst{19-16} = Rn; 410 let Inst{3-0} = Rm; 411 } 412 413 class T2sThreeReg<dag oops, dag iops, InstrItinClass itin, 414 string opc, string asm, list<dag> pattern> 415 : T2sI<oops, iops, itin, opc, asm, pattern> { 416 bits<4> Rd; 417 bits<4> Rn; 418 bits<4> Rm; 419 420 let Inst{11-8} = Rd; 421 let Inst{19-16} = Rn; 422 let Inst{3-0} = Rm; 423 } 424 425 class T2TwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 426 string opc, string asm, list<dag> pattern> 427 : T2I<oops, iops, itin, opc, asm, pattern> { 428 bits<4> Rd; 429 bits<4> Rn; 430 bits<12> ShiftedRm; 431 432 let Inst{11-8} = Rd; 433 let Inst{19-16} = Rn; 434 let Inst{3-0} = ShiftedRm{3-0}; 435 let Inst{5-4} = ShiftedRm{6-5}; 436 let Inst{14-12} = ShiftedRm{11-9}; 437 let Inst{7-6} = ShiftedRm{8-7}; 438 } 439 440 class T2sTwoRegShiftedReg<dag oops, dag iops, InstrItinClass itin, 441 string opc, string asm, list<dag> pattern> 442 : T2sI<oops, iops, itin, opc, asm, pattern> { 443 bits<4> Rd; 444 bits<4> Rn; 445 bits<12> ShiftedRm; 446 447 let Inst{11-8} = Rd; 448 let Inst{19-16} = Rn; 449 let Inst{3-0} = ShiftedRm{3-0}; 450 let Inst{5-4} = ShiftedRm{6-5}; 451 let Inst{14-12} = ShiftedRm{11-9}; 452 let Inst{7-6} = ShiftedRm{8-7}; 453 } 454 455 class T2FourReg<dag oops, dag iops, InstrItinClass itin, 456 string opc, string asm, list<dag> pattern> 457 : T2I<oops, iops, itin, opc, asm, pattern> { 458 bits<4> Rd; 459 bits<4> Rn; 460 bits<4> Rm; 461 bits<4> Ra; 462 463 let Inst{19-16} = Rn; 464 let Inst{15-12} = Ra; 465 let Inst{11-8} = Rd; 466 let Inst{3-0} = Rm; 467 } 468 469 class T2MulLong<bits<3> opc22_20, bits<4> opc7_4, 470 dag oops, dag iops, InstrItinClass itin, 471 string opc, string asm, list<dag> pattern> 472 : T2I<oops, iops, itin, opc, asm, pattern> { 473 bits<4> RdLo; 474 bits<4> RdHi; 475 bits<4> Rn; 476 bits<4> Rm; 477 478 let Inst{31-23} = 0b111110111; 479 let Inst{22-20} = opc22_20; 480 let Inst{19-16} = Rn; 481 let Inst{15-12} = RdLo; 482 let Inst{11-8} = RdHi; 483 let Inst{7-4} = opc7_4; 484 let Inst{3-0} = Rm; 485 } 486 487 488 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 489 /// binary operation that produces a value. These are predicable and can be 490 /// changed to modify CPSR. 491 multiclass T2I_bin_irs<bits<4> opcod, string opc, 492 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 493 PatFrag opnode, string baseOpc, bit Commutable = 0, 494 string wide = ""> { 495 // shifted imm 496 def ri : T2sTwoRegImm< 497 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), iii, 498 opc, "\t$Rd, $Rn, $imm", 499 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_imm:$imm))]> { 500 let Inst{31-27} = 0b11110; 501 let Inst{25} = 0; 502 let Inst{24-21} = opcod; 503 let Inst{15} = 0; 504 } 505 // register 506 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), iir, 507 opc, !strconcat(wide, "\t$Rd, $Rn, $Rm"), 508 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { 509 let isCommutable = Commutable; 510 let Inst{31-27} = 0b11101; 511 let Inst{26-25} = 0b01; 512 let Inst{24-21} = opcod; 513 let Inst{14-12} = 0b000; // imm3 514 let Inst{7-6} = 0b00; // imm2 515 let Inst{5-4} = 0b00; // type 516 } 517 // shifted register 518 def rs : T2sTwoRegShiftedReg< 519 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), iis, 520 opc, !strconcat(wide, "\t$Rd, $Rn, $ShiftedRm"), 521 [(set rGPR:$Rd, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm))]> { 522 let Inst{31-27} = 0b11101; 523 let Inst{26-25} = 0b01; 524 let Inst{24-21} = opcod; 525 } 526 // Assembly aliases for optional destination operand when it's the same 527 // as the source operand. 528 def : t2InstAlias<!strconcat(opc, "${s}${p} $Rdn, $imm"), 529 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 530 t2_so_imm:$imm, pred:$p, 531 cc_out:$s)>; 532 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $Rm"), 533 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 534 rGPR:$Rm, pred:$p, 535 cc_out:$s)>; 536 def : t2InstAlias<!strconcat(opc, "${s}${p}", wide, " $Rdn, $shift"), 537 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn, 538 t2_so_reg:$shift, pred:$p, 539 cc_out:$s)>; 540 } 541 542 /// T2I_bin_w_irs - Same as T2I_bin_irs except these operations need 543 // the ".w" suffix to indicate that they are wide. 544 multiclass T2I_bin_w_irs<bits<4> opcod, string opc, 545 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 546 PatFrag opnode, string baseOpc, bit Commutable = 0> : 547 T2I_bin_irs<opcod, opc, iii, iir, iis, opnode, baseOpc, Commutable, ".w"> { 548 // Assembler aliases w/o the ".w" suffix. 549 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 550 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn, 551 rGPR:$Rm, pred:$p, 552 cc_out:$s)>; 553 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $shift"), 554 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rd, rGPR:$Rn, 555 t2_so_reg:$shift, pred:$p, 556 cc_out:$s)>; 557 558 // and with the optional destination operand, too. 559 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 560 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 561 rGPR:$Rm, pred:$p, 562 cc_out:$s)>; 563 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $shift"), 564 (!cast<Instruction>(!strconcat(baseOpc, "rs")) rGPR:$Rdn, rGPR:$Rdn, 565 t2_so_reg:$shift, pred:$p, 566 cc_out:$s)>; 567 } 568 569 /// T2I_rbin_is - Same as T2I_bin_irs except the order of operands are 570 /// reversed. The 'rr' form is only defined for the disassembler; for codegen 571 /// it is equivalent to the T2I_bin_irs counterpart. 572 multiclass T2I_rbin_irs<bits<4> opcod, string opc, PatFrag opnode> { 573 // shifted imm 574 def ri : T2sTwoRegImm< 575 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, 576 opc, ".w\t$Rd, $Rn, $imm", 577 [(set rGPR:$Rd, (opnode t2_so_imm:$imm, rGPR:$Rn))]> { 578 let Inst{31-27} = 0b11110; 579 let Inst{25} = 0; 580 let Inst{24-21} = opcod; 581 let Inst{15} = 0; 582 } 583 // register 584 def rr : T2sThreeReg< 585 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 586 opc, "\t$Rd, $Rn, $Rm", 587 [/* For disassembly only; pattern left blank */]> { 588 let Inst{31-27} = 0b11101; 589 let Inst{26-25} = 0b01; 590 let Inst{24-21} = opcod; 591 let Inst{14-12} = 0b000; // imm3 592 let Inst{7-6} = 0b00; // imm2 593 let Inst{5-4} = 0b00; // type 594 } 595 // shifted register 596 def rs : T2sTwoRegShiftedReg< 597 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 598 IIC_iALUsir, opc, "\t$Rd, $Rn, $ShiftedRm", 599 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]> { 600 let Inst{31-27} = 0b11101; 601 let Inst{26-25} = 0b01; 602 let Inst{24-21} = opcod; 603 } 604 } 605 606 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the 607 /// instruction modifies the CPSR register. 608 /// 609 /// These opcodes will be converted to the real non-S opcodes by 610 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand. 611 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in { 612 multiclass T2I_bin_s_irs<bits<4> opcod, string opc, 613 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 614 PatFrag opnode, bit Commutable = 0> { 615 // shifted imm 616 def ri : T2sTwoRegImm< 617 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm), iii, 618 opc, ".w\t$Rd, $Rn, $imm", 619 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_imm:$imm))]>; 620 // register 621 def rr : T2sThreeReg< 622 (outs rGPR:$Rd), (ins GPR:$Rn, rGPR:$Rm), iir, 623 opc, ".w\t$Rd, $Rn, $Rm", 624 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, rGPR:$Rm))]>; 625 // shifted register 626 def rs : T2sTwoRegShiftedReg< 627 (outs rGPR:$Rd), (ins GPR:$Rn, t2_so_reg:$ShiftedRm), iis, 628 opc, ".w\t$Rd, $Rn, $ShiftedRm", 629 [(set rGPR:$Rd, CPSR, (opnode GPR:$Rn, t2_so_reg:$ShiftedRm))]>; 630 } 631 } 632 633 /// T2I_bin_ii12rs - Defines a set of (op reg, {so_imm|imm0_4095|r|so_reg}) 634 /// patterns for a binary operation that produces a value. 635 multiclass T2I_bin_ii12rs<bits<3> op23_21, string opc, PatFrag opnode, 636 bit Commutable = 0> { 637 // shifted imm 638 // The register-immediate version is re-materializable. This is useful 639 // in particular for taking the address of a local. 640 let isReMaterializable = 1 in { 641 def ri : T2sTwoRegImm< 642 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_imm:$imm), IIC_iALUi, 643 opc, ".w\t$Rd, $Rn, $imm", 644 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_imm:$imm))]> { 645 let Inst{31-27} = 0b11110; 646 let Inst{25} = 0; 647 let Inst{24} = 1; 648 let Inst{23-21} = op23_21; 649 let Inst{15} = 0; 650 } 651 } 652 // 12-bit imm 653 def ri12 : T2I< 654 (outs GPRnopc:$Rd), (ins GPR:$Rn, imm0_4095:$imm), IIC_iALUi, 655 !strconcat(opc, "w"), "\t$Rd, $Rn, $imm", 656 [(set GPRnopc:$Rd, (opnode GPR:$Rn, imm0_4095:$imm))]> { 657 bits<4> Rd; 658 bits<4> Rn; 659 bits<12> imm; 660 let Inst{31-27} = 0b11110; 661 let Inst{26} = imm{11}; 662 let Inst{25-24} = 0b10; 663 let Inst{23-21} = op23_21; 664 let Inst{20} = 0; // The S bit. 665 let Inst{19-16} = Rn; 666 let Inst{15} = 0; 667 let Inst{14-12} = imm{10-8}; 668 let Inst{11-8} = Rd; 669 let Inst{7-0} = imm{7-0}; 670 } 671 // register 672 def rr : T2sThreeReg<(outs GPRnopc:$Rd), (ins GPRnopc:$Rn, rGPR:$Rm), 673 IIC_iALUr, opc, ".w\t$Rd, $Rn, $Rm", 674 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, rGPR:$Rm))]> { 675 let isCommutable = Commutable; 676 let Inst{31-27} = 0b11101; 677 let Inst{26-25} = 0b01; 678 let Inst{24} = 1; 679 let Inst{23-21} = op23_21; 680 let Inst{14-12} = 0b000; // imm3 681 let Inst{7-6} = 0b00; // imm2 682 let Inst{5-4} = 0b00; // type 683 } 684 // shifted register 685 def rs : T2sTwoRegShiftedReg< 686 (outs GPRnopc:$Rd), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), 687 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 688 [(set GPRnopc:$Rd, (opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm))]> { 689 let Inst{31-27} = 0b11101; 690 let Inst{26-25} = 0b01; 691 let Inst{24} = 1; 692 let Inst{23-21} = op23_21; 693 } 694 } 695 696 /// T2I_adde_sube_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns 697 /// for a binary operation that produces a value and use the carry 698 /// bit. It's not predicable. 699 let Defs = [CPSR], Uses = [CPSR] in { 700 multiclass T2I_adde_sube_irs<bits<4> opcod, string opc, PatFrag opnode, 701 bit Commutable = 0> { 702 // shifted imm 703 def ri : T2sTwoRegImm<(outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), 704 IIC_iALUi, opc, "\t$Rd, $Rn, $imm", 705 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_imm:$imm, CPSR))]>, 706 Requires<[IsThumb2]> { 707 let Inst{31-27} = 0b11110; 708 let Inst{25} = 0; 709 let Inst{24-21} = opcod; 710 let Inst{15} = 0; 711 } 712 // register 713 def rr : T2sThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUr, 714 opc, ".w\t$Rd, $Rn, $Rm", 715 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, rGPR:$Rm, CPSR))]>, 716 Requires<[IsThumb2]> { 717 let isCommutable = Commutable; 718 let Inst{31-27} = 0b11101; 719 let Inst{26-25} = 0b01; 720 let Inst{24-21} = opcod; 721 let Inst{14-12} = 0b000; // imm3 722 let Inst{7-6} = 0b00; // imm2 723 let Inst{5-4} = 0b00; // type 724 } 725 // shifted register 726 def rs : T2sTwoRegShiftedReg< 727 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 728 IIC_iALUsi, opc, ".w\t$Rd, $Rn, $ShiftedRm", 729 [(set rGPR:$Rd, CPSR, (opnode rGPR:$Rn, t2_so_reg:$ShiftedRm, CPSR))]>, 730 Requires<[IsThumb2]> { 731 let Inst{31-27} = 0b11101; 732 let Inst{26-25} = 0b01; 733 let Inst{24-21} = opcod; 734 } 735 } 736 } 737 738 /// T2I_rbin_s_is - Same as T2I_rbin_irs except sets 's' bit and the register 739 /// version is not needed since this is only for codegen. 740 /// 741 /// These opcodes will be converted to the real non-S opcodes by 742 /// AdjustInstrPostInstrSelection after giving then an optional CPSR operand. 743 let hasPostISelHook = 1, isCodeGenOnly = 1, isPseudo = 1, Defs = [CPSR] in { 744 multiclass T2I_rbin_s_is<bits<4> opcod, string opc, PatFrag opnode> { 745 // shifted imm 746 def ri : T2sTwoRegImm< 747 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_imm:$imm), IIC_iALUi, 748 opc, ".w\t$Rd, $Rn, $imm", 749 [(set rGPR:$Rd, CPSR, (opnode t2_so_imm:$imm, rGPR:$Rn))]>; 750 // shifted register 751 def rs : T2sTwoRegShiftedReg< 752 (outs rGPR:$Rd), (ins rGPR:$Rn, t2_so_reg:$ShiftedRm), 753 IIC_iALUsi, opc, "\t$Rd, $Rn, $ShiftedRm", 754 [(set rGPR:$Rd, CPSR, (opnode t2_so_reg:$ShiftedRm, rGPR:$Rn))]>; 755 } 756 } 757 758 /// T2I_sh_ir - Defines a set of (op reg, {so_imm|r}) patterns for a shift / 759 // rotate operation that produces a value. 760 multiclass T2I_sh_ir<bits<2> opcod, string opc, Operand ty, PatFrag opnode, 761 string baseOpc> { 762 // 5-bit imm 763 def ri : T2sTwoRegShiftImm< 764 (outs rGPR:$Rd), (ins rGPR:$Rm, ty:$imm), IIC_iMOVsi, 765 opc, ".w\t$Rd, $Rm, $imm", 766 [(set rGPR:$Rd, (opnode rGPR:$Rm, (i32 ty:$imm)))]> { 767 let Inst{31-27} = 0b11101; 768 let Inst{26-21} = 0b010010; 769 let Inst{19-16} = 0b1111; // Rn 770 let Inst{5-4} = opcod; 771 } 772 // register 773 def rr : T2sThreeReg< 774 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMOVsr, 775 opc, ".w\t$Rd, $Rn, $Rm", 776 [(set rGPR:$Rd, (opnode rGPR:$Rn, rGPR:$Rm))]> { 777 let Inst{31-27} = 0b11111; 778 let Inst{26-23} = 0b0100; 779 let Inst{22-21} = opcod; 780 let Inst{15-12} = 0b1111; 781 let Inst{7-4} = 0b0000; 782 } 783 784 // Optional destination register 785 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $imm"), 786 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 787 ty:$imm, pred:$p, 788 cc_out:$s)>; 789 def : t2InstAlias<!strconcat(opc, "${s}${p}", ".w $Rdn, $Rm"), 790 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 791 rGPR:$Rm, pred:$p, 792 cc_out:$s)>; 793 794 // Assembler aliases w/o the ".w" suffix. 795 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $imm"), 796 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rd, rGPR:$Rn, 797 ty:$imm, pred:$p, 798 cc_out:$s)>; 799 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rd, $Rn, $Rm"), 800 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rd, rGPR:$Rn, 801 rGPR:$Rm, pred:$p, 802 cc_out:$s)>; 803 804 // and with the optional destination operand, too. 805 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $imm"), 806 (!cast<Instruction>(!strconcat(baseOpc, "ri")) rGPR:$Rdn, rGPR:$Rdn, 807 ty:$imm, pred:$p, 808 cc_out:$s)>; 809 def : t2InstAlias<!strconcat(opc, "${s}${p}", " $Rdn, $Rm"), 810 (!cast<Instruction>(!strconcat(baseOpc, "rr")) rGPR:$Rdn, rGPR:$Rdn, 811 rGPR:$Rm, pred:$p, 812 cc_out:$s)>; 813 } 814 815 /// T2I_cmp_irs - Defines a set of (op r, {so_imm|r|so_reg}) cmp / test 816 /// patterns. Similar to T2I_bin_irs except the instruction does not produce 817 /// a explicit result, only implicitly set CPSR. 818 multiclass T2I_cmp_irs<bits<4> opcod, string opc, 819 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 820 PatFrag opnode, string baseOpc> { 821 let isCompare = 1, Defs = [CPSR] in { 822 // shifted imm 823 def ri : T2OneRegCmpImm< 824 (outs), (ins GPRnopc:$Rn, t2_so_imm:$imm), iii, 825 opc, ".w\t$Rn, $imm", 826 [(opnode GPRnopc:$Rn, t2_so_imm:$imm)]> { 827 let Inst{31-27} = 0b11110; 828 let Inst{25} = 0; 829 let Inst{24-21} = opcod; 830 let Inst{20} = 1; // The S bit. 831 let Inst{15} = 0; 832 let Inst{11-8} = 0b1111; // Rd 833 } 834 // register 835 def rr : T2TwoRegCmp< 836 (outs), (ins GPRnopc:$Rn, rGPR:$Rm), iir, 837 opc, ".w\t$Rn, $Rm", 838 [(opnode GPRnopc:$Rn, rGPR:$Rm)]> { 839 let Inst{31-27} = 0b11101; 840 let Inst{26-25} = 0b01; 841 let Inst{24-21} = opcod; 842 let Inst{20} = 1; // The S bit. 843 let Inst{14-12} = 0b000; // imm3 844 let Inst{11-8} = 0b1111; // Rd 845 let Inst{7-6} = 0b00; // imm2 846 let Inst{5-4} = 0b00; // type 847 } 848 // shifted register 849 def rs : T2OneRegCmpShiftedReg< 850 (outs), (ins GPRnopc:$Rn, t2_so_reg:$ShiftedRm), iis, 851 opc, ".w\t$Rn, $ShiftedRm", 852 [(opnode GPRnopc:$Rn, t2_so_reg:$ShiftedRm)]> { 853 let Inst{31-27} = 0b11101; 854 let Inst{26-25} = 0b01; 855 let Inst{24-21} = opcod; 856 let Inst{20} = 1; // The S bit. 857 let Inst{11-8} = 0b1111; // Rd 858 } 859 } 860 861 // Assembler aliases w/o the ".w" suffix. 862 // No alias here for 'rr' version as not all instantiations of this 863 // multiclass want one (CMP in particular, does not). 864 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $imm"), 865 (!cast<Instruction>(!strconcat(baseOpc, "ri")) GPRnopc:$Rn, 866 t2_so_imm:$imm, pred:$p)>; 867 def : t2InstAlias<!strconcat(opc, "${p}", " $Rn, $shift"), 868 (!cast<Instruction>(!strconcat(baseOpc, "rs")) GPRnopc:$Rn, 869 t2_so_reg:$shift, 870 pred:$p)>; 871 } 872 873 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns. 874 multiclass T2I_ld<bit signed, bits<2> opcod, string opc, 875 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 876 PatFrag opnode> { 877 def i12 : T2Ii12<(outs target:$Rt), (ins t2addrmode_imm12:$addr), iii, 878 opc, ".w\t$Rt, $addr", 879 [(set target:$Rt, (opnode t2addrmode_imm12:$addr))]> { 880 bits<4> Rt; 881 bits<17> addr; 882 let Inst{31-25} = 0b1111100; 883 let Inst{24} = signed; 884 let Inst{23} = 1; 885 let Inst{22-21} = opcod; 886 let Inst{20} = 1; // load 887 let Inst{19-16} = addr{16-13}; // Rn 888 let Inst{15-12} = Rt; 889 let Inst{11-0} = addr{11-0}; // imm 890 } 891 def i8 : T2Ii8 <(outs target:$Rt), (ins t2addrmode_negimm8:$addr), iii, 892 opc, "\t$Rt, $addr", 893 [(set target:$Rt, (opnode t2addrmode_negimm8:$addr))]> { 894 bits<4> Rt; 895 bits<13> addr; 896 let Inst{31-27} = 0b11111; 897 let Inst{26-25} = 0b00; 898 let Inst{24} = signed; 899 let Inst{23} = 0; 900 let Inst{22-21} = opcod; 901 let Inst{20} = 1; // load 902 let Inst{19-16} = addr{12-9}; // Rn 903 let Inst{15-12} = Rt; 904 let Inst{11} = 1; 905 // Offset: index==TRUE, wback==FALSE 906 let Inst{10} = 1; // The P bit. 907 let Inst{9} = addr{8}; // U 908 let Inst{8} = 0; // The W bit. 909 let Inst{7-0} = addr{7-0}; // imm 910 } 911 def s : T2Iso <(outs target:$Rt), (ins t2addrmode_so_reg:$addr), iis, 912 opc, ".w\t$Rt, $addr", 913 [(set target:$Rt, (opnode t2addrmode_so_reg:$addr))]> { 914 let Inst{31-27} = 0b11111; 915 let Inst{26-25} = 0b00; 916 let Inst{24} = signed; 917 let Inst{23} = 0; 918 let Inst{22-21} = opcod; 919 let Inst{20} = 1; // load 920 let Inst{11-6} = 0b000000; 921 922 bits<4> Rt; 923 let Inst{15-12} = Rt; 924 925 bits<10> addr; 926 let Inst{19-16} = addr{9-6}; // Rn 927 let Inst{3-0} = addr{5-2}; // Rm 928 let Inst{5-4} = addr{1-0}; // imm 929 930 let DecoderMethod = "DecodeT2LoadShift"; 931 } 932 933 // FIXME: Is the pci variant actually needed? 934 def pci : T2Ipc <(outs target:$Rt), (ins t2ldrlabel:$addr), iii, 935 opc, ".w\t$Rt, $addr", 936 [(set target:$Rt, (opnode (ARMWrapper tconstpool:$addr)))]> { 937 let isReMaterializable = 1; 938 let Inst{31-27} = 0b11111; 939 let Inst{26-25} = 0b00; 940 let Inst{24} = signed; 941 let Inst{23} = ?; // add = (U == '1') 942 let Inst{22-21} = opcod; 943 let Inst{20} = 1; // load 944 let Inst{19-16} = 0b1111; // Rn 945 bits<4> Rt; 946 bits<12> addr; 947 let Inst{15-12} = Rt{3-0}; 948 let Inst{11-0} = addr{11-0}; 949 } 950 } 951 952 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns. 953 multiclass T2I_st<bits<2> opcod, string opc, 954 InstrItinClass iii, InstrItinClass iis, RegisterClass target, 955 PatFrag opnode> { 956 def i12 : T2Ii12<(outs), (ins target:$Rt, t2addrmode_imm12:$addr), iii, 957 opc, ".w\t$Rt, $addr", 958 [(opnode target:$Rt, t2addrmode_imm12:$addr)]> { 959 let Inst{31-27} = 0b11111; 960 let Inst{26-23} = 0b0001; 961 let Inst{22-21} = opcod; 962 let Inst{20} = 0; // !load 963 964 bits<4> Rt; 965 let Inst{15-12} = Rt; 966 967 bits<17> addr; 968 let addr{12} = 1; // add = TRUE 969 let Inst{19-16} = addr{16-13}; // Rn 970 let Inst{23} = addr{12}; // U 971 let Inst{11-0} = addr{11-0}; // imm 972 } 973 def i8 : T2Ii8 <(outs), (ins target:$Rt, t2addrmode_negimm8:$addr), iii, 974 opc, "\t$Rt, $addr", 975 [(opnode target:$Rt, t2addrmode_negimm8:$addr)]> { 976 let Inst{31-27} = 0b11111; 977 let Inst{26-23} = 0b0000; 978 let Inst{22-21} = opcod; 979 let Inst{20} = 0; // !load 980 let Inst{11} = 1; 981 // Offset: index==TRUE, wback==FALSE 982 let Inst{10} = 1; // The P bit. 983 let Inst{8} = 0; // The W bit. 984 985 bits<4> Rt; 986 let Inst{15-12} = Rt; 987 988 bits<13> addr; 989 let Inst{19-16} = addr{12-9}; // Rn 990 let Inst{9} = addr{8}; // U 991 let Inst{7-0} = addr{7-0}; // imm 992 } 993 def s : T2Iso <(outs), (ins target:$Rt, t2addrmode_so_reg:$addr), iis, 994 opc, ".w\t$Rt, $addr", 995 [(opnode target:$Rt, t2addrmode_so_reg:$addr)]> { 996 let Inst{31-27} = 0b11111; 997 let Inst{26-23} = 0b0000; 998 let Inst{22-21} = opcod; 999 let Inst{20} = 0; // !load 1000 let Inst{11-6} = 0b000000; 1001 1002 bits<4> Rt; 1003 let Inst{15-12} = Rt; 1004 1005 bits<10> addr; 1006 let Inst{19-16} = addr{9-6}; // Rn 1007 let Inst{3-0} = addr{5-2}; // Rm 1008 let Inst{5-4} = addr{1-0}; // imm 1009 } 1010 } 1011 1012 /// T2I_ext_rrot - A unary operation with two forms: one whose operand is a 1013 /// register and one whose operand is a register rotated by 8/16/24. 1014 class T2I_ext_rrot<bits<3> opcod, string opc, PatFrag opnode> 1015 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, 1016 opc, ".w\t$Rd, $Rm$rot", 1017 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, 1018 Requires<[IsThumb2]> { 1019 let Inst{31-27} = 0b11111; 1020 let Inst{26-23} = 0b0100; 1021 let Inst{22-20} = opcod; 1022 let Inst{19-16} = 0b1111; // Rn 1023 let Inst{15-12} = 0b1111; 1024 let Inst{7} = 1; 1025 1026 bits<2> rot; 1027 let Inst{5-4} = rot{1-0}; // rotate 1028 } 1029 1030 // UXTB16 - Requres T2ExtractPack, does not need the .w qualifier. 1031 class T2I_ext_rrot_uxtb16<bits<3> opcod, string opc, PatFrag opnode> 1032 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), 1033 IIC_iEXTr, opc, "\t$Rd, $Rm$rot", 1034 [(set rGPR:$Rd, (opnode (rotr rGPR:$Rm, rot_imm:$rot)))]>, 1035 Requires<[HasT2ExtractPack, IsThumb2]> { 1036 bits<2> rot; 1037 let Inst{31-27} = 0b11111; 1038 let Inst{26-23} = 0b0100; 1039 let Inst{22-20} = opcod; 1040 let Inst{19-16} = 0b1111; // Rn 1041 let Inst{15-12} = 0b1111; 1042 let Inst{7} = 1; 1043 let Inst{5-4} = rot; 1044 } 1045 1046 // SXTB16 - Requres T2ExtractPack, does not need the .w qualifier, no pattern 1047 // supported yet. 1048 class T2I_ext_rrot_sxtb16<bits<3> opcod, string opc> 1049 : T2TwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm, rot_imm:$rot), IIC_iEXTr, 1050 opc, "\t$Rd, $Rm$rot", []>, 1051 Requires<[IsThumb2, HasT2ExtractPack]> { 1052 bits<2> rot; 1053 let Inst{31-27} = 0b11111; 1054 let Inst{26-23} = 0b0100; 1055 let Inst{22-20} = opcod; 1056 let Inst{19-16} = 0b1111; // Rn 1057 let Inst{15-12} = 0b1111; 1058 let Inst{7} = 1; 1059 let Inst{5-4} = rot; 1060 } 1061 1062 /// T2I_exta_rrot - A binary operation with two forms: one whose operand is a 1063 /// register and one whose operand is a register rotated by 8/16/24. 1064 class T2I_exta_rrot<bits<3> opcod, string opc, PatFrag opnode> 1065 : T2ThreeReg<(outs rGPR:$Rd), 1066 (ins rGPR:$Rn, rGPR:$Rm, rot_imm:$rot), 1067 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", 1068 [(set rGPR:$Rd, (opnode rGPR:$Rn, (rotr rGPR:$Rm,rot_imm:$rot)))]>, 1069 Requires<[HasT2ExtractPack, IsThumb2]> { 1070 bits<2> rot; 1071 let Inst{31-27} = 0b11111; 1072 let Inst{26-23} = 0b0100; 1073 let Inst{22-20} = opcod; 1074 let Inst{15-12} = 0b1111; 1075 let Inst{7} = 1; 1076 let Inst{5-4} = rot; 1077 } 1078 1079 class T2I_exta_rrot_np<bits<3> opcod, string opc> 1080 : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm,rot_imm:$rot), 1081 IIC_iEXTAsr, opc, "\t$Rd, $Rn, $Rm$rot", []> { 1082 bits<2> rot; 1083 let Inst{31-27} = 0b11111; 1084 let Inst{26-23} = 0b0100; 1085 let Inst{22-20} = opcod; 1086 let Inst{15-12} = 0b1111; 1087 let Inst{7} = 1; 1088 let Inst{5-4} = rot; 1089 } 1090 1091 //===----------------------------------------------------------------------===// 1092 // Instructions 1093 //===----------------------------------------------------------------------===// 1094 1095 //===----------------------------------------------------------------------===// 1096 // Miscellaneous Instructions. 1097 // 1098 1099 class T2PCOneRegImm<dag oops, dag iops, InstrItinClass itin, 1100 string asm, list<dag> pattern> 1101 : T2XI<oops, iops, itin, asm, pattern> { 1102 bits<4> Rd; 1103 bits<12> label; 1104 1105 let Inst{11-8} = Rd; 1106 let Inst{26} = label{11}; 1107 let Inst{14-12} = label{10-8}; 1108 let Inst{7-0} = label{7-0}; 1109 } 1110 1111 // LEApcrel - Load a pc-relative address into a register without offending the 1112 // assembler. 1113 def t2ADR : T2PCOneRegImm<(outs rGPR:$Rd), 1114 (ins t2adrlabel:$addr, pred:$p), 1115 IIC_iALUi, "adr{$p}.w\t$Rd, $addr", []> { 1116 let Inst{31-27} = 0b11110; 1117 let Inst{25-24} = 0b10; 1118 // Inst{23:21} = '11' (add = FALSE) or '00' (add = TRUE) 1119 let Inst{22} = 0; 1120 let Inst{20} = 0; 1121 let Inst{19-16} = 0b1111; // Rn 1122 let Inst{15} = 0; 1123 1124 bits<4> Rd; 1125 bits<13> addr; 1126 let Inst{11-8} = Rd; 1127 let Inst{23} = addr{12}; 1128 let Inst{21} = addr{12}; 1129 let Inst{26} = addr{11}; 1130 let Inst{14-12} = addr{10-8}; 1131 let Inst{7-0} = addr{7-0}; 1132 1133 let DecoderMethod = "DecodeT2Adr"; 1134 } 1135 1136 let neverHasSideEffects = 1, isReMaterializable = 1 in 1137 def t2LEApcrel : t2PseudoInst<(outs rGPR:$Rd), (ins i32imm:$label, pred:$p), 1138 4, IIC_iALUi, []>; 1139 def t2LEApcrelJT : t2PseudoInst<(outs rGPR:$Rd), 1140 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1141 4, IIC_iALUi, 1142 []>; 1143 1144 1145 //===----------------------------------------------------------------------===// 1146 // Load / store Instructions. 1147 // 1148 1149 // Load 1150 let canFoldAsLoad = 1, isReMaterializable = 1 in 1151 defm t2LDR : T2I_ld<0, 0b10, "ldr", IIC_iLoad_i, IIC_iLoad_si, GPR, 1152 UnOpFrag<(load node:$Src)>>; 1153 1154 // Loads with zero extension 1155 defm t2LDRH : T2I_ld<0, 0b01, "ldrh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1156 rGPR, UnOpFrag<(zextloadi16 node:$Src)>>; 1157 defm t2LDRB : T2I_ld<0, 0b00, "ldrb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1158 rGPR, UnOpFrag<(zextloadi8 node:$Src)>>; 1159 1160 // Loads with sign extension 1161 defm t2LDRSH : T2I_ld<1, 0b01, "ldrsh", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1162 rGPR, UnOpFrag<(sextloadi16 node:$Src)>>; 1163 defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si, 1164 rGPR, UnOpFrag<(sextloadi8 node:$Src)>>; 1165 1166 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in { 1167 // Load doubleword 1168 def t2LDRDi8 : T2Ii8s4<1, 0, 1, (outs rGPR:$Rt, rGPR:$Rt2), 1169 (ins t2addrmode_imm8s4:$addr), 1170 IIC_iLoad_d_i, "ldrd", "\t$Rt, $Rt2, $addr", "", []>; 1171 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 1172 1173 // zextload i1 -> zextload i8 1174 def : T2Pat<(zextloadi1 t2addrmode_imm12:$addr), 1175 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1176 def : T2Pat<(zextloadi1 t2addrmode_negimm8:$addr), 1177 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1178 def : T2Pat<(zextloadi1 t2addrmode_so_reg:$addr), 1179 (t2LDRBs t2addrmode_so_reg:$addr)>; 1180 def : T2Pat<(zextloadi1 (ARMWrapper tconstpool:$addr)), 1181 (t2LDRBpci tconstpool:$addr)>; 1182 1183 // extload -> zextload 1184 // FIXME: Reduce the number of patterns by legalizing extload to zextload 1185 // earlier? 1186 def : T2Pat<(extloadi1 t2addrmode_imm12:$addr), 1187 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1188 def : T2Pat<(extloadi1 t2addrmode_negimm8:$addr), 1189 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1190 def : T2Pat<(extloadi1 t2addrmode_so_reg:$addr), 1191 (t2LDRBs t2addrmode_so_reg:$addr)>; 1192 def : T2Pat<(extloadi1 (ARMWrapper tconstpool:$addr)), 1193 (t2LDRBpci tconstpool:$addr)>; 1194 1195 def : T2Pat<(extloadi8 t2addrmode_imm12:$addr), 1196 (t2LDRBi12 t2addrmode_imm12:$addr)>; 1197 def : T2Pat<(extloadi8 t2addrmode_negimm8:$addr), 1198 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 1199 def : T2Pat<(extloadi8 t2addrmode_so_reg:$addr), 1200 (t2LDRBs t2addrmode_so_reg:$addr)>; 1201 def : T2Pat<(extloadi8 (ARMWrapper tconstpool:$addr)), 1202 (t2LDRBpci tconstpool:$addr)>; 1203 1204 def : T2Pat<(extloadi16 t2addrmode_imm12:$addr), 1205 (t2LDRHi12 t2addrmode_imm12:$addr)>; 1206 def : T2Pat<(extloadi16 t2addrmode_negimm8:$addr), 1207 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 1208 def : T2Pat<(extloadi16 t2addrmode_so_reg:$addr), 1209 (t2LDRHs t2addrmode_so_reg:$addr)>; 1210 def : T2Pat<(extloadi16 (ARMWrapper tconstpool:$addr)), 1211 (t2LDRHpci tconstpool:$addr)>; 1212 1213 // FIXME: The destination register of the loads and stores can't be PC, but 1214 // can be SP. We need another regclass (similar to rGPR) to represent 1215 // that. Not a pressing issue since these are selected manually, 1216 // not via pattern. 1217 1218 // Indexed loads 1219 1220 let mayLoad = 1, neverHasSideEffects = 1 in { 1221 def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1222 (ins t2addrmode_imm8:$addr), 1223 AddrModeT2_i8, IndexModePre, IIC_iLoad_iu, 1224 "ldr", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1225 []> { 1226 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1227 } 1228 1229 def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1230 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1231 AddrModeT2_i8, IndexModePost, IIC_iLoad_iu, 1232 "ldr", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1233 1234 def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1235 (ins t2addrmode_imm8:$addr), 1236 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1237 "ldrb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1238 []> { 1239 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1240 } 1241 def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1242 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1243 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1244 "ldrb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1245 1246 def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1247 (ins t2addrmode_imm8:$addr), 1248 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1249 "ldrh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1250 []> { 1251 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1252 } 1253 def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1254 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1255 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1256 "ldrh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1257 1258 def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1259 (ins t2addrmode_imm8:$addr), 1260 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1261 "ldrsb", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1262 []> { 1263 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1264 } 1265 def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1266 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1267 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1268 "ldrsb", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1269 1270 def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), 1271 (ins t2addrmode_imm8:$addr), 1272 AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu, 1273 "ldrsh", "\t$Rt, $addr!", "$addr.base = $Rn_wb", 1274 []> { 1275 let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; 1276 } 1277 def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), 1278 (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), 1279 AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, 1280 "ldrsh", "\t$Rt, $Rn$offset", "$Rn = $Rn_wb", []>; 1281 } // mayLoad = 1, neverHasSideEffects = 1 1282 1283 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110). 1284 // Ref: A8.6.57 LDR (immediate, Thumb) Encoding T4 1285 class T2IldT<bit signed, bits<2> type, string opc, InstrItinClass ii> 1286 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_posimm8:$addr), ii, opc, 1287 "\t$Rt, $addr", []> { 1288 bits<4> Rt; 1289 bits<13> addr; 1290 let Inst{31-27} = 0b11111; 1291 let Inst{26-25} = 0b00; 1292 let Inst{24} = signed; 1293 let Inst{23} = 0; 1294 let Inst{22-21} = type; 1295 let Inst{20} = 1; // load 1296 let Inst{19-16} = addr{12-9}; 1297 let Inst{15-12} = Rt; 1298 let Inst{11} = 1; 1299 let Inst{10-8} = 0b110; // PUW. 1300 let Inst{7-0} = addr{7-0}; 1301 } 1302 1303 def t2LDRT : T2IldT<0, 0b10, "ldrt", IIC_iLoad_i>; 1304 def t2LDRBT : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>; 1305 def t2LDRHT : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>; 1306 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>; 1307 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>; 1308 1309 // Store 1310 defm t2STR :T2I_st<0b10,"str", IIC_iStore_i, IIC_iStore_si, GPR, 1311 BinOpFrag<(store node:$LHS, node:$RHS)>>; 1312 defm t2STRB:T2I_st<0b00,"strb", IIC_iStore_bh_i, IIC_iStore_bh_si, 1313 rGPR, BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 1314 defm t2STRH:T2I_st<0b01,"strh", IIC_iStore_bh_i, IIC_iStore_bh_si, 1315 rGPR, BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 1316 1317 // Store doubleword 1318 let mayLoad = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in 1319 def t2STRDi8 : T2Ii8s4<1, 0, 0, (outs), 1320 (ins GPR:$Rt, GPR:$Rt2, t2addrmode_imm8s4:$addr), 1321 IIC_iStore_d_r, "strd", "\t$Rt, $Rt2, $addr", "", []>; 1322 1323 // Indexed stores 1324 def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb), 1325 (ins rGPR:$Rt, t2addrmode_imm8:$addr), 1326 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1327 "str", "\t$Rt, $addr!", 1328 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 1329 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8"; 1330 } 1331 def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb), 1332 (ins rGPR:$Rt, t2addrmode_imm8:$addr), 1333 AddrModeT2_i8, IndexModePre, IIC_iStore_iu, 1334 "strh", "\t$Rt, $addr!", 1335 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 1336 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8"; 1337 } 1338 1339 def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb), 1340 (ins rGPR:$Rt, t2addrmode_imm8:$addr), 1341 AddrModeT2_i8, IndexModePre, IIC_iStore_bh_iu, 1342 "strb", "\t$Rt, $addr!", 1343 "$addr.base = $Rn_wb,@earlyclobber $Rn_wb", []> { 1344 let AsmMatchConverter = "cvtStWriteBackRegT2AddrModeImm8"; 1345 } 1346 1347 def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb), 1348 (ins rGPR:$Rt, addr_offset_none:$Rn, 1349 t2am_imm8_offset:$offset), 1350 AddrModeT2_i8, IndexModePost, IIC_iStore_iu, 1351 "str", "\t$Rt, $Rn$offset", 1352 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1353 [(set GPRnopc:$Rn_wb, 1354 (post_store rGPR:$Rt, addr_offset_none:$Rn, 1355 t2am_imm8_offset:$offset))]>; 1356 1357 def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb), 1358 (ins rGPR:$Rt, addr_offset_none:$Rn, 1359 t2am_imm8_offset:$offset), 1360 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1361 "strh", "\t$Rt, $Rn$offset", 1362 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1363 [(set GPRnopc:$Rn_wb, 1364 (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, 1365 t2am_imm8_offset:$offset))]>; 1366 1367 def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb), 1368 (ins rGPR:$Rt, addr_offset_none:$Rn, 1369 t2am_imm8_offset:$offset), 1370 AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, 1371 "strb", "\t$Rt, $Rn$offset", 1372 "$Rn = $Rn_wb,@earlyclobber $Rn_wb", 1373 [(set GPRnopc:$Rn_wb, 1374 (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, 1375 t2am_imm8_offset:$offset))]>; 1376 1377 // Pseudo-instructions for pattern matching the pre-indexed stores. We can't 1378 // put the patterns on the instruction definitions directly as ISel wants 1379 // the address base and offset to be separate operands, not a single 1380 // complex operand like we represent the instructions themselves. The 1381 // pseudos map between the two. 1382 let usesCustomInserter = 1, 1383 Constraints = "$Rn = $Rn_wb,@earlyclobber $Rn_wb" in { 1384 def t2STR_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1385 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1386 4, IIC_iStore_ru, 1387 [(set GPRnopc:$Rn_wb, 1388 (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1389 def t2STRB_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1390 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1391 4, IIC_iStore_ru, 1392 [(set GPRnopc:$Rn_wb, 1393 (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1394 def t2STRH_preidx: t2PseudoInst<(outs GPRnopc:$Rn_wb), 1395 (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset, pred:$p), 1396 4, IIC_iStore_ru, 1397 [(set GPRnopc:$Rn_wb, 1398 (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$offset))]>; 1399 } 1400 1401 1402 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly 1403 // only. 1404 // Ref: A8.6.193 STR (immediate, Thumb) Encoding T4 1405 class T2IstT<bits<2> type, string opc, InstrItinClass ii> 1406 : T2Ii8<(outs rGPR:$Rt), (ins t2addrmode_imm8:$addr), ii, opc, 1407 "\t$Rt, $addr", []> { 1408 let Inst{31-27} = 0b11111; 1409 let Inst{26-25} = 0b00; 1410 let Inst{24} = 0; // not signed 1411 let Inst{23} = 0; 1412 let Inst{22-21} = type; 1413 let Inst{20} = 0; // store 1414 let Inst{11} = 1; 1415 let Inst{10-8} = 0b110; // PUW 1416 1417 bits<4> Rt; 1418 bits<13> addr; 1419 let Inst{15-12} = Rt; 1420 let Inst{19-16} = addr{12-9}; 1421 let Inst{7-0} = addr{7-0}; 1422 } 1423 1424 def t2STRT : T2IstT<0b10, "strt", IIC_iStore_i>; 1425 def t2STRBT : T2IstT<0b00, "strbt", IIC_iStore_bh_i>; 1426 def t2STRHT : T2IstT<0b01, "strht", IIC_iStore_bh_i>; 1427 1428 // ldrd / strd pre / post variants 1429 // For disassembly only. 1430 1431 def t2LDRD_PRE : T2Ii8s4<1, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1432 (ins t2addrmode_imm8s4:$addr), IIC_iLoad_d_ru, 1433 "ldrd", "\t$Rt, $Rt2, $addr!", "$addr.base = $wb", []> { 1434 let AsmMatchConverter = "cvtT2LdrdPre"; 1435 let DecoderMethod = "DecodeT2LDRDPreInstruction"; 1436 } 1437 1438 def t2LDRD_POST : T2Ii8s4post<0, 1, 1, (outs rGPR:$Rt, rGPR:$Rt2, GPR:$wb), 1439 (ins addr_offset_none:$addr, t2am_imm8s4_offset:$imm), 1440 IIC_iLoad_d_ru, "ldrd", "\t$Rt, $Rt2, $addr$imm", 1441 "$addr.base = $wb", []>; 1442 1443 def t2STRD_PRE : T2Ii8s4<1, 1, 0, (outs GPR:$wb), 1444 (ins rGPR:$Rt, rGPR:$Rt2, t2addrmode_imm8s4:$addr), 1445 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr!", 1446 "$addr.base = $wb", []> { 1447 let AsmMatchConverter = "cvtT2StrdPre"; 1448 let DecoderMethod = "DecodeT2STRDPreInstruction"; 1449 } 1450 1451 def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb), 1452 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr, 1453 t2am_imm8s4_offset:$imm), 1454 IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm", 1455 "$addr.base = $wb", []>; 1456 1457 // T2Ipl (Preload Data/Instruction) signals the memory system of possible future 1458 // data/instruction access. These are for disassembly only. 1459 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0), 1460 // (prefetch 1) -> (preload 2), (prefetch 2) -> (preload 1). 1461 multiclass T2Ipl<bits<1> write, bits<1> instr, string opc> { 1462 1463 def i12 : T2Ii12<(outs), (ins t2addrmode_imm12:$addr), IIC_Preload, opc, 1464 "\t$addr", 1465 [(ARMPreload t2addrmode_imm12:$addr, (i32 write), (i32 instr))]> { 1466 let Inst{31-25} = 0b1111100; 1467 let Inst{24} = instr; 1468 let Inst{22} = 0; 1469 let Inst{21} = write; 1470 let Inst{20} = 1; 1471 let Inst{15-12} = 0b1111; 1472 1473 bits<17> addr; 1474 let addr{12} = 1; // add = TRUE 1475 let Inst{19-16} = addr{16-13}; // Rn 1476 let Inst{23} = addr{12}; // U 1477 let Inst{11-0} = addr{11-0}; // imm12 1478 } 1479 1480 def i8 : T2Ii8<(outs), (ins t2addrmode_negimm8:$addr), IIC_Preload, opc, 1481 "\t$addr", 1482 [(ARMPreload t2addrmode_negimm8:$addr, (i32 write), (i32 instr))]> { 1483 let Inst{31-25} = 0b1111100; 1484 let Inst{24} = instr; 1485 let Inst{23} = 0; // U = 0 1486 let Inst{22} = 0; 1487 let Inst{21} = write; 1488 let Inst{20} = 1; 1489 let Inst{15-12} = 0b1111; 1490 let Inst{11-8} = 0b1100; 1491 1492 bits<13> addr; 1493 let Inst{19-16} = addr{12-9}; // Rn 1494 let Inst{7-0} = addr{7-0}; // imm8 1495 } 1496 1497 def s : T2Iso<(outs), (ins t2addrmode_so_reg:$addr), IIC_Preload, opc, 1498 "\t$addr", 1499 [(ARMPreload t2addrmode_so_reg:$addr, (i32 write), (i32 instr))]> { 1500 let Inst{31-25} = 0b1111100; 1501 let Inst{24} = instr; 1502 let Inst{23} = 0; // add = TRUE for T1 1503 let Inst{22} = 0; 1504 let Inst{21} = write; 1505 let Inst{20} = 1; 1506 let Inst{15-12} = 0b1111; 1507 let Inst{11-6} = 0000000; 1508 1509 bits<10> addr; 1510 let Inst{19-16} = addr{9-6}; // Rn 1511 let Inst{3-0} = addr{5-2}; // Rm 1512 let Inst{5-4} = addr{1-0}; // imm2 1513 1514 let DecoderMethod = "DecodeT2LoadShift"; 1515 } 1516 } 1517 1518 defm t2PLD : T2Ipl<0, 0, "pld">, Requires<[IsThumb2]>; 1519 defm t2PLDW : T2Ipl<1, 0, "pldw">, Requires<[IsThumb2,HasV7,HasMP]>; 1520 defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>; 1521 1522 //===----------------------------------------------------------------------===// 1523 // Load / store multiple Instructions. 1524 // 1525 1526 multiclass thumb2_ld_mult<string asm, InstrItinClass itin, 1527 InstrItinClass itin_upd, bit L_bit> { 1528 def IA : 1529 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1530 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1531 bits<4> Rn; 1532 bits<16> regs; 1533 1534 let Inst{31-27} = 0b11101; 1535 let Inst{26-25} = 0b00; 1536 let Inst{24-23} = 0b01; // Increment After 1537 let Inst{22} = 0; 1538 let Inst{21} = 0; // No writeback 1539 let Inst{20} = L_bit; 1540 let Inst{19-16} = Rn; 1541 let Inst{15-0} = regs; 1542 } 1543 def IA_UPD : 1544 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1545 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1546 bits<4> Rn; 1547 bits<16> regs; 1548 1549 let Inst{31-27} = 0b11101; 1550 let Inst{26-25} = 0b00; 1551 let Inst{24-23} = 0b01; // Increment After 1552 let Inst{22} = 0; 1553 let Inst{21} = 1; // Writeback 1554 let Inst{20} = L_bit; 1555 let Inst{19-16} = Rn; 1556 let Inst{15-0} = regs; 1557 } 1558 def DB : 1559 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1560 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1561 bits<4> Rn; 1562 bits<16> regs; 1563 1564 let Inst{31-27} = 0b11101; 1565 let Inst{26-25} = 0b00; 1566 let Inst{24-23} = 0b10; // Decrement Before 1567 let Inst{22} = 0; 1568 let Inst{21} = 0; // No writeback 1569 let Inst{20} = L_bit; 1570 let Inst{19-16} = Rn; 1571 let Inst{15-0} = regs; 1572 } 1573 def DB_UPD : 1574 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1575 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1576 bits<4> Rn; 1577 bits<16> regs; 1578 1579 let Inst{31-27} = 0b11101; 1580 let Inst{26-25} = 0b00; 1581 let Inst{24-23} = 0b10; // Decrement Before 1582 let Inst{22} = 0; 1583 let Inst{21} = 1; // Writeback 1584 let Inst{20} = L_bit; 1585 let Inst{19-16} = Rn; 1586 let Inst{15-0} = regs; 1587 } 1588 } 1589 1590 let neverHasSideEffects = 1 in { 1591 1592 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 1593 defm t2LDM : thumb2_ld_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 1>; 1594 1595 multiclass thumb2_st_mult<string asm, InstrItinClass itin, 1596 InstrItinClass itin_upd, bit L_bit> { 1597 def IA : 1598 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1599 itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> { 1600 bits<4> Rn; 1601 bits<16> regs; 1602 1603 let Inst{31-27} = 0b11101; 1604 let Inst{26-25} = 0b00; 1605 let Inst{24-23} = 0b01; // Increment After 1606 let Inst{22} = 0; 1607 let Inst{21} = 0; // No writeback 1608 let Inst{20} = L_bit; 1609 let Inst{19-16} = Rn; 1610 let Inst{15} = 0; 1611 let Inst{14} = regs{14}; 1612 let Inst{13} = 0; 1613 let Inst{12-0} = regs{12-0}; 1614 } 1615 def IA_UPD : 1616 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1617 itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> { 1618 bits<4> Rn; 1619 bits<16> regs; 1620 1621 let Inst{31-27} = 0b11101; 1622 let Inst{26-25} = 0b00; 1623 let Inst{24-23} = 0b01; // Increment After 1624 let Inst{22} = 0; 1625 let Inst{21} = 1; // Writeback 1626 let Inst{20} = L_bit; 1627 let Inst{19-16} = Rn; 1628 let Inst{15} = 0; 1629 let Inst{14} = regs{14}; 1630 let Inst{13} = 0; 1631 let Inst{12-0} = regs{12-0}; 1632 } 1633 def DB : 1634 T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1635 itin, !strconcat(asm, "db${p}\t$Rn, $regs"), []> { 1636 bits<4> Rn; 1637 bits<16> regs; 1638 1639 let Inst{31-27} = 0b11101; 1640 let Inst{26-25} = 0b00; 1641 let Inst{24-23} = 0b10; // Decrement Before 1642 let Inst{22} = 0; 1643 let Inst{21} = 0; // No writeback 1644 let Inst{20} = L_bit; 1645 let Inst{19-16} = Rn; 1646 let Inst{15} = 0; 1647 let Inst{14} = regs{14}; 1648 let Inst{13} = 0; 1649 let Inst{12-0} = regs{12-0}; 1650 } 1651 def DB_UPD : 1652 T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 1653 itin_upd, !strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> { 1654 bits<4> Rn; 1655 bits<16> regs; 1656 1657 let Inst{31-27} = 0b11101; 1658 let Inst{26-25} = 0b00; 1659 let Inst{24-23} = 0b10; // Decrement Before 1660 let Inst{22} = 0; 1661 let Inst{21} = 1; // Writeback 1662 let Inst{20} = L_bit; 1663 let Inst{19-16} = Rn; 1664 let Inst{15} = 0; 1665 let Inst{14} = regs{14}; 1666 let Inst{13} = 0; 1667 let Inst{12-0} = regs{12-0}; 1668 } 1669 } 1670 1671 1672 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 1673 defm t2STM : thumb2_st_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 0>; 1674 1675 } // neverHasSideEffects 1676 1677 1678 //===----------------------------------------------------------------------===// 1679 // Move Instructions. 1680 // 1681 1682 let neverHasSideEffects = 1 in 1683 def t2MOVr : T2sTwoReg<(outs GPRnopc:$Rd), (ins GPR:$Rm), IIC_iMOVr, 1684 "mov", ".w\t$Rd, $Rm", []> { 1685 let Inst{31-27} = 0b11101; 1686 let Inst{26-25} = 0b01; 1687 let Inst{24-21} = 0b0010; 1688 let Inst{19-16} = 0b1111; // Rn 1689 let Inst{14-12} = 0b000; 1690 let Inst{7-4} = 0b0000; 1691 } 1692 def : t2InstAlias<"movs${p}.w $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, 1693 pred:$p, CPSR)>; 1694 def : t2InstAlias<"movs${p} $Rd, $Rm", (t2MOVr GPRnopc:$Rd, GPR:$Rm, 1695 pred:$p, CPSR)>; 1696 1697 // AddedComplexity to ensure isel tries t2MOVi before t2MOVi16. 1698 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1, 1699 AddedComplexity = 1 in 1700 def t2MOVi : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), IIC_iMOVi, 1701 "mov", ".w\t$Rd, $imm", 1702 [(set rGPR:$Rd, t2_so_imm:$imm)]> { 1703 let Inst{31-27} = 0b11110; 1704 let Inst{25} = 0; 1705 let Inst{24-21} = 0b0010; 1706 let Inst{19-16} = 0b1111; // Rn 1707 let Inst{15} = 0; 1708 } 1709 1710 // cc_out is handled as part of the explicit mnemonic in the parser for 'mov'. 1711 // Use aliases to get that to play nice here. 1712 def : t2InstAlias<"movs${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1713 pred:$p, CPSR)>; 1714 def : t2InstAlias<"movs${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1715 pred:$p, CPSR)>; 1716 1717 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1718 pred:$p, zero_reg)>; 1719 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm, 1720 pred:$p, zero_reg)>; 1721 1722 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in 1723 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi, 1724 "movw", "\t$Rd, $imm", 1725 [(set rGPR:$Rd, imm0_65535:$imm)]> { 1726 let Inst{31-27} = 0b11110; 1727 let Inst{25} = 1; 1728 let Inst{24-21} = 0b0010; 1729 let Inst{20} = 0; // The S bit. 1730 let Inst{15} = 0; 1731 1732 bits<4> Rd; 1733 bits<16> imm; 1734 1735 let Inst{11-8} = Rd; 1736 let Inst{19-16} = imm{15-12}; 1737 let Inst{26} = imm{11}; 1738 let Inst{14-12} = imm{10-8}; 1739 let Inst{7-0} = imm{7-0}; 1740 let DecoderMethod = "DecodeT2MOVTWInstruction"; 1741 } 1742 1743 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1744 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 1745 1746 let Constraints = "$src = $Rd" in { 1747 def t2MOVTi16 : T2I<(outs rGPR:$Rd), 1748 (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi, 1749 "movt", "\t$Rd, $imm", 1750 [(set rGPR:$Rd, 1751 (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]> { 1752 let Inst{31-27} = 0b11110; 1753 let Inst{25} = 1; 1754 let Inst{24-21} = 0b0110; 1755 let Inst{20} = 0; // The S bit. 1756 let Inst{15} = 0; 1757 1758 bits<4> Rd; 1759 bits<16> imm; 1760 1761 let Inst{11-8} = Rd; 1762 let Inst{19-16} = imm{15-12}; 1763 let Inst{26} = imm{11}; 1764 let Inst{14-12} = imm{10-8}; 1765 let Inst{7-0} = imm{7-0}; 1766 let DecoderMethod = "DecodeT2MOVTWInstruction"; 1767 } 1768 1769 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd), 1770 (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>; 1771 } // Constraints 1772 1773 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>; 1774 1775 //===----------------------------------------------------------------------===// 1776 // Extend Instructions. 1777 // 1778 1779 // Sign extenders 1780 1781 def t2SXTB : T2I_ext_rrot<0b100, "sxtb", 1782 UnOpFrag<(sext_inreg node:$Src, i8)>>; 1783 def t2SXTH : T2I_ext_rrot<0b000, "sxth", 1784 UnOpFrag<(sext_inreg node:$Src, i16)>>; 1785 def t2SXTB16 : T2I_ext_rrot_sxtb16<0b010, "sxtb16">; 1786 1787 def t2SXTAB : T2I_exta_rrot<0b100, "sxtab", 1788 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; 1789 def t2SXTAH : T2I_exta_rrot<0b000, "sxtah", 1790 BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; 1791 def t2SXTAB16 : T2I_exta_rrot_np<0b010, "sxtab16">; 1792 1793 // Zero extenders 1794 1795 let AddedComplexity = 16 in { 1796 def t2UXTB : T2I_ext_rrot<0b101, "uxtb", 1797 UnOpFrag<(and node:$Src, 0x000000FF)>>; 1798 def t2UXTH : T2I_ext_rrot<0b001, "uxth", 1799 UnOpFrag<(and node:$Src, 0x0000FFFF)>>; 1800 def t2UXTB16 : T2I_ext_rrot_uxtb16<0b011, "uxtb16", 1801 UnOpFrag<(and node:$Src, 0x00FF00FF)>>; 1802 1803 // FIXME: This pattern incorrectly assumes the shl operator is a rotate. 1804 // The transformation should probably be done as a combiner action 1805 // instead so we can include a check for masking back in the upper 1806 // eight bits of the source into the lower eight bits of the result. 1807 //def : T2Pat<(and (shl rGPR:$Src, (i32 8)), 0xFF00FF), 1808 // (t2UXTB16 rGPR:$Src, 3)>, 1809 // Requires<[HasT2ExtractPack, IsThumb2]>; 1810 def : T2Pat<(and (srl rGPR:$Src, (i32 8)), 0xFF00FF), 1811 (t2UXTB16 rGPR:$Src, 1)>, 1812 Requires<[HasT2ExtractPack, IsThumb2]>; 1813 1814 def t2UXTAB : T2I_exta_rrot<0b101, "uxtab", 1815 BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; 1816 def t2UXTAH : T2I_exta_rrot<0b001, "uxtah", 1817 BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; 1818 def t2UXTAB16 : T2I_exta_rrot_np<0b011, "uxtab16">; 1819 } 1820 1821 //===----------------------------------------------------------------------===// 1822 // Arithmetic Instructions. 1823 // 1824 1825 defm t2ADD : T2I_bin_ii12rs<0b000, "add", 1826 BinOpFrag<(add node:$LHS, node:$RHS)>, 1>; 1827 defm t2SUB : T2I_bin_ii12rs<0b101, "sub", 1828 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1829 1830 // ADD and SUB with 's' bit set. No 12-bit immediate (T4) variants. 1831 // 1832 // Currently, t2ADDS/t2SUBS are pseudo opcodes that exist only in the 1833 // selection DAG. They are "lowered" to real t2ADD/t2SUB opcodes by 1834 // AdjustInstrPostInstrSelection where we determine whether or not to 1835 // set the "s" bit based on CPSR liveness. 1836 // 1837 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen 1838 // support for an optional CPSR definition that corresponds to the DAG 1839 // node's second value. We can then eliminate the implicit def of CPSR. 1840 defm t2ADDS : T2I_bin_s_irs <0b1000, "add", 1841 IIC_iALUi, IIC_iALUr, IIC_iALUsi, 1842 BinOpFrag<(ARMaddc node:$LHS, node:$RHS)>, 1>; 1843 defm t2SUBS : T2I_bin_s_irs <0b1101, "sub", 1844 IIC_iALUi, IIC_iALUr, IIC_iALUsi, 1845 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 1846 1847 let hasPostISelHook = 1 in { 1848 defm t2ADC : T2I_adde_sube_irs<0b1010, "adc", 1849 BinOpWithFlagFrag<(ARMadde node:$LHS, node:$RHS, node:$FLAG)>, 1>; 1850 defm t2SBC : T2I_adde_sube_irs<0b1011, "sbc", 1851 BinOpWithFlagFrag<(ARMsube node:$LHS, node:$RHS, node:$FLAG)>>; 1852 } 1853 1854 // RSB 1855 defm t2RSB : T2I_rbin_irs <0b1110, "rsb", 1856 BinOpFrag<(sub node:$LHS, node:$RHS)>>; 1857 1858 // FIXME: Eliminate them if we can write def : Pat patterns which defines 1859 // CPSR and the implicit def of CPSR is not needed. 1860 defm t2RSBS : T2I_rbin_s_is <0b1110, "rsb", 1861 BinOpFrag<(ARMsubc node:$LHS, node:$RHS)>>; 1862 1863 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form. 1864 // The assume-no-carry-in form uses the negation of the input since add/sub 1865 // assume opposite meanings of the carry flag (i.e., carry == !borrow). 1866 // See the definition of AddWithCarry() in the ARM ARM A2.2.1 for the gory 1867 // details. 1868 // The AddedComplexity preferences the first variant over the others since 1869 // it can be shrunk to a 16-bit wide encoding, while the others cannot. 1870 let AddedComplexity = 1 in 1871 def : T2Pat<(add GPR:$src, imm0_255_neg:$imm), 1872 (t2SUBri GPR:$src, imm0_255_neg:$imm)>; 1873 def : T2Pat<(add GPR:$src, t2_so_imm_neg:$imm), 1874 (t2SUBri GPR:$src, t2_so_imm_neg:$imm)>; 1875 def : T2Pat<(add GPR:$src, imm0_4095_neg:$imm), 1876 (t2SUBri12 GPR:$src, imm0_4095_neg:$imm)>; 1877 let AddedComplexity = 1 in 1878 def : T2Pat<(ARMaddc rGPR:$src, imm0_255_neg:$imm), 1879 (t2SUBSri rGPR:$src, imm0_255_neg:$imm)>; 1880 def : T2Pat<(ARMaddc rGPR:$src, t2_so_imm_neg:$imm), 1881 (t2SUBSri rGPR:$src, t2_so_imm_neg:$imm)>; 1882 // The with-carry-in form matches bitwise not instead of the negation. 1883 // Effectively, the inverse interpretation of the carry flag already accounts 1884 // for part of the negation. 1885 let AddedComplexity = 1 in 1886 def : T2Pat<(ARMadde rGPR:$src, imm0_255_not:$imm, CPSR), 1887 (t2SBCri rGPR:$src, imm0_255_not:$imm)>; 1888 def : T2Pat<(ARMadde rGPR:$src, t2_so_imm_not:$imm, CPSR), 1889 (t2SBCri rGPR:$src, t2_so_imm_not:$imm)>; 1890 1891 // Select Bytes -- for disassembly only 1892 1893 def t2SEL : T2ThreeReg<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), 1894 NoItinerary, "sel", "\t$Rd, $Rn, $Rm", []>, 1895 Requires<[IsThumb2, HasThumb2DSP]> { 1896 let Inst{31-27} = 0b11111; 1897 let Inst{26-24} = 0b010; 1898 let Inst{23} = 0b1; 1899 let Inst{22-20} = 0b010; 1900 let Inst{15-12} = 0b1111; 1901 let Inst{7} = 0b1; 1902 let Inst{6-4} = 0b000; 1903 } 1904 1905 // A6.3.13, A6.3.14, A6.3.15 Parallel addition and subtraction (signed/unsigned) 1906 // And Miscellaneous operations -- for disassembly only 1907 class T2I_pam<bits<3> op22_20, bits<4> op7_4, string opc, 1908 list<dag> pat = [/* For disassembly only; pattern left blank */], 1909 dag iops = (ins rGPR:$Rn, rGPR:$Rm), 1910 string asm = "\t$Rd, $Rn, $Rm"> 1911 : T2I<(outs rGPR:$Rd), iops, NoItinerary, opc, asm, pat>, 1912 Requires<[IsThumb2, HasThumb2DSP]> { 1913 let Inst{31-27} = 0b11111; 1914 let Inst{26-23} = 0b0101; 1915 let Inst{22-20} = op22_20; 1916 let Inst{15-12} = 0b1111; 1917 let Inst{7-4} = op7_4; 1918 1919 bits<4> Rd; 1920 bits<4> Rn; 1921 bits<4> Rm; 1922 1923 let Inst{11-8} = Rd; 1924 let Inst{19-16} = Rn; 1925 let Inst{3-0} = Rm; 1926 } 1927 1928 // Saturating add/subtract -- for disassembly only 1929 1930 def t2QADD : T2I_pam<0b000, 0b1000, "qadd", 1931 [(set rGPR:$Rd, (int_arm_qadd rGPR:$Rn, rGPR:$Rm))], 1932 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1933 def t2QADD16 : T2I_pam<0b001, 0b0001, "qadd16">; 1934 def t2QADD8 : T2I_pam<0b000, 0b0001, "qadd8">; 1935 def t2QASX : T2I_pam<0b010, 0b0001, "qasx">; 1936 def t2QDADD : T2I_pam<0b000, 0b1001, "qdadd", [], 1937 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1938 def t2QDSUB : T2I_pam<0b000, 0b1011, "qdsub", [], 1939 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1940 def t2QSAX : T2I_pam<0b110, 0b0001, "qsax">; 1941 def t2QSUB : T2I_pam<0b000, 0b1010, "qsub", 1942 [(set rGPR:$Rd, (int_arm_qsub rGPR:$Rn, rGPR:$Rm))], 1943 (ins rGPR:$Rm, rGPR:$Rn), "\t$Rd, $Rm, $Rn">; 1944 def t2QSUB16 : T2I_pam<0b101, 0b0001, "qsub16">; 1945 def t2QSUB8 : T2I_pam<0b100, 0b0001, "qsub8">; 1946 def t2UQADD16 : T2I_pam<0b001, 0b0101, "uqadd16">; 1947 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">; 1948 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">; 1949 def t2UQSAX : T2I_pam<0b110, 0b0101, "uqsax">; 1950 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">; 1951 def t2UQSUB8 : T2I_pam<0b100, 0b0101, "uqsub8">; 1952 1953 // Signed/Unsigned add/subtract -- for disassembly only 1954 1955 def t2SASX : T2I_pam<0b010, 0b0000, "sasx">; 1956 def t2SADD16 : T2I_pam<0b001, 0b0000, "sadd16">; 1957 def t2SADD8 : T2I_pam<0b000, 0b0000, "sadd8">; 1958 def t2SSAX : T2I_pam<0b110, 0b0000, "ssax">; 1959 def t2SSUB16 : T2I_pam<0b101, 0b0000, "ssub16">; 1960 def t2SSUB8 : T2I_pam<0b100, 0b0000, "ssub8">; 1961 def t2UASX : T2I_pam<0b010, 0b0100, "uasx">; 1962 def t2UADD16 : T2I_pam<0b001, 0b0100, "uadd16">; 1963 def t2UADD8 : T2I_pam<0b000, 0b0100, "uadd8">; 1964 def t2USAX : T2I_pam<0b110, 0b0100, "usax">; 1965 def t2USUB16 : T2I_pam<0b101, 0b0100, "usub16">; 1966 def t2USUB8 : T2I_pam<0b100, 0b0100, "usub8">; 1967 1968 // Signed/Unsigned halving add/subtract -- for disassembly only 1969 1970 def t2SHASX : T2I_pam<0b010, 0b0010, "shasx">; 1971 def t2SHADD16 : T2I_pam<0b001, 0b0010, "shadd16">; 1972 def t2SHADD8 : T2I_pam<0b000, 0b0010, "shadd8">; 1973 def t2SHSAX : T2I_pam<0b110, 0b0010, "shsax">; 1974 def t2SHSUB16 : T2I_pam<0b101, 0b0010, "shsub16">; 1975 def t2SHSUB8 : T2I_pam<0b100, 0b0010, "shsub8">; 1976 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">; 1977 def t2UHADD16 : T2I_pam<0b001, 0b0110, "uhadd16">; 1978 def t2UHADD8 : T2I_pam<0b000, 0b0110, "uhadd8">; 1979 def t2UHSAX : T2I_pam<0b110, 0b0110, "uhsax">; 1980 def t2UHSUB16 : T2I_pam<0b101, 0b0110, "uhsub16">; 1981 def t2UHSUB8 : T2I_pam<0b100, 0b0110, "uhsub8">; 1982 1983 // Helper class for disassembly only 1984 // A6.3.16 & A6.3.17 1985 // T2Imac - Thumb2 multiply [accumulate, and absolute difference] instructions. 1986 class T2ThreeReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 1987 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1988 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 1989 let Inst{31-27} = 0b11111; 1990 let Inst{26-24} = 0b011; 1991 let Inst{23} = long; 1992 let Inst{22-20} = op22_20; 1993 let Inst{7-4} = op7_4; 1994 } 1995 1996 class T2FourReg_mac<bit long, bits<3> op22_20, bits<4> op7_4, dag oops, 1997 dag iops, InstrItinClass itin, string opc, string asm, list<dag> pattern> 1998 : T2FourReg<oops, iops, itin, opc, asm, pattern> { 1999 let Inst{31-27} = 0b11111; 2000 let Inst{26-24} = 0b011; 2001 let Inst{23} = long; 2002 let Inst{22-20} = op22_20; 2003 let Inst{7-4} = op7_4; 2004 } 2005 2006 // Unsigned Sum of Absolute Differences [and Accumulate]. 2007 def t2USAD8 : T2ThreeReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2008 (ins rGPR:$Rn, rGPR:$Rm), 2009 NoItinerary, "usad8", "\t$Rd, $Rn, $Rm", []>, 2010 Requires<[IsThumb2, HasThumb2DSP]> { 2011 let Inst{15-12} = 0b1111; 2012 } 2013 def t2USADA8 : T2FourReg_mac<0, 0b111, 0b0000, (outs rGPR:$Rd), 2014 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), NoItinerary, 2015 "usada8", "\t$Rd, $Rn, $Rm, $Ra", []>, 2016 Requires<[IsThumb2, HasThumb2DSP]>; 2017 2018 // Signed/Unsigned saturate. 2019 class T2SatI<dag oops, dag iops, InstrItinClass itin, 2020 string opc, string asm, list<dag> pattern> 2021 : T2I<oops, iops, itin, opc, asm, pattern> { 2022 bits<4> Rd; 2023 bits<4> Rn; 2024 bits<5> sat_imm; 2025 bits<7> sh; 2026 2027 let Inst{11-8} = Rd; 2028 let Inst{19-16} = Rn; 2029 let Inst{4-0} = sat_imm; 2030 let Inst{21} = sh{5}; 2031 let Inst{14-12} = sh{4-2}; 2032 let Inst{7-6} = sh{1-0}; 2033 } 2034 2035 def t2SSAT: T2SatI< 2036 (outs rGPR:$Rd), 2037 (ins imm1_32:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2038 NoItinerary, "ssat", "\t$Rd, $sat_imm, $Rn$sh", []> { 2039 let Inst{31-27} = 0b11110; 2040 let Inst{25-22} = 0b1100; 2041 let Inst{20} = 0; 2042 let Inst{15} = 0; 2043 let Inst{5} = 0; 2044 } 2045 2046 def t2SSAT16: T2SatI< 2047 (outs rGPR:$Rd), (ins imm1_16:$sat_imm, rGPR:$Rn), NoItinerary, 2048 "ssat16", "\t$Rd, $sat_imm, $Rn", []>, 2049 Requires<[IsThumb2, HasThumb2DSP]> { 2050 let Inst{31-27} = 0b11110; 2051 let Inst{25-22} = 0b1100; 2052 let Inst{20} = 0; 2053 let Inst{15} = 0; 2054 let Inst{21} = 1; // sh = '1' 2055 let Inst{14-12} = 0b000; // imm3 = '000' 2056 let Inst{7-6} = 0b00; // imm2 = '00' 2057 let Inst{5-4} = 0b00; 2058 } 2059 2060 def t2USAT: T2SatI< 2061 (outs rGPR:$Rd), 2062 (ins imm0_31:$sat_imm, rGPR:$Rn, t2_shift_imm:$sh), 2063 NoItinerary, "usat", "\t$Rd, $sat_imm, $Rn$sh", []> { 2064 let Inst{31-27} = 0b11110; 2065 let Inst{25-22} = 0b1110; 2066 let Inst{20} = 0; 2067 let Inst{15} = 0; 2068 } 2069 2070 def t2USAT16: T2SatI<(outs rGPR:$Rd), (ins imm0_15:$sat_imm, rGPR:$Rn), 2071 NoItinerary, 2072 "usat16", "\t$Rd, $sat_imm, $Rn", []>, 2073 Requires<[IsThumb2, HasThumb2DSP]> { 2074 let Inst{31-22} = 0b1111001110; 2075 let Inst{20} = 0; 2076 let Inst{15} = 0; 2077 let Inst{21} = 1; // sh = '1' 2078 let Inst{14-12} = 0b000; // imm3 = '000' 2079 let Inst{7-6} = 0b00; // imm2 = '00' 2080 let Inst{5-4} = 0b00; 2081 } 2082 2083 def : T2Pat<(int_arm_ssat GPR:$a, imm:$pos), (t2SSAT imm:$pos, GPR:$a, 0)>; 2084 def : T2Pat<(int_arm_usat GPR:$a, imm:$pos), (t2USAT imm:$pos, GPR:$a, 0)>; 2085 2086 //===----------------------------------------------------------------------===// 2087 // Shift and rotate Instructions. 2088 // 2089 2090 defm t2LSL : T2I_sh_ir<0b00, "lsl", imm0_31, 2091 BinOpFrag<(shl node:$LHS, node:$RHS)>, "t2LSL">; 2092 defm t2LSR : T2I_sh_ir<0b01, "lsr", imm_sr, 2093 BinOpFrag<(srl node:$LHS, node:$RHS)>, "t2LSR">; 2094 defm t2ASR : T2I_sh_ir<0b10, "asr", imm_sr, 2095 BinOpFrag<(sra node:$LHS, node:$RHS)>, "t2ASR">; 2096 defm t2ROR : T2I_sh_ir<0b11, "ror", imm0_31, 2097 BinOpFrag<(rotr node:$LHS, node:$RHS)>, "t2ROR">; 2098 2099 // (rotr x, (and y, 0x...1f)) ==> (ROR x, y) 2100 def : Pat<(rotr rGPR:$lhs, (and rGPR:$rhs, lo5AllOne)), 2101 (t2RORrr rGPR:$lhs, rGPR:$rhs)>; 2102 2103 let Uses = [CPSR] in { 2104 def t2RRX : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2105 "rrx", "\t$Rd, $Rm", 2106 [(set rGPR:$Rd, (ARMrrx rGPR:$Rm))]> { 2107 let Inst{31-27} = 0b11101; 2108 let Inst{26-25} = 0b01; 2109 let Inst{24-21} = 0b0010; 2110 let Inst{19-16} = 0b1111; // Rn 2111 let Inst{14-12} = 0b000; 2112 let Inst{7-4} = 0b0011; 2113 } 2114 } 2115 2116 let isCodeGenOnly = 1, Defs = [CPSR] in { 2117 def t2MOVsrl_flag : T2TwoRegShiftImm< 2118 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2119 "lsrs", ".w\t$Rd, $Rm, #1", 2120 [(set rGPR:$Rd, (ARMsrl_flag rGPR:$Rm))]> { 2121 let Inst{31-27} = 0b11101; 2122 let Inst{26-25} = 0b01; 2123 let Inst{24-21} = 0b0010; 2124 let Inst{20} = 1; // The S bit. 2125 let Inst{19-16} = 0b1111; // Rn 2126 let Inst{5-4} = 0b01; // Shift type. 2127 // Shift amount = Inst{14-12:7-6} = 1. 2128 let Inst{14-12} = 0b000; 2129 let Inst{7-6} = 0b01; 2130 } 2131 def t2MOVsra_flag : T2TwoRegShiftImm< 2132 (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iMOVsi, 2133 "asrs", ".w\t$Rd, $Rm, #1", 2134 [(set rGPR:$Rd, (ARMsra_flag rGPR:$Rm))]> { 2135 let Inst{31-27} = 0b11101; 2136 let Inst{26-25} = 0b01; 2137 let Inst{24-21} = 0b0010; 2138 let Inst{20} = 1; // The S bit. 2139 let Inst{19-16} = 0b1111; // Rn 2140 let Inst{5-4} = 0b10; // Shift type. 2141 // Shift amount = Inst{14-12:7-6} = 1. 2142 let Inst{14-12} = 0b000; 2143 let Inst{7-6} = 0b01; 2144 } 2145 } 2146 2147 //===----------------------------------------------------------------------===// 2148 // Bitwise Instructions. 2149 // 2150 2151 defm t2AND : T2I_bin_w_irs<0b0000, "and", 2152 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2153 BinOpFrag<(and node:$LHS, node:$RHS)>, "t2AND", 1>; 2154 defm t2ORR : T2I_bin_w_irs<0b0010, "orr", 2155 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2156 BinOpFrag<(or node:$LHS, node:$RHS)>, "t2ORR", 1>; 2157 defm t2EOR : T2I_bin_w_irs<0b0100, "eor", 2158 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2159 BinOpFrag<(xor node:$LHS, node:$RHS)>, "t2EOR", 1>; 2160 2161 defm t2BIC : T2I_bin_w_irs<0b0001, "bic", 2162 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2163 BinOpFrag<(and node:$LHS, (not node:$RHS))>, 2164 "t2BIC">; 2165 2166 class T2BitFI<dag oops, dag iops, InstrItinClass itin, 2167 string opc, string asm, list<dag> pattern> 2168 : T2I<oops, iops, itin, opc, asm, pattern> { 2169 bits<4> Rd; 2170 bits<5> msb; 2171 bits<5> lsb; 2172 2173 let Inst{11-8} = Rd; 2174 let Inst{4-0} = msb{4-0}; 2175 let Inst{14-12} = lsb{4-2}; 2176 let Inst{7-6} = lsb{1-0}; 2177 } 2178 2179 class T2TwoRegBitFI<dag oops, dag iops, InstrItinClass itin, 2180 string opc, string asm, list<dag> pattern> 2181 : T2BitFI<oops, iops, itin, opc, asm, pattern> { 2182 bits<4> Rn; 2183 2184 let Inst{19-16} = Rn; 2185 } 2186 2187 let Constraints = "$src = $Rd" in 2188 def t2BFC : T2BitFI<(outs rGPR:$Rd), (ins rGPR:$src, bf_inv_mask_imm:$imm), 2189 IIC_iUNAsi, "bfc", "\t$Rd, $imm", 2190 [(set rGPR:$Rd, (and rGPR:$src, bf_inv_mask_imm:$imm))]> { 2191 let Inst{31-27} = 0b11110; 2192 let Inst{26} = 0; // should be 0. 2193 let Inst{25} = 1; 2194 let Inst{24-20} = 0b10110; 2195 let Inst{19-16} = 0b1111; // Rn 2196 let Inst{15} = 0; 2197 let Inst{5} = 0; // should be 0. 2198 2199 bits<10> imm; 2200 let msb{4-0} = imm{9-5}; 2201 let lsb{4-0} = imm{4-0}; 2202 } 2203 2204 def t2SBFX: T2TwoRegBitFI< 2205 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2206 IIC_iUNAsi, "sbfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2207 let Inst{31-27} = 0b11110; 2208 let Inst{25} = 1; 2209 let Inst{24-20} = 0b10100; 2210 let Inst{15} = 0; 2211 } 2212 2213 def t2UBFX: T2TwoRegBitFI< 2214 (outs rGPR:$Rd), (ins rGPR:$Rn, imm0_31:$lsb, imm1_32:$msb), 2215 IIC_iUNAsi, "ubfx", "\t$Rd, $Rn, $lsb, $msb", []> { 2216 let Inst{31-27} = 0b11110; 2217 let Inst{25} = 1; 2218 let Inst{24-20} = 0b11100; 2219 let Inst{15} = 0; 2220 } 2221 2222 // A8.6.18 BFI - Bitfield insert (Encoding T1) 2223 let Constraints = "$src = $Rd" in { 2224 def t2BFI : T2TwoRegBitFI<(outs rGPR:$Rd), 2225 (ins rGPR:$src, rGPR:$Rn, bf_inv_mask_imm:$imm), 2226 IIC_iBITi, "bfi", "\t$Rd, $Rn, $imm", 2227 [(set rGPR:$Rd, (ARMbfi rGPR:$src, rGPR:$Rn, 2228 bf_inv_mask_imm:$imm))]> { 2229 let Inst{31-27} = 0b11110; 2230 let Inst{26} = 0; // should be 0. 2231 let Inst{25} = 1; 2232 let Inst{24-20} = 0b10110; 2233 let Inst{15} = 0; 2234 let Inst{5} = 0; // should be 0. 2235 2236 bits<10> imm; 2237 let msb{4-0} = imm{9-5}; 2238 let lsb{4-0} = imm{4-0}; 2239 } 2240 } 2241 2242 defm t2ORN : T2I_bin_irs<0b0011, "orn", 2243 IIC_iBITi, IIC_iBITr, IIC_iBITsi, 2244 BinOpFrag<(or node:$LHS, (not node:$RHS))>, 2245 "t2ORN", 0, "">; 2246 2247 /// T2I_un_irs - Defines a set of (op reg, {so_imm|r|so_reg}) patterns for a 2248 /// unary operation that produces a value. These are predicable and can be 2249 /// changed to modify CPSR. 2250 multiclass T2I_un_irs<bits<4> opcod, string opc, 2251 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis, 2252 PatFrag opnode, bit Cheap = 0, bit ReMat = 0> { 2253 // shifted imm 2254 def i : T2sOneRegImm<(outs rGPR:$Rd), (ins t2_so_imm:$imm), iii, 2255 opc, "\t$Rd, $imm", 2256 [(set rGPR:$Rd, (opnode t2_so_imm:$imm))]> { 2257 let isAsCheapAsAMove = Cheap; 2258 let isReMaterializable = ReMat; 2259 let Inst{31-27} = 0b11110; 2260 let Inst{25} = 0; 2261 let Inst{24-21} = opcod; 2262 let Inst{19-16} = 0b1111; // Rn 2263 let Inst{15} = 0; 2264 } 2265 // register 2266 def r : T2sTwoReg<(outs rGPR:$Rd), (ins rGPR:$Rm), iir, 2267 opc, ".w\t$Rd, $Rm", 2268 [(set rGPR:$Rd, (opnode rGPR:$Rm))]> { 2269 let Inst{31-27} = 0b11101; 2270 let Inst{26-25} = 0b01; 2271 let Inst{24-21} = opcod; 2272 let Inst{19-16} = 0b1111; // Rn 2273 let Inst{14-12} = 0b000; // imm3 2274 let Inst{7-6} = 0b00; // imm2 2275 let Inst{5-4} = 0b00; // type 2276 } 2277 // shifted register 2278 def s : T2sOneRegShiftedReg<(outs rGPR:$Rd), (ins t2_so_reg:$ShiftedRm), iis, 2279 opc, ".w\t$Rd, $ShiftedRm", 2280 [(set rGPR:$Rd, (opnode t2_so_reg:$ShiftedRm))]> { 2281 let Inst{31-27} = 0b11101; 2282 let Inst{26-25} = 0b01; 2283 let Inst{24-21} = opcod; 2284 let Inst{19-16} = 0b1111; // Rn 2285 } 2286 } 2287 2288 // Prefer over of t2EORri ra, rb, -1 because mvn has 16-bit version 2289 let AddedComplexity = 1 in 2290 defm t2MVN : T2I_un_irs <0b0011, "mvn", 2291 IIC_iMVNi, IIC_iMVNr, IIC_iMVNsi, 2292 UnOpFrag<(not node:$Src)>, 1, 1>; 2293 2294 let AddedComplexity = 1 in 2295 def : T2Pat<(and rGPR:$src, t2_so_imm_not:$imm), 2296 (t2BICri rGPR:$src, t2_so_imm_not:$imm)>; 2297 2298 // FIXME: Disable this pattern on Darwin to workaround an assembler bug. 2299 def : T2Pat<(or rGPR:$src, t2_so_imm_not:$imm), 2300 (t2ORNri rGPR:$src, t2_so_imm_not:$imm)>, 2301 Requires<[IsThumb2]>; 2302 2303 def : T2Pat<(t2_so_imm_not:$src), 2304 (t2MVNi t2_so_imm_not:$src)>; 2305 2306 //===----------------------------------------------------------------------===// 2307 // Multiply Instructions. 2308 // 2309 let isCommutable = 1 in 2310 def t2MUL: T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2311 "mul", "\t$Rd, $Rn, $Rm", 2312 [(set rGPR:$Rd, (mul rGPR:$Rn, rGPR:$Rm))]> { 2313 let Inst{31-27} = 0b11111; 2314 let Inst{26-23} = 0b0110; 2315 let Inst{22-20} = 0b000; 2316 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2317 let Inst{7-4} = 0b0000; // Multiply 2318 } 2319 2320 def t2MLA: T2FourReg< 2321 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2322 "mla", "\t$Rd, $Rn, $Rm, $Ra", 2323 [(set rGPR:$Rd, (add (mul rGPR:$Rn, rGPR:$Rm), rGPR:$Ra))]> { 2324 let Inst{31-27} = 0b11111; 2325 let Inst{26-23} = 0b0110; 2326 let Inst{22-20} = 0b000; 2327 let Inst{7-4} = 0b0000; // Multiply 2328 } 2329 2330 def t2MLS: T2FourReg< 2331 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2332 "mls", "\t$Rd, $Rn, $Rm, $Ra", 2333 [(set rGPR:$Rd, (sub rGPR:$Ra, (mul rGPR:$Rn, rGPR:$Rm)))]> { 2334 let Inst{31-27} = 0b11111; 2335 let Inst{26-23} = 0b0110; 2336 let Inst{22-20} = 0b000; 2337 let Inst{7-4} = 0b0001; // Multiply and Subtract 2338 } 2339 2340 // Extra precision multiplies with low / high results 2341 let neverHasSideEffects = 1 in { 2342 let isCommutable = 1 in { 2343 def t2SMULL : T2MulLong<0b000, 0b0000, 2344 (outs rGPR:$RdLo, rGPR:$RdHi), 2345 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 2346 "smull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2347 2348 def t2UMULL : T2MulLong<0b010, 0b0000, 2349 (outs rGPR:$RdLo, rGPR:$RdHi), 2350 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL64, 2351 "umull", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2352 } // isCommutable 2353 2354 // Multiply + accumulate 2355 def t2SMLAL : T2MulLong<0b100, 0b0000, 2356 (outs rGPR:$RdLo, rGPR:$RdHi), 2357 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2358 "smlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2359 2360 def t2UMLAL : T2MulLong<0b110, 0b0000, 2361 (outs rGPR:$RdLo, rGPR:$RdHi), 2362 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2363 "umlal", "\t$RdLo, $RdHi, $Rn, $Rm", []>; 2364 2365 def t2UMAAL : T2MulLong<0b110, 0b0110, 2366 (outs rGPR:$RdLo, rGPR:$RdHi), 2367 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, 2368 "umaal", "\t$RdLo, $RdHi, $Rn, $Rm", []>, 2369 Requires<[IsThumb2, HasThumb2DSP]>; 2370 } // neverHasSideEffects 2371 2372 // Rounding variants of the below included for disassembly only 2373 2374 // Most significant word multiply 2375 def t2SMMUL : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2376 "smmul", "\t$Rd, $Rn, $Rm", 2377 [(set rGPR:$Rd, (mulhs rGPR:$Rn, rGPR:$Rm))]>, 2378 Requires<[IsThumb2, HasThumb2DSP]> { 2379 let Inst{31-27} = 0b11111; 2380 let Inst{26-23} = 0b0110; 2381 let Inst{22-20} = 0b101; 2382 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2383 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2384 } 2385 2386 def t2SMMULR : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL32, 2387 "smmulr", "\t$Rd, $Rn, $Rm", []>, 2388 Requires<[IsThumb2, HasThumb2DSP]> { 2389 let Inst{31-27} = 0b11111; 2390 let Inst{26-23} = 0b0110; 2391 let Inst{22-20} = 0b101; 2392 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2393 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2394 } 2395 2396 def t2SMMLA : T2FourReg< 2397 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2398 "smmla", "\t$Rd, $Rn, $Rm, $Ra", 2399 [(set rGPR:$Rd, (add (mulhs rGPR:$Rm, rGPR:$Rn), rGPR:$Ra))]>, 2400 Requires<[IsThumb2, HasThumb2DSP]> { 2401 let Inst{31-27} = 0b11111; 2402 let Inst{26-23} = 0b0110; 2403 let Inst{22-20} = 0b101; 2404 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2405 } 2406 2407 def t2SMMLAR: T2FourReg< 2408 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2409 "smmlar", "\t$Rd, $Rn, $Rm, $Ra", []>, 2410 Requires<[IsThumb2, HasThumb2DSP]> { 2411 let Inst{31-27} = 0b11111; 2412 let Inst{26-23} = 0b0110; 2413 let Inst{22-20} = 0b101; 2414 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2415 } 2416 2417 def t2SMMLS: T2FourReg< 2418 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2419 "smmls", "\t$Rd, $Rn, $Rm, $Ra", 2420 [(set rGPR:$Rd, (sub rGPR:$Ra, (mulhs rGPR:$Rn, rGPR:$Rm)))]>, 2421 Requires<[IsThumb2, HasThumb2DSP]> { 2422 let Inst{31-27} = 0b11111; 2423 let Inst{26-23} = 0b0110; 2424 let Inst{22-20} = 0b110; 2425 let Inst{7-4} = 0b0000; // No Rounding (Inst{4} = 0) 2426 } 2427 2428 def t2SMMLSR:T2FourReg< 2429 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, 2430 "smmlsr", "\t$Rd, $Rn, $Rm, $Ra", []>, 2431 Requires<[IsThumb2, HasThumb2DSP]> { 2432 let Inst{31-27} = 0b11111; 2433 let Inst{26-23} = 0b0110; 2434 let Inst{22-20} = 0b110; 2435 let Inst{7-4} = 0b0001; // Rounding (Inst{4} = 1) 2436 } 2437 2438 multiclass T2I_smul<string opc, PatFrag opnode> { 2439 def BB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2440 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm", 2441 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), 2442 (sext_inreg rGPR:$Rm, i16)))]>, 2443 Requires<[IsThumb2, HasThumb2DSP]> { 2444 let Inst{31-27} = 0b11111; 2445 let Inst{26-23} = 0b0110; 2446 let Inst{22-20} = 0b001; 2447 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2448 let Inst{7-6} = 0b00; 2449 let Inst{5-4} = 0b00; 2450 } 2451 2452 def BT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2453 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm", 2454 [(set rGPR:$Rd, (opnode (sext_inreg rGPR:$Rn, i16), 2455 (sra rGPR:$Rm, (i32 16))))]>, 2456 Requires<[IsThumb2, HasThumb2DSP]> { 2457 let Inst{31-27} = 0b11111; 2458 let Inst{26-23} = 0b0110; 2459 let Inst{22-20} = 0b001; 2460 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2461 let Inst{7-6} = 0b00; 2462 let Inst{5-4} = 0b01; 2463 } 2464 2465 def TB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2466 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm", 2467 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)), 2468 (sext_inreg rGPR:$Rm, i16)))]>, 2469 Requires<[IsThumb2, HasThumb2DSP]> { 2470 let Inst{31-27} = 0b11111; 2471 let Inst{26-23} = 0b0110; 2472 let Inst{22-20} = 0b001; 2473 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2474 let Inst{7-6} = 0b00; 2475 let Inst{5-4} = 0b10; 2476 } 2477 2478 def TT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2479 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm", 2480 [(set rGPR:$Rd, (opnode (sra rGPR:$Rn, (i32 16)), 2481 (sra rGPR:$Rm, (i32 16))))]>, 2482 Requires<[IsThumb2, HasThumb2DSP]> { 2483 let Inst{31-27} = 0b11111; 2484 let Inst{26-23} = 0b0110; 2485 let Inst{22-20} = 0b001; 2486 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2487 let Inst{7-6} = 0b00; 2488 let Inst{5-4} = 0b11; 2489 } 2490 2491 def WB : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2492 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm", 2493 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn, 2494 (sext_inreg rGPR:$Rm, i16)), (i32 16)))]>, 2495 Requires<[IsThumb2, HasThumb2DSP]> { 2496 let Inst{31-27} = 0b11111; 2497 let Inst{26-23} = 0b0110; 2498 let Inst{22-20} = 0b011; 2499 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2500 let Inst{7-6} = 0b00; 2501 let Inst{5-4} = 0b00; 2502 } 2503 2504 def WT : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iMUL16, 2505 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm", 2506 [(set rGPR:$Rd, (sra (opnode rGPR:$Rn, 2507 (sra rGPR:$Rm, (i32 16))), (i32 16)))]>, 2508 Requires<[IsThumb2, HasThumb2DSP]> { 2509 let Inst{31-27} = 0b11111; 2510 let Inst{26-23} = 0b0110; 2511 let Inst{22-20} = 0b011; 2512 let Inst{15-12} = 0b1111; // Ra = 0b1111 (no accumulate) 2513 let Inst{7-6} = 0b00; 2514 let Inst{5-4} = 0b01; 2515 } 2516 } 2517 2518 2519 multiclass T2I_smla<string opc, PatFrag opnode> { 2520 def BB : T2FourReg< 2521 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2522 !strconcat(opc, "bb"), "\t$Rd, $Rn, $Rm, $Ra", 2523 [(set rGPR:$Rd, (add rGPR:$Ra, 2524 (opnode (sext_inreg rGPR:$Rn, i16), 2525 (sext_inreg rGPR:$Rm, i16))))]>, 2526 Requires<[IsThumb2, HasThumb2DSP]> { 2527 let Inst{31-27} = 0b11111; 2528 let Inst{26-23} = 0b0110; 2529 let Inst{22-20} = 0b001; 2530 let Inst{7-6} = 0b00; 2531 let Inst{5-4} = 0b00; 2532 } 2533 2534 def BT : T2FourReg< 2535 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2536 !strconcat(opc, "bt"), "\t$Rd, $Rn, $Rm, $Ra", 2537 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sext_inreg rGPR:$Rn, i16), 2538 (sra rGPR:$Rm, (i32 16)))))]>, 2539 Requires<[IsThumb2, HasThumb2DSP]> { 2540 let Inst{31-27} = 0b11111; 2541 let Inst{26-23} = 0b0110; 2542 let Inst{22-20} = 0b001; 2543 let Inst{7-6} = 0b00; 2544 let Inst{5-4} = 0b01; 2545 } 2546 2547 def TB : T2FourReg< 2548 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2549 !strconcat(opc, "tb"), "\t$Rd, $Rn, $Rm, $Ra", 2550 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), 2551 (sext_inreg rGPR:$Rm, i16))))]>, 2552 Requires<[IsThumb2, HasThumb2DSP]> { 2553 let Inst{31-27} = 0b11111; 2554 let Inst{26-23} = 0b0110; 2555 let Inst{22-20} = 0b001; 2556 let Inst{7-6} = 0b00; 2557 let Inst{5-4} = 0b10; 2558 } 2559 2560 def TT : T2FourReg< 2561 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2562 !strconcat(opc, "tt"), "\t$Rd, $Rn, $Rm, $Ra", 2563 [(set rGPR:$Rd, (add rGPR:$Ra, (opnode (sra rGPR:$Rn, (i32 16)), 2564 (sra rGPR:$Rm, (i32 16)))))]>, 2565 Requires<[IsThumb2, HasThumb2DSP]> { 2566 let Inst{31-27} = 0b11111; 2567 let Inst{26-23} = 0b0110; 2568 let Inst{22-20} = 0b001; 2569 let Inst{7-6} = 0b00; 2570 let Inst{5-4} = 0b11; 2571 } 2572 2573 def WB : T2FourReg< 2574 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2575 !strconcat(opc, "wb"), "\t$Rd, $Rn, $Rm, $Ra", 2576 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn, 2577 (sext_inreg rGPR:$Rm, i16)), (i32 16))))]>, 2578 Requires<[IsThumb2, HasThumb2DSP]> { 2579 let Inst{31-27} = 0b11111; 2580 let Inst{26-23} = 0b0110; 2581 let Inst{22-20} = 0b011; 2582 let Inst{7-6} = 0b00; 2583 let Inst{5-4} = 0b00; 2584 } 2585 2586 def WT : T2FourReg< 2587 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC16, 2588 !strconcat(opc, "wt"), "\t$Rd, $Rn, $Rm, $Ra", 2589 [(set rGPR:$Rd, (add rGPR:$Ra, (sra (opnode rGPR:$Rn, 2590 (sra rGPR:$Rm, (i32 16))), (i32 16))))]>, 2591 Requires<[IsThumb2, HasThumb2DSP]> { 2592 let Inst{31-27} = 0b11111; 2593 let Inst{26-23} = 0b0110; 2594 let Inst{22-20} = 0b011; 2595 let Inst{7-6} = 0b00; 2596 let Inst{5-4} = 0b01; 2597 } 2598 } 2599 2600 defm t2SMUL : T2I_smul<"smul", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2601 defm t2SMLA : T2I_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>; 2602 2603 // Halfword multiple accumulate long: SMLAL<x><y> 2604 def t2SMLALBB : T2FourReg_mac<1, 0b100, 0b1000, (outs rGPR:$Ra,rGPR:$Rd), 2605 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbb", "\t$Ra, $Rd, $Rn, $Rm", 2606 [/* For disassembly only; pattern left blank */]>, 2607 Requires<[IsThumb2, HasThumb2DSP]>; 2608 def t2SMLALBT : T2FourReg_mac<1, 0b100, 0b1001, (outs rGPR:$Ra,rGPR:$Rd), 2609 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlalbt", "\t$Ra, $Rd, $Rn, $Rm", 2610 [/* For disassembly only; pattern left blank */]>, 2611 Requires<[IsThumb2, HasThumb2DSP]>; 2612 def t2SMLALTB : T2FourReg_mac<1, 0b100, 0b1010, (outs rGPR:$Ra,rGPR:$Rd), 2613 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltb", "\t$Ra, $Rd, $Rn, $Rm", 2614 [/* For disassembly only; pattern left blank */]>, 2615 Requires<[IsThumb2, HasThumb2DSP]>; 2616 def t2SMLALTT : T2FourReg_mac<1, 0b100, 0b1011, (outs rGPR:$Ra,rGPR:$Rd), 2617 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaltt", "\t$Ra, $Rd, $Rn, $Rm", 2618 [/* For disassembly only; pattern left blank */]>, 2619 Requires<[IsThumb2, HasThumb2DSP]>; 2620 2621 // Dual halfword multiple: SMUAD, SMUSD, SMLAD, SMLSD, SMLALD, SMLSLD 2622 def t2SMUAD: T2ThreeReg_mac< 2623 0, 0b010, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2624 IIC_iMAC32, "smuad", "\t$Rd, $Rn, $Rm", []>, 2625 Requires<[IsThumb2, HasThumb2DSP]> { 2626 let Inst{15-12} = 0b1111; 2627 } 2628 def t2SMUADX:T2ThreeReg_mac< 2629 0, 0b010, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2630 IIC_iMAC32, "smuadx", "\t$Rd, $Rn, $Rm", []>, 2631 Requires<[IsThumb2, HasThumb2DSP]> { 2632 let Inst{15-12} = 0b1111; 2633 } 2634 def t2SMUSD: T2ThreeReg_mac< 2635 0, 0b100, 0b0000, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2636 IIC_iMAC32, "smusd", "\t$Rd, $Rn, $Rm", []>, 2637 Requires<[IsThumb2, HasThumb2DSP]> { 2638 let Inst{15-12} = 0b1111; 2639 } 2640 def t2SMUSDX:T2ThreeReg_mac< 2641 0, 0b100, 0b0001, (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), 2642 IIC_iMAC32, "smusdx", "\t$Rd, $Rn, $Rm", []>, 2643 Requires<[IsThumb2, HasThumb2DSP]> { 2644 let Inst{15-12} = 0b1111; 2645 } 2646 def t2SMLAD : T2FourReg_mac< 2647 0, 0b010, 0b0000, (outs rGPR:$Rd), 2648 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlad", 2649 "\t$Rd, $Rn, $Rm, $Ra", []>, 2650 Requires<[IsThumb2, HasThumb2DSP]>; 2651 def t2SMLADX : T2FourReg_mac< 2652 0, 0b010, 0b0001, (outs rGPR:$Rd), 2653 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smladx", 2654 "\t$Rd, $Rn, $Rm, $Ra", []>, 2655 Requires<[IsThumb2, HasThumb2DSP]>; 2656 def t2SMLSD : T2FourReg_mac<0, 0b100, 0b0000, (outs rGPR:$Rd), 2657 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsd", 2658 "\t$Rd, $Rn, $Rm, $Ra", []>, 2659 Requires<[IsThumb2, HasThumb2DSP]>; 2660 def t2SMLSDX : T2FourReg_mac<0, 0b100, 0b0001, (outs rGPR:$Rd), 2661 (ins rGPR:$Rn, rGPR:$Rm, rGPR:$Ra), IIC_iMAC32, "smlsdx", 2662 "\t$Rd, $Rn, $Rm, $Ra", []>, 2663 Requires<[IsThumb2, HasThumb2DSP]>; 2664 def t2SMLALD : T2FourReg_mac<1, 0b100, 0b1100, (outs rGPR:$Ra,rGPR:$Rd), 2665 (ins rGPR:$Rn, rGPR:$Rm), IIC_iMAC64, "smlald", 2666 "\t$Ra, $Rd, $Rn, $Rm", []>, 2667 Requires<[IsThumb2, HasThumb2DSP]>; 2668 def t2SMLALDX : T2FourReg_mac<1, 0b100, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), 2669 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlaldx", 2670 "\t$Ra, $Rd, $Rn, $Rm", []>, 2671 Requires<[IsThumb2, HasThumb2DSP]>; 2672 def t2SMLSLD : T2FourReg_mac<1, 0b101, 0b1100, (outs rGPR:$Ra,rGPR:$Rd), 2673 (ins rGPR:$Rn,rGPR:$Rm), IIC_iMAC64, "smlsld", 2674 "\t$Ra, $Rd, $Rn, $Rm", []>, 2675 Requires<[IsThumb2, HasThumb2DSP]>; 2676 def t2SMLSLDX : T2FourReg_mac<1, 0b101, 0b1101, (outs rGPR:$Ra,rGPR:$Rd), 2677 (ins rGPR:$Rm,rGPR:$Rn), IIC_iMAC64, "smlsldx", 2678 "\t$Ra, $Rd, $Rn, $Rm", []>, 2679 Requires<[IsThumb2, HasThumb2DSP]>; 2680 2681 //===----------------------------------------------------------------------===// 2682 // Division Instructions. 2683 // Signed and unsigned division on v7-M 2684 // 2685 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, 2686 "sdiv", "\t$Rd, $Rn, $Rm", 2687 [(set rGPR:$Rd, (sdiv rGPR:$Rn, rGPR:$Rm))]>, 2688 Requires<[HasDivide, IsThumb2]> { 2689 let Inst{31-27} = 0b11111; 2690 let Inst{26-21} = 0b011100; 2691 let Inst{20} = 0b1; 2692 let Inst{15-12} = 0b1111; 2693 let Inst{7-4} = 0b1111; 2694 } 2695 2696 def t2UDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi, 2697 "udiv", "\t$Rd, $Rn, $Rm", 2698 [(set rGPR:$Rd, (udiv rGPR:$Rn, rGPR:$Rm))]>, 2699 Requires<[HasDivide, IsThumb2]> { 2700 let Inst{31-27} = 0b11111; 2701 let Inst{26-21} = 0b011101; 2702 let Inst{20} = 0b1; 2703 let Inst{15-12} = 0b1111; 2704 let Inst{7-4} = 0b1111; 2705 } 2706 2707 //===----------------------------------------------------------------------===// 2708 // Misc. Arithmetic Instructions. 2709 // 2710 2711 class T2I_misc<bits<2> op1, bits<2> op2, dag oops, dag iops, 2712 InstrItinClass itin, string opc, string asm, list<dag> pattern> 2713 : T2ThreeReg<oops, iops, itin, opc, asm, pattern> { 2714 let Inst{31-27} = 0b11111; 2715 let Inst{26-22} = 0b01010; 2716 let Inst{21-20} = op1; 2717 let Inst{15-12} = 0b1111; 2718 let Inst{7-6} = 0b10; 2719 let Inst{5-4} = op2; 2720 let Rn{3-0} = Rm; 2721 } 2722 2723 def t2CLZ : T2I_misc<0b11, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2724 "clz", "\t$Rd, $Rm", [(set rGPR:$Rd, (ctlz rGPR:$Rm))]>; 2725 2726 def t2RBIT : T2I_misc<0b01, 0b10, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2727 "rbit", "\t$Rd, $Rm", 2728 [(set rGPR:$Rd, (ARMrbit rGPR:$Rm))]>; 2729 2730 def t2REV : T2I_misc<0b01, 0b00, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2731 "rev", ".w\t$Rd, $Rm", [(set rGPR:$Rd, (bswap rGPR:$Rm))]>; 2732 2733 def t2REV16 : T2I_misc<0b01, 0b01, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2734 "rev16", ".w\t$Rd, $Rm", 2735 [(set rGPR:$Rd, (rotr (bswap rGPR:$Rm), (i32 16)))]>; 2736 2737 def t2REVSH : T2I_misc<0b01, 0b11, (outs rGPR:$Rd), (ins rGPR:$Rm), IIC_iUNAr, 2738 "revsh", ".w\t$Rd, $Rm", 2739 [(set rGPR:$Rd, (sra (bswap rGPR:$Rm), (i32 16)))]>; 2740 2741 def : T2Pat<(or (sra (shl rGPR:$Rm, (i32 24)), (i32 16)), 2742 (and (srl rGPR:$Rm, (i32 8)), 0xFF)), 2743 (t2REVSH rGPR:$Rm)>; 2744 2745 def t2PKHBT : T2ThreeReg< 2746 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_lsl_amt:$sh), 2747 IIC_iBITsi, "pkhbt", "\t$Rd, $Rn, $Rm$sh", 2748 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF), 2749 (and (shl rGPR:$Rm, pkh_lsl_amt:$sh), 2750 0xFFFF0000)))]>, 2751 Requires<[HasT2ExtractPack, IsThumb2]> { 2752 let Inst{31-27} = 0b11101; 2753 let Inst{26-25} = 0b01; 2754 let Inst{24-20} = 0b01100; 2755 let Inst{5} = 0; // BT form 2756 let Inst{4} = 0; 2757 2758 bits<5> sh; 2759 let Inst{14-12} = sh{4-2}; 2760 let Inst{7-6} = sh{1-0}; 2761 } 2762 2763 // Alternate cases for PKHBT where identities eliminate some nodes. 2764 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)), 2765 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>, 2766 Requires<[HasT2ExtractPack, IsThumb2]>; 2767 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)), 2768 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 2769 Requires<[HasT2ExtractPack, IsThumb2]>; 2770 2771 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and 2772 // will match the pattern below. 2773 def t2PKHTB : T2ThreeReg< 2774 (outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm, pkh_asr_amt:$sh), 2775 IIC_iBITsi, "pkhtb", "\t$Rd, $Rn, $Rm$sh", 2776 [(set rGPR:$Rd, (or (and rGPR:$Rn, 0xFFFF0000), 2777 (and (sra rGPR:$Rm, pkh_asr_amt:$sh), 2778 0xFFFF)))]>, 2779 Requires<[HasT2ExtractPack, IsThumb2]> { 2780 let Inst{31-27} = 0b11101; 2781 let Inst{26-25} = 0b01; 2782 let Inst{24-20} = 0b01100; 2783 let Inst{5} = 1; // TB form 2784 let Inst{4} = 0; 2785 2786 bits<5> sh; 2787 let Inst{14-12} = sh{4-2}; 2788 let Inst{7-6} = sh{1-0}; 2789 } 2790 2791 // Alternate cases for PKHTB where identities eliminate some nodes. Note that 2792 // a shift amount of 0 is *not legal* here, it is PKHBT instead. 2793 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)), 2794 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>, 2795 Requires<[HasT2ExtractPack, IsThumb2]>; 2796 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), 2797 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)), 2798 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$sh)>, 2799 Requires<[HasT2ExtractPack, IsThumb2]>; 2800 2801 //===----------------------------------------------------------------------===// 2802 // Comparison Instructions... 2803 // 2804 defm t2CMP : T2I_cmp_irs<0b1101, "cmp", 2805 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 2806 BinOpFrag<(ARMcmp node:$LHS, node:$RHS)>, "t2CMP">; 2807 2808 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_imm:$imm), 2809 (t2CMPri GPRnopc:$lhs, t2_so_imm:$imm)>; 2810 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, rGPR:$rhs), 2811 (t2CMPrr GPRnopc:$lhs, rGPR:$rhs)>; 2812 def : T2Pat<(ARMcmpZ GPRnopc:$lhs, t2_so_reg:$rhs), 2813 (t2CMPrs GPRnopc:$lhs, t2_so_reg:$rhs)>; 2814 2815 //FIXME: Disable CMN, as CCodes are backwards from compare expectations 2816 // Compare-to-zero still works out, just not the relationals 2817 //defm t2CMN : T2I_cmp_irs<0b1000, "cmn", 2818 // BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; 2819 defm t2CMNz : T2I_cmp_irs<0b1000, "cmn", 2820 IIC_iCMPi, IIC_iCMPr, IIC_iCMPsi, 2821 BinOpFrag<(ARMcmpZ node:$LHS,(ineg node:$RHS))>, 2822 "t2CMNz">; 2823 2824 //def : T2Pat<(ARMcmp GPR:$src, t2_so_imm_neg:$imm), 2825 // (t2CMNri GPR:$src, t2_so_imm_neg:$imm)>; 2826 2827 def : T2Pat<(ARMcmpZ GPRnopc:$src, t2_so_imm_neg:$imm), 2828 (t2CMNzri GPRnopc:$src, t2_so_imm_neg:$imm)>; 2829 2830 defm t2TST : T2I_cmp_irs<0b0000, "tst", 2831 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 2832 BinOpFrag<(ARMcmpZ (and_su node:$LHS, node:$RHS), 0)>, 2833 "t2TST">; 2834 defm t2TEQ : T2I_cmp_irs<0b0100, "teq", 2835 IIC_iTSTi, IIC_iTSTr, IIC_iTSTsi, 2836 BinOpFrag<(ARMcmpZ (xor_su node:$LHS, node:$RHS), 0)>, 2837 "t2TEQ">; 2838 2839 // Conditional moves 2840 // FIXME: should be able to write a pattern for ARMcmov, but can't use 2841 // a two-value operand where a dag node expects two operands. :( 2842 let neverHasSideEffects = 1 in { 2843 def t2MOVCCr : t2PseudoInst<(outs rGPR:$Rd), 2844 (ins rGPR:$false, rGPR:$Rm, pred:$p), 2845 4, IIC_iCMOVr, 2846 [/*(set rGPR:$Rd, (ARMcmov rGPR:$false, rGPR:$Rm, imm:$cc, CCR:$ccr))*/]>, 2847 RegConstraint<"$false = $Rd">; 2848 2849 let isMoveImm = 1 in 2850 def t2MOVCCi : t2PseudoInst<(outs rGPR:$Rd), 2851 (ins rGPR:$false, t2_so_imm:$imm, pred:$p), 2852 4, IIC_iCMOVi, 2853 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm:$imm, imm:$cc, CCR:$ccr))*/]>, 2854 RegConstraint<"$false = $Rd">; 2855 2856 // FIXME: Pseudo-ize these. For now, just mark codegen only. 2857 let isCodeGenOnly = 1 in { 2858 let isMoveImm = 1 in 2859 def t2MOVCCi16 : T2I<(outs rGPR:$Rd), (ins rGPR:$false, imm0_65535_expr:$imm), 2860 IIC_iCMOVi, 2861 "movw", "\t$Rd, $imm", []>, 2862 RegConstraint<"$false = $Rd"> { 2863 let Inst{31-27} = 0b11110; 2864 let Inst{25} = 1; 2865 let Inst{24-21} = 0b0010; 2866 let Inst{20} = 0; // The S bit. 2867 let Inst{15} = 0; 2868 2869 bits<4> Rd; 2870 bits<16> imm; 2871 2872 let Inst{11-8} = Rd; 2873 let Inst{19-16} = imm{15-12}; 2874 let Inst{26} = imm{11}; 2875 let Inst{14-12} = imm{10-8}; 2876 let Inst{7-0} = imm{7-0}; 2877 } 2878 2879 let isMoveImm = 1 in 2880 def t2MOVCCi32imm : PseudoInst<(outs rGPR:$dst), 2881 (ins rGPR:$false, i32imm:$src, pred:$p), 2882 IIC_iCMOVix2, []>, RegConstraint<"$false = $dst">; 2883 2884 let isMoveImm = 1 in 2885 def t2MVNCCi : T2OneRegImm<(outs rGPR:$Rd), (ins rGPR:$false, t2_so_imm:$imm), 2886 IIC_iCMOVi, "mvn", ".w\t$Rd, $imm", 2887 [/*(set rGPR:$Rd,(ARMcmov rGPR:$false,t2_so_imm_not:$imm, 2888 imm:$cc, CCR:$ccr))*/]>, 2889 RegConstraint<"$false = $Rd"> { 2890 let Inst{31-27} = 0b11110; 2891 let Inst{25} = 0; 2892 let Inst{24-21} = 0b0011; 2893 let Inst{20} = 0; // The S bit. 2894 let Inst{19-16} = 0b1111; // Rn 2895 let Inst{15} = 0; 2896 } 2897 2898 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin, 2899 string opc, string asm, list<dag> pattern> 2900 : T2TwoRegShiftImm<oops, iops, itin, opc, asm, pattern> { 2901 let Inst{31-27} = 0b11101; 2902 let Inst{26-25} = 0b01; 2903 let Inst{24-21} = 0b0010; 2904 let Inst{20} = 0; // The S bit. 2905 let Inst{19-16} = 0b1111; // Rn 2906 let Inst{5-4} = opcod; // Shift type. 2907 } 2908 def t2MOVCClsl : T2I_movcc_sh<0b00, (outs rGPR:$Rd), 2909 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2910 IIC_iCMOVsi, "lsl", ".w\t$Rd, $Rm, $imm", []>, 2911 RegConstraint<"$false = $Rd">; 2912 def t2MOVCClsr : T2I_movcc_sh<0b01, (outs rGPR:$Rd), 2913 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2914 IIC_iCMOVsi, "lsr", ".w\t$Rd, $Rm, $imm", []>, 2915 RegConstraint<"$false = $Rd">; 2916 def t2MOVCCasr : T2I_movcc_sh<0b10, (outs rGPR:$Rd), 2917 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2918 IIC_iCMOVsi, "asr", ".w\t$Rd, $Rm, $imm", []>, 2919 RegConstraint<"$false = $Rd">; 2920 def t2MOVCCror : T2I_movcc_sh<0b11, (outs rGPR:$Rd), 2921 (ins rGPR:$false, rGPR:$Rm, i32imm:$imm), 2922 IIC_iCMOVsi, "ror", ".w\t$Rd, $Rm, $imm", []>, 2923 RegConstraint<"$false = $Rd">; 2924 } // isCodeGenOnly = 1 2925 } // neverHasSideEffects 2926 2927 //===----------------------------------------------------------------------===// 2928 // Atomic operations intrinsics 2929 // 2930 2931 // memory barriers protect the atomic sequences 2932 let hasSideEffects = 1 in { 2933 def t2DMB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 2934 "dmb", "\t$opt", [(ARMMemBarrier (i32 imm:$opt))]>, 2935 Requires<[IsThumb, HasDB]> { 2936 bits<4> opt; 2937 let Inst{31-4} = 0xf3bf8f5; 2938 let Inst{3-0} = opt; 2939 } 2940 } 2941 2942 def t2DSB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 2943 "dsb", "\t$opt", []>, 2944 Requires<[IsThumb, HasDB]> { 2945 bits<4> opt; 2946 let Inst{31-4} = 0xf3bf8f4; 2947 let Inst{3-0} = opt; 2948 } 2949 2950 def t2ISB : AInoP<(outs), (ins memb_opt:$opt), ThumbFrm, NoItinerary, 2951 "isb", "\t$opt", 2952 []>, Requires<[IsThumb2, HasDB]> { 2953 bits<4> opt; 2954 let Inst{31-4} = 0xf3bf8f6; 2955 let Inst{3-0} = opt; 2956 } 2957 2958 class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, 2959 InstrItinClass itin, string opc, string asm, string cstr, 2960 list<dag> pattern, bits<4> rt2 = 0b1111> 2961 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2962 let Inst{31-27} = 0b11101; 2963 let Inst{26-20} = 0b0001101; 2964 let Inst{11-8} = rt2; 2965 let Inst{7-6} = 0b01; 2966 let Inst{5-4} = opcod; 2967 let Inst{3-0} = 0b1111; 2968 2969 bits<4> addr; 2970 bits<4> Rt; 2971 let Inst{19-16} = addr; 2972 let Inst{15-12} = Rt; 2973 } 2974 class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, int sz, 2975 InstrItinClass itin, string opc, string asm, string cstr, 2976 list<dag> pattern, bits<4> rt2 = 0b1111> 2977 : Thumb2I<oops, iops, am, sz, itin, opc, asm, cstr, pattern> { 2978 let Inst{31-27} = 0b11101; 2979 let Inst{26-20} = 0b0001100; 2980 let Inst{11-8} = rt2; 2981 let Inst{7-6} = 0b01; 2982 let Inst{5-4} = opcod; 2983 2984 bits<4> Rd; 2985 bits<4> addr; 2986 bits<4> Rt; 2987 let Inst{3-0} = Rd; 2988 let Inst{19-16} = addr; 2989 let Inst{15-12} = Rt; 2990 } 2991 2992 let mayLoad = 1 in { 2993 def t2LDREXB : T2I_ldrex<0b00, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 2994 AddrModeNone, 4, NoItinerary, 2995 "ldrexb", "\t$Rt, $addr", "", []>; 2996 def t2LDREXH : T2I_ldrex<0b01, (outs rGPR:$Rt), (ins addr_offset_none:$addr), 2997 AddrModeNone, 4, NoItinerary, 2998 "ldrexh", "\t$Rt, $addr", "", []>; 2999 def t2LDREX : Thumb2I<(outs rGPR:$Rt), (ins t2addrmode_imm0_1020s4:$addr), 3000 AddrModeNone, 4, NoItinerary, 3001 "ldrex", "\t$Rt, $addr", "", []> { 3002 bits<4> Rt; 3003 bits<12> addr; 3004 let Inst{31-27} = 0b11101; 3005 let Inst{26-20} = 0b0000101; 3006 let Inst{19-16} = addr{11-8}; 3007 let Inst{15-12} = Rt; 3008 let Inst{11-8} = 0b1111; 3009 let Inst{7-0} = addr{7-0}; 3010 } 3011 let hasExtraDefRegAllocReq = 1 in 3012 def t2LDREXD : T2I_ldrex<0b11, (outs rGPR:$Rt, rGPR:$Rt2), 3013 (ins addr_offset_none:$addr), 3014 AddrModeNone, 4, NoItinerary, 3015 "ldrexd", "\t$Rt, $Rt2, $addr", "", 3016 [], {?, ?, ?, ?}> { 3017 bits<4> Rt2; 3018 let Inst{11-8} = Rt2; 3019 } 3020 } 3021 3022 let mayStore = 1, Constraints = "@earlyclobber $Rd" in { 3023 def t2STREXB : T2I_strex<0b00, (outs rGPR:$Rd), 3024 (ins rGPR:$Rt, addr_offset_none:$addr), 3025 AddrModeNone, 4, NoItinerary, 3026 "strexb", "\t$Rd, $Rt, $addr", "", []>; 3027 def t2STREXH : T2I_strex<0b01, (outs rGPR:$Rd), 3028 (ins rGPR:$Rt, addr_offset_none:$addr), 3029 AddrModeNone, 4, NoItinerary, 3030 "strexh", "\t$Rd, $Rt, $addr", "", []>; 3031 def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt, 3032 t2addrmode_imm0_1020s4:$addr), 3033 AddrModeNone, 4, NoItinerary, 3034 "strex", "\t$Rd, $Rt, $addr", "", 3035 []> { 3036 bits<4> Rd; 3037 bits<4> Rt; 3038 bits<12> addr; 3039 let Inst{31-27} = 0b11101; 3040 let Inst{26-20} = 0b0000100; 3041 let Inst{19-16} = addr{11-8}; 3042 let Inst{15-12} = Rt; 3043 let Inst{11-8} = Rd; 3044 let Inst{7-0} = addr{7-0}; 3045 } 3046 } 3047 3048 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in 3049 def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd), 3050 (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), 3051 AddrModeNone, 4, NoItinerary, 3052 "strexd", "\t$Rd, $Rt, $Rt2, $addr", "", [], 3053 {?, ?, ?, ?}> { 3054 bits<4> Rt2; 3055 let Inst{11-8} = Rt2; 3056 } 3057 3058 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>, 3059 Requires<[IsThumb2, HasV7]> { 3060 let Inst{31-16} = 0xf3bf; 3061 let Inst{15-14} = 0b10; 3062 let Inst{13} = 0; 3063 let Inst{12} = 0; 3064 let Inst{11-8} = 0b1111; 3065 let Inst{7-4} = 0b0010; 3066 let Inst{3-0} = 0b1111; 3067 } 3068 3069 //===----------------------------------------------------------------------===// 3070 // SJLJ Exception handling intrinsics 3071 // eh_sjlj_setjmp() is an instruction sequence to store the return 3072 // address and save #0 in R0 for the non-longjmp case. 3073 // Since by its nature we may be coming from some other function to get 3074 // here, and we're using the stack frame for the containing function to 3075 // save/restore registers, we can't keep anything live in regs across 3076 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 3077 // when we get here from a longjmp(). We force everything out of registers 3078 // except for our own input by listing the relevant registers in Defs. By 3079 // doing so, we also cause the prologue/epilogue code to actively preserve 3080 // all of the callee-saved resgisters, which is exactly what we want. 3081 // $val is a scratch register for our use. 3082 let Defs = 3083 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR, 3084 QQQQ0, QQQQ1, QQQQ2, QQQQ3 ], 3085 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { 3086 def t2Int_eh_sjlj_setjmp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3087 AddrModeNone, 0, NoItinerary, "", "", 3088 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3089 Requires<[IsThumb2, HasVFP2]>; 3090 } 3091 3092 let Defs = 3093 [ R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, LR, CPSR ], 3094 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in { 3095 def t2Int_eh_sjlj_setjmp_nofp : Thumb2XI<(outs), (ins tGPR:$src, tGPR:$val), 3096 AddrModeNone, 0, NoItinerary, "", "", 3097 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>, 3098 Requires<[IsThumb2, NoVFP]>; 3099 } 3100 3101 3102 //===----------------------------------------------------------------------===// 3103 // Control-Flow Instructions 3104 // 3105 3106 // FIXME: remove when we have a way to marking a MI with these properties. 3107 // FIXME: Should pc be an implicit operand like PICADD, etc? 3108 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 3109 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in 3110 def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, 3111 reglist:$regs, variable_ops), 3112 4, IIC_iLoad_mBr, [], 3113 (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>, 3114 RegConstraint<"$Rn = $wb">; 3115 3116 let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 3117 let isPredicable = 1 in 3118 def t2B : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br, 3119 "b", ".w\t$target", 3120 [(br bb:$target)]> { 3121 let Inst{31-27} = 0b11110; 3122 let Inst{15-14} = 0b10; 3123 let Inst{12} = 1; 3124 3125 bits<20> target; 3126 let Inst{26} = target{19}; 3127 let Inst{11} = target{18}; 3128 let Inst{13} = target{17}; 3129 let Inst{21-16} = target{16-11}; 3130 let Inst{10-0} = target{10-0}; 3131 } 3132 3133 let isNotDuplicable = 1, isIndirectBranch = 1 in { 3134 def t2BR_JT : t2PseudoInst<(outs), 3135 (ins GPR:$target, GPR:$index, i32imm:$jt, i32imm:$id), 3136 0, IIC_Br, 3137 [(ARMbr2jt GPR:$target, GPR:$index, tjumptable:$jt, imm:$id)]>; 3138 3139 // FIXME: Add a non-pc based case that can be predicated. 3140 def t2TBB_JT : t2PseudoInst<(outs), 3141 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>; 3142 3143 def t2TBH_JT : t2PseudoInst<(outs), 3144 (ins GPR:$index, i32imm:$jt, i32imm:$id), 0, IIC_Br, []>; 3145 3146 def t2TBB : T2I<(outs), (ins addrmode_tbb:$addr), IIC_Br, 3147 "tbb", "\t$addr", []> { 3148 bits<4> Rn; 3149 bits<4> Rm; 3150 let Inst{31-20} = 0b111010001101; 3151 let Inst{19-16} = Rn; 3152 let Inst{15-5} = 0b11110000000; 3153 let Inst{4} = 0; // B form 3154 let Inst{3-0} = Rm; 3155 3156 let DecoderMethod = "DecodeThumbTableBranch"; 3157 } 3158 3159 def t2TBH : T2I<(outs), (ins addrmode_tbh:$addr), IIC_Br, 3160 "tbh", "\t$addr", []> { 3161 bits<4> Rn; 3162 bits<4> Rm; 3163 let Inst{31-20} = 0b111010001101; 3164 let Inst{19-16} = Rn; 3165 let Inst{15-5} = 0b11110000000; 3166 let Inst{4} = 1; // H form 3167 let Inst{3-0} = Rm; 3168 3169 let DecoderMethod = "DecodeThumbTableBranch"; 3170 } 3171 } // isNotDuplicable, isIndirectBranch 3172 3173 } // isBranch, isTerminator, isBarrier 3174 3175 // FIXME: should be able to write a pattern for ARMBrcond, but can't use 3176 // a two-value operand where a dag node expects ", "two operands. :( 3177 let isBranch = 1, isTerminator = 1 in 3178 def t2Bcc : T2I<(outs), (ins brtarget:$target), IIC_Br, 3179 "b", ".w\t$target", 3180 [/*(ARMbrcond bb:$target, imm:$cc)*/]> { 3181 let Inst{31-27} = 0b11110; 3182 let Inst{15-14} = 0b10; 3183 let Inst{12} = 0; 3184 3185 bits<4> p; 3186 let Inst{25-22} = p; 3187 3188 bits<21> target; 3189 let Inst{26} = target{20}; 3190 let Inst{11} = target{19}; 3191 let Inst{13} = target{18}; 3192 let Inst{21-16} = target{17-12}; 3193 let Inst{10-0} = target{11-1}; 3194 3195 let DecoderMethod = "DecodeThumb2BCCInstruction"; 3196 } 3197 3198 // Tail calls. The Darwin version of thumb tail calls uses a t2 branch, so 3199 // it goes here. 3200 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 3201 // Darwin version. 3202 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC], 3203 Uses = [SP] in 3204 def tTAILJMPd: tPseudoExpand<(outs), 3205 (ins uncondbrtarget:$dst, pred:$p, variable_ops), 3206 4, IIC_Br, [], 3207 (t2B uncondbrtarget:$dst, pred:$p)>, 3208 Requires<[IsThumb2, IsDarwin]>; 3209 } 3210 3211 // IT block 3212 let Defs = [ITSTATE] in 3213 def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask), 3214 AddrModeNone, 2, IIC_iALUx, 3215 "it$mask\t$cc", "", []> { 3216 // 16-bit instruction. 3217 let Inst{31-16} = 0x0000; 3218 let Inst{15-8} = 0b10111111; 3219 3220 bits<4> cc; 3221 bits<4> mask; 3222 let Inst{7-4} = cc; 3223 let Inst{3-0} = mask; 3224 3225 let DecoderMethod = "DecodeIT"; 3226 } 3227 3228 // Branch and Exchange Jazelle -- for disassembly only 3229 // Rm = Inst{19-16} 3230 def t2BXJ : T2I<(outs), (ins rGPR:$func), NoItinerary, "bxj", "\t$func", []> { 3231 bits<4> func; 3232 let Inst{31-27} = 0b11110; 3233 let Inst{26} = 0; 3234 let Inst{25-20} = 0b111100; 3235 let Inst{19-16} = func; 3236 let Inst{15-0} = 0b1000111100000000; 3237 } 3238 3239 // Compare and branch on zero / non-zero 3240 let isBranch = 1, isTerminator = 1 in { 3241 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 3242 "cbz\t$Rn, $target", []>, 3243 T1Misc<{0,0,?,1,?,?,?}>, 3244 Requires<[IsThumb2]> { 3245 // A8.6.27 3246 bits<6> target; 3247 bits<3> Rn; 3248 let Inst{9} = target{5}; 3249 let Inst{7-3} = target{4-0}; 3250 let Inst{2-0} = Rn; 3251 } 3252 3253 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 3254 "cbnz\t$Rn, $target", []>, 3255 T1Misc<{1,0,?,1,?,?,?}>, 3256 Requires<[IsThumb2]> { 3257 // A8.6.27 3258 bits<6> target; 3259 bits<3> Rn; 3260 let Inst{9} = target{5}; 3261 let Inst{7-3} = target{4-0}; 3262 let Inst{2-0} = Rn; 3263 } 3264 } 3265 3266 3267 // Change Processor State is a system instruction. 3268 // FIXME: Since the asm parser has currently no clean way to handle optional 3269 // operands, create 3 versions of the same instruction. Once there's a clean 3270 // framework to represent optional operands, change this behavior. 3271 class t2CPS<dag iops, string asm_op> : T2XI<(outs), iops, NoItinerary, 3272 !strconcat("cps", asm_op), []> { 3273 bits<2> imod; 3274 bits<3> iflags; 3275 bits<5> mode; 3276 bit M; 3277 3278 let Inst{31-27} = 0b11110; 3279 let Inst{26} = 0; 3280 let Inst{25-20} = 0b111010; 3281 let Inst{19-16} = 0b1111; 3282 let Inst{15-14} = 0b10; 3283 let Inst{12} = 0; 3284 let Inst{10-9} = imod; 3285 let Inst{8} = M; 3286 let Inst{7-5} = iflags; 3287 let Inst{4-0} = mode; 3288 let DecoderMethod = "DecodeT2CPSInstruction"; 3289 } 3290 3291 let M = 1 in 3292 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode), 3293 "$imod.w\t$iflags, $mode">; 3294 let mode = 0, M = 0 in 3295 def t2CPS2p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags), 3296 "$imod.w\t$iflags">; 3297 let imod = 0, iflags = 0, M = 1 in 3298 def t2CPS1p : t2CPS<(ins imm0_31:$mode), "\t$mode">; 3299 3300 // A6.3.4 Branches and miscellaneous control 3301 // Table A6-14 Change Processor State, and hint instructions 3302 class T2I_hint<bits<8> op7_0, string opc, string asm> 3303 : T2I<(outs), (ins), NoItinerary, opc, asm, []> { 3304 let Inst{31-20} = 0xf3a; 3305 let Inst{19-16} = 0b1111; 3306 let Inst{15-14} = 0b10; 3307 let Inst{12} = 0; 3308 let Inst{10-8} = 0b000; 3309 let Inst{7-0} = op7_0; 3310 } 3311 3312 def t2NOP : T2I_hint<0b00000000, "nop", ".w">; 3313 def t2YIELD : T2I_hint<0b00000001, "yield", ".w">; 3314 def t2WFE : T2I_hint<0b00000010, "wfe", ".w">; 3315 def t2WFI : T2I_hint<0b00000011, "wfi", ".w">; 3316 def t2SEV : T2I_hint<0b00000100, "sev", ".w">; 3317 3318 def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> { 3319 bits<4> opt; 3320 let Inst{31-20} = 0b111100111010; 3321 let Inst{19-16} = 0b1111; 3322 let Inst{15-8} = 0b10000000; 3323 let Inst{7-4} = 0b1111; 3324 let Inst{3-0} = opt; 3325 } 3326 3327 // Secure Monitor Call is a system instruction. 3328 // Option = Inst{19-16} 3329 def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt", []> { 3330 let Inst{31-27} = 0b11110; 3331 let Inst{26-20} = 0b1111111; 3332 let Inst{15-12} = 0b1000; 3333 3334 bits<4> opt; 3335 let Inst{19-16} = opt; 3336 } 3337 3338 class T2SRS<bits<2> Op, bit W, dag oops, dag iops, InstrItinClass itin, 3339 string opc, string asm, list<dag> pattern> 3340 : T2I<oops, iops, itin, opc, asm, pattern> { 3341 bits<5> mode; 3342 let Inst{31-25} = 0b1110100; 3343 let Inst{24-23} = Op; 3344 let Inst{22} = 0; 3345 let Inst{21} = W; 3346 let Inst{20-16} = 0b01101; 3347 let Inst{15-5} = 0b11000000000; 3348 let Inst{4-0} = mode{4-0}; 3349 } 3350 3351 // Store Return State is a system instruction. 3352 def t2SRSDB_UPD : T2SRS<0b00, 1, (outs), (ins imm0_31:$mode), NoItinerary, 3353 "srsdb", "\tsp!, $mode", []>; 3354 def t2SRSDB : T2SRS<0b00, 0, (outs), (ins imm0_31:$mode), NoItinerary, 3355 "srsdb","\tsp, $mode", []>; 3356 def t2SRSIA_UPD : T2SRS<0b11, 1, (outs), (ins imm0_31:$mode), NoItinerary, 3357 "srsia","\tsp!, $mode", []>; 3358 def t2SRSIA : T2SRS<0b11, 0, (outs), (ins imm0_31:$mode), NoItinerary, 3359 "srsia","\tsp, $mode", []>; 3360 3361 // Return From Exception is a system instruction. 3362 class T2RFE<bits<12> op31_20, dag oops, dag iops, InstrItinClass itin, 3363 string opc, string asm, list<dag> pattern> 3364 : T2I<oops, iops, itin, opc, asm, pattern> { 3365 let Inst{31-20} = op31_20{11-0}; 3366 3367 bits<4> Rn; 3368 let Inst{19-16} = Rn; 3369 let Inst{15-0} = 0xc000; 3370 } 3371 3372 def t2RFEDBW : T2RFE<0b111010000011, 3373 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn!", 3374 [/* For disassembly only; pattern left blank */]>; 3375 def t2RFEDB : T2RFE<0b111010000001, 3376 (outs), (ins GPR:$Rn), NoItinerary, "rfedb", "\t$Rn", 3377 [/* For disassembly only; pattern left blank */]>; 3378 def t2RFEIAW : T2RFE<0b111010011011, 3379 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn!", 3380 [/* For disassembly only; pattern left blank */]>; 3381 def t2RFEIA : T2RFE<0b111010011001, 3382 (outs), (ins GPR:$Rn), NoItinerary, "rfeia", "\t$Rn", 3383 [/* For disassembly only; pattern left blank */]>; 3384 3385 //===----------------------------------------------------------------------===// 3386 // Non-Instruction Patterns 3387 // 3388 3389 // 32-bit immediate using movw + movt. 3390 // This is a single pseudo instruction to make it re-materializable. 3391 // FIXME: Remove this when we can do generalized remat. 3392 let isReMaterializable = 1, isMoveImm = 1 in 3393 def t2MOVi32imm : PseudoInst<(outs rGPR:$dst), (ins i32imm:$src), IIC_iMOVix2, 3394 [(set rGPR:$dst, (i32 imm:$src))]>, 3395 Requires<[IsThumb, HasV6T2]>; 3396 3397 // Pseudo instruction that combines movw + movt + add pc (if pic). 3398 // It also makes it possible to rematerialize the instructions. 3399 // FIXME: Remove this when we can do generalized remat and when machine licm 3400 // can properly the instructions. 3401 let isReMaterializable = 1 in { 3402 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 3403 IIC_iMOVix2addpc, 3404 [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>, 3405 Requires<[IsThumb2, UseMovt]>; 3406 3407 def t2MOV_ga_dyn : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr), 3408 IIC_iMOVix2, 3409 [(set rGPR:$dst, (ARMWrapperDYN tglobaladdr:$addr))]>, 3410 Requires<[IsThumb2, UseMovt]>; 3411 } 3412 3413 // ConstantPool, GlobalAddress, and JumpTable 3414 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2LEApcrel tglobaladdr :$dst)>, 3415 Requires<[IsThumb2, DontUseMovt]>; 3416 def : T2Pat<(ARMWrapper tconstpool :$dst), (t2LEApcrel tconstpool :$dst)>; 3417 def : T2Pat<(ARMWrapper tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>, 3418 Requires<[IsThumb2, UseMovt]>; 3419 3420 def : T2Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 3421 (t2LEApcrelJT tjumptable:$dst, imm:$id)>; 3422 3423 // Pseudo instruction that combines ldr from constpool and add pc. This should 3424 // be expanded into two instructions late to allow if-conversion and 3425 // scheduling. 3426 let canFoldAsLoad = 1, isReMaterializable = 1 in 3427 def t2LDRpci_pic : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr, pclabel:$cp), 3428 IIC_iLoadiALU, 3429 [(set rGPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 3430 imm:$cp))]>, 3431 Requires<[IsThumb2]>; 3432 3433 // Pseudo isntruction that combines movs + predicated rsbmi 3434 // to implement integer ABS 3435 let usesCustomInserter = 1, Defs = [CPSR] in { 3436 def t2ABS : PseudoInst<(outs rGPR:$dst), (ins rGPR:$src), 3437 NoItinerary, []>, Requires<[IsThumb2]>; 3438 } 3439 3440 //===----------------------------------------------------------------------===// 3441 // Coprocessor load/store -- for disassembly only 3442 // 3443 class T2CI<bits<4> op31_28, dag oops, dag iops, string opc, string asm> 3444 : T2I<oops, iops, NoItinerary, opc, asm, []> { 3445 let Inst{31-28} = op31_28; 3446 let Inst{27-25} = 0b110; 3447 } 3448 3449 multiclass t2LdStCop<bits<4> op31_28, bit load, bit Dbit, string asm> { 3450 def _OFFSET : T2CI<op31_28, 3451 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3452 asm, "\t$cop, $CRd, $addr"> { 3453 bits<13> addr; 3454 bits<4> cop; 3455 bits<4> CRd; 3456 let Inst{24} = 1; // P = 1 3457 let Inst{23} = addr{8}; 3458 let Inst{22} = Dbit; 3459 let Inst{21} = 0; // W = 0 3460 let Inst{20} = load; 3461 let Inst{19-16} = addr{12-9}; 3462 let Inst{15-12} = CRd; 3463 let Inst{11-8} = cop; 3464 let Inst{7-0} = addr{7-0}; 3465 let DecoderMethod = "DecodeCopMemInstruction"; 3466 } 3467 def _PRE : T2CI<op31_28, 3468 (outs), (ins p_imm:$cop, c_imm:$CRd, addrmode5:$addr), 3469 asm, "\t$cop, $CRd, $addr!"> { 3470 bits<13> addr; 3471 bits<4> cop; 3472 bits<4> CRd; 3473 let Inst{24} = 1; // P = 1 3474 let Inst{23} = addr{8}; 3475 let Inst{22} = Dbit; 3476 let Inst{21} = 1; // W = 1 3477 let Inst{20} = load; 3478 let Inst{19-16} = addr{12-9}; 3479 let Inst{15-12} = CRd; 3480 let Inst{11-8} = cop; 3481 let Inst{7-0} = addr{7-0}; 3482 let DecoderMethod = "DecodeCopMemInstruction"; 3483 } 3484 def _POST: T2CI<op31_28, 3485 (outs), (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3486 postidx_imm8s4:$offset), 3487 asm, "\t$cop, $CRd, $addr, $offset"> { 3488 bits<9> offset; 3489 bits<4> addr; 3490 bits<4> cop; 3491 bits<4> CRd; 3492 let Inst{24} = 0; // P = 0 3493 let Inst{23} = offset{8}; 3494 let Inst{22} = Dbit; 3495 let Inst{21} = 1; // W = 1 3496 let Inst{20} = load; 3497 let Inst{19-16} = addr; 3498 let Inst{15-12} = CRd; 3499 let Inst{11-8} = cop; 3500 let Inst{7-0} = offset{7-0}; 3501 let DecoderMethod = "DecodeCopMemInstruction"; 3502 } 3503 def _OPTION : T2CI<op31_28, (outs), 3504 (ins p_imm:$cop, c_imm:$CRd, addr_offset_none:$addr, 3505 coproc_option_imm:$option), 3506 asm, "\t$cop, $CRd, $addr, $option"> { 3507 bits<8> option; 3508 bits<4> addr; 3509 bits<4> cop; 3510 bits<4> CRd; 3511 let Inst{24} = 0; // P = 0 3512 let Inst{23} = 1; // U = 1 3513 let Inst{22} = Dbit; 3514 let Inst{21} = 0; // W = 0 3515 let Inst{20} = load; 3516 let Inst{19-16} = addr; 3517 let Inst{15-12} = CRd; 3518 let Inst{11-8} = cop; 3519 let Inst{7-0} = option; 3520 let DecoderMethod = "DecodeCopMemInstruction"; 3521 } 3522 } 3523 3524 defm t2LDC : t2LdStCop<0b1110, 1, 0, "ldc">; 3525 defm t2LDCL : t2LdStCop<0b1110, 1, 1, "ldcl">; 3526 defm t2STC : t2LdStCop<0b1110, 0, 0, "stc">; 3527 defm t2STCL : t2LdStCop<0b1110, 0, 1, "stcl">; 3528 defm t2LDC2 : t2LdStCop<0b1111, 1, 0, "ldc2">; 3529 defm t2LDC2L : t2LdStCop<0b1111, 1, 1, "ldc2l">; 3530 defm t2STC2 : t2LdStCop<0b1111, 0, 0, "stc2">; 3531 defm t2STC2L : t2LdStCop<0b1111, 0, 1, "stc2l">; 3532 3533 3534 //===----------------------------------------------------------------------===// 3535 // Move between special register and ARM core register -- for disassembly only 3536 // 3537 // Move to ARM core register from Special Register 3538 3539 // A/R class MRS. 3540 // 3541 // A/R class can only move from CPSR or SPSR. 3542 def t2MRS_AR : T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, apsr", []>, 3543 Requires<[IsThumb2,IsARClass]> { 3544 bits<4> Rd; 3545 let Inst{31-12} = 0b11110011111011111000; 3546 let Inst{11-8} = Rd; 3547 let Inst{7-0} = 0b0000; 3548 } 3549 3550 def : t2InstAlias<"mrs${p} $Rd, cpsr", (t2MRS_AR GPR:$Rd, pred:$p)>; 3551 3552 def t2MRSsys_AR: T2I<(outs GPR:$Rd), (ins), NoItinerary, "mrs", "\t$Rd, spsr", []>, 3553 Requires<[IsThumb2,IsARClass]> { 3554 bits<4> Rd; 3555 let Inst{31-12} = 0b11110011111111111000; 3556 let Inst{11-8} = Rd; 3557 let Inst{7-0} = 0b0000; 3558 } 3559 3560 // M class MRS. 3561 // 3562 // This MRS has a mask field in bits 7-0 and can take more values than 3563 // the A/R class (a full msr_mask). 3564 def t2MRS_M : T2I<(outs rGPR:$Rd), (ins msr_mask:$mask), NoItinerary, 3565 "mrs", "\t$Rd, $mask", []>, 3566 Requires<[IsThumb2,IsMClass]> { 3567 bits<4> Rd; 3568 bits<8> mask; 3569 let Inst{31-12} = 0b11110011111011111000; 3570 let Inst{11-8} = Rd; 3571 let Inst{19-16} = 0b1111; 3572 let Inst{7-0} = mask; 3573 } 3574 3575 3576 // Move from ARM core register to Special Register 3577 // 3578 // A/R class MSR. 3579 // 3580 // No need to have both system and application versions, the encodings are the 3581 // same and the assembly parser has no way to distinguish between them. The mask 3582 // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains 3583 // the mask with the fields to be accessed in the special register. 3584 def t2MSR_AR : T2I<(outs), (ins msr_mask:$mask, rGPR:$Rn), 3585 NoItinerary, "msr", "\t$mask, $Rn", []>, 3586 Requires<[IsThumb2,IsARClass]> { 3587 bits<5> mask; 3588 bits<4> Rn; 3589 let Inst{31-21} = 0b11110011100; 3590 let Inst{20} = mask{4}; // R Bit 3591 let Inst{19-16} = Rn; 3592 let Inst{15-12} = 0b1000; 3593 let Inst{11-8} = mask{3-0}; 3594 let Inst{7-0} = 0; 3595 } 3596 3597 // M class MSR. 3598 // 3599 // Move from ARM core register to Special Register 3600 def t2MSR_M : T2I<(outs), (ins msr_mask:$SYSm, rGPR:$Rn), 3601 NoItinerary, "msr", "\t$SYSm, $Rn", []>, 3602 Requires<[IsThumb2,IsMClass]> { 3603 bits<8> SYSm; 3604 bits<4> Rn; 3605 let Inst{31-21} = 0b11110011100; 3606 let Inst{20} = 0b0; 3607 let Inst{19-16} = Rn; 3608 let Inst{15-12} = 0b1000; 3609 let Inst{7-0} = SYSm; 3610 } 3611 3612 3613 //===----------------------------------------------------------------------===// 3614 // Move between coprocessor and ARM core register 3615 // 3616 3617 class t2MovRCopro<bits<4> Op, string opc, bit direction, dag oops, dag iops, 3618 list<dag> pattern> 3619 : T2Cop<Op, oops, iops, 3620 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), 3621 pattern> { 3622 let Inst{27-24} = 0b1110; 3623 let Inst{20} = direction; 3624 let Inst{4} = 1; 3625 3626 bits<4> Rt; 3627 bits<4> cop; 3628 bits<3> opc1; 3629 bits<3> opc2; 3630 bits<4> CRm; 3631 bits<4> CRn; 3632 3633 let Inst{15-12} = Rt; 3634 let Inst{11-8} = cop; 3635 let Inst{23-21} = opc1; 3636 let Inst{7-5} = opc2; 3637 let Inst{3-0} = CRm; 3638 let Inst{19-16} = CRn; 3639 } 3640 3641 class t2MovRRCopro<bits<4> Op, string opc, bit direction, 3642 list<dag> pattern = []> 3643 : T2Cop<Op, (outs), 3644 (ins p_imm:$cop, imm0_15:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), 3645 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> { 3646 let Inst{27-24} = 0b1100; 3647 let Inst{23-21} = 0b010; 3648 let Inst{20} = direction; 3649 3650 bits<4> Rt; 3651 bits<4> Rt2; 3652 bits<4> cop; 3653 bits<4> opc1; 3654 bits<4> CRm; 3655 3656 let Inst{15-12} = Rt; 3657 let Inst{19-16} = Rt2; 3658 let Inst{11-8} = cop; 3659 let Inst{7-4} = opc1; 3660 let Inst{3-0} = CRm; 3661 } 3662 3663 /* from ARM core register to coprocessor */ 3664 def t2MCR : t2MovRCopro<0b1110, "mcr", 0, 3665 (outs), 3666 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3667 c_imm:$CRm, imm0_7:$opc2), 3668 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 3669 imm:$CRm, imm:$opc2)]>; 3670 def t2MCR2 : t2MovRCopro<0b1111, "mcr2", 0, 3671 (outs), (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, 3672 c_imm:$CRm, imm0_7:$opc2), 3673 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn, 3674 imm:$CRm, imm:$opc2)]>; 3675 3676 /* from coprocessor to ARM core register */ 3677 def t2MRC : t2MovRCopro<0b1110, "mrc", 1, 3678 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3679 c_imm:$CRm, imm0_7:$opc2), []>; 3680 3681 def t2MRC2 : t2MovRCopro<0b1111, "mrc2", 1, 3682 (outs GPR:$Rt), (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, 3683 c_imm:$CRm, imm0_7:$opc2), []>; 3684 3685 def : T2v6Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 3686 (t2MRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 3687 3688 def : T2v6Pat<(int_arm_mrc2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2), 3689 (t2MRC2 imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>; 3690 3691 3692 /* from ARM core register to coprocessor */ 3693 def t2MCRR : t2MovRRCopro<0b1110, "mcrr", 0, 3694 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2, 3695 imm:$CRm)]>; 3696 def t2MCRR2 : t2MovRRCopro<0b1111, "mcrr2", 0, 3697 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, 3698 GPR:$Rt2, imm:$CRm)]>; 3699 /* from coprocessor to ARM core register */ 3700 def t2MRRC : t2MovRRCopro<0b1110, "mrrc", 1>; 3701 3702 def t2MRRC2 : t2MovRRCopro<0b1111, "mrrc2", 1>; 3703 3704 //===----------------------------------------------------------------------===// 3705 // Other Coprocessor Instructions. 3706 // 3707 3708 def tCDP : T2Cop<0b1110, (outs), (ins p_imm:$cop, imm0_15:$opc1, 3709 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 3710 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 3711 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 3712 imm:$CRm, imm:$opc2)]> { 3713 let Inst{27-24} = 0b1110; 3714 3715 bits<4> opc1; 3716 bits<4> CRn; 3717 bits<4> CRd; 3718 bits<4> cop; 3719 bits<3> opc2; 3720 bits<4> CRm; 3721 3722 let Inst{3-0} = CRm; 3723 let Inst{4} = 0; 3724 let Inst{7-5} = opc2; 3725 let Inst{11-8} = cop; 3726 let Inst{15-12} = CRd; 3727 let Inst{19-16} = CRn; 3728 let Inst{23-20} = opc1; 3729 } 3730 3731 def t2CDP2 : T2Cop<0b1111, (outs), (ins p_imm:$cop, imm0_15:$opc1, 3732 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2), 3733 "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 3734 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn, 3735 imm:$CRm, imm:$opc2)]> { 3736 let Inst{27-24} = 0b1110; 3737 3738 bits<4> opc1; 3739 bits<4> CRn; 3740 bits<4> CRd; 3741 bits<4> cop; 3742 bits<3> opc2; 3743 bits<4> CRm; 3744 3745 let Inst{3-0} = CRm; 3746 let Inst{4} = 0; 3747 let Inst{7-5} = opc2; 3748 let Inst{11-8} = cop; 3749 let Inst{15-12} = CRd; 3750 let Inst{19-16} = CRn; 3751 let Inst{23-20} = opc1; 3752 } 3753 3754 3755 3756 //===----------------------------------------------------------------------===// 3757 // Non-Instruction Patterns 3758 // 3759 3760 // SXT/UXT with no rotate 3761 let AddedComplexity = 16 in { 3762 def : T2Pat<(and rGPR:$Rm, 0x000000FF), (t2UXTB rGPR:$Rm, 0)>, 3763 Requires<[IsThumb2]>; 3764 def : T2Pat<(and rGPR:$Rm, 0x0000FFFF), (t2UXTH rGPR:$Rm, 0)>, 3765 Requires<[IsThumb2]>; 3766 def : T2Pat<(and rGPR:$Rm, 0x00FF00FF), (t2UXTB16 rGPR:$Rm, 0)>, 3767 Requires<[HasT2ExtractPack, IsThumb2]>; 3768 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0x00FF)), 3769 (t2UXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 3770 Requires<[HasT2ExtractPack, IsThumb2]>; 3771 def : T2Pat<(add rGPR:$Rn, (and rGPR:$Rm, 0xFFFF)), 3772 (t2UXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 3773 Requires<[HasT2ExtractPack, IsThumb2]>; 3774 } 3775 3776 def : T2Pat<(sext_inreg rGPR:$Src, i8), (t2SXTB rGPR:$Src, 0)>, 3777 Requires<[IsThumb2]>; 3778 def : T2Pat<(sext_inreg rGPR:$Src, i16), (t2SXTH rGPR:$Src, 0)>, 3779 Requires<[IsThumb2]>; 3780 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i8)), 3781 (t2SXTAB rGPR:$Rn, rGPR:$Rm, 0)>, 3782 Requires<[HasT2ExtractPack, IsThumb2]>; 3783 def : T2Pat<(add rGPR:$Rn, (sext_inreg rGPR:$Rm, i16)), 3784 (t2SXTAH rGPR:$Rn, rGPR:$Rm, 0)>, 3785 Requires<[HasT2ExtractPack, IsThumb2]>; 3786 3787 // Atomic load/store patterns 3788 def : T2Pat<(atomic_load_8 t2addrmode_imm12:$addr), 3789 (t2LDRBi12 t2addrmode_imm12:$addr)>; 3790 def : T2Pat<(atomic_load_8 t2addrmode_negimm8:$addr), 3791 (t2LDRBi8 t2addrmode_negimm8:$addr)>; 3792 def : T2Pat<(atomic_load_8 t2addrmode_so_reg:$addr), 3793 (t2LDRBs t2addrmode_so_reg:$addr)>; 3794 def : T2Pat<(atomic_load_16 t2addrmode_imm12:$addr), 3795 (t2LDRHi12 t2addrmode_imm12:$addr)>; 3796 def : T2Pat<(atomic_load_16 t2addrmode_negimm8:$addr), 3797 (t2LDRHi8 t2addrmode_negimm8:$addr)>; 3798 def : T2Pat<(atomic_load_16 t2addrmode_so_reg:$addr), 3799 (t2LDRHs t2addrmode_so_reg:$addr)>; 3800 def : T2Pat<(atomic_load_32 t2addrmode_imm12:$addr), 3801 (t2LDRi12 t2addrmode_imm12:$addr)>; 3802 def : T2Pat<(atomic_load_32 t2addrmode_negimm8:$addr), 3803 (t2LDRi8 t2addrmode_negimm8:$addr)>; 3804 def : T2Pat<(atomic_load_32 t2addrmode_so_reg:$addr), 3805 (t2LDRs t2addrmode_so_reg:$addr)>; 3806 def : T2Pat<(atomic_store_8 t2addrmode_imm12:$addr, GPR:$val), 3807 (t2STRBi12 GPR:$val, t2addrmode_imm12:$addr)>; 3808 def : T2Pat<(atomic_store_8 t2addrmode_negimm8:$addr, GPR:$val), 3809 (t2STRBi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3810 def : T2Pat<(atomic_store_8 t2addrmode_so_reg:$addr, GPR:$val), 3811 (t2STRBs GPR:$val, t2addrmode_so_reg:$addr)>; 3812 def : T2Pat<(atomic_store_16 t2addrmode_imm12:$addr, GPR:$val), 3813 (t2STRHi12 GPR:$val, t2addrmode_imm12:$addr)>; 3814 def : T2Pat<(atomic_store_16 t2addrmode_negimm8:$addr, GPR:$val), 3815 (t2STRHi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3816 def : T2Pat<(atomic_store_16 t2addrmode_so_reg:$addr, GPR:$val), 3817 (t2STRHs GPR:$val, t2addrmode_so_reg:$addr)>; 3818 def : T2Pat<(atomic_store_32 t2addrmode_imm12:$addr, GPR:$val), 3819 (t2STRi12 GPR:$val, t2addrmode_imm12:$addr)>; 3820 def : T2Pat<(atomic_store_32 t2addrmode_negimm8:$addr, GPR:$val), 3821 (t2STRi8 GPR:$val, t2addrmode_negimm8:$addr)>; 3822 def : T2Pat<(atomic_store_32 t2addrmode_so_reg:$addr, GPR:$val), 3823 (t2STRs GPR:$val, t2addrmode_so_reg:$addr)>; 3824 3825 3826 //===----------------------------------------------------------------------===// 3827 // Assembler aliases 3828 // 3829 3830 // Aliases for ADC without the ".w" optional width specifier. 3831 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $Rm", 3832 (t2ADCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3833 def : t2InstAlias<"adc${s}${p} $Rd, $Rn, $ShiftedRm", 3834 (t2ADCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 3835 pred:$p, cc_out:$s)>; 3836 3837 // Aliases for SBC without the ".w" optional width specifier. 3838 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $Rm", 3839 (t2SBCrr rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3840 def : t2InstAlias<"sbc${s}${p} $Rd, $Rn, $ShiftedRm", 3841 (t2SBCrs rGPR:$Rd, rGPR:$Rn, t2_so_reg:$ShiftedRm, 3842 pred:$p, cc_out:$s)>; 3843 3844 // Aliases for ADD without the ".w" optional width specifier. 3845 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $imm", 3846 (t2ADDri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 3847 def : t2InstAlias<"add${p} $Rd, $Rn, $imm", 3848 (t2ADDri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 3849 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $Rm", 3850 (t2ADDrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3851 def : t2InstAlias<"add${s}${p} $Rd, $Rn, $ShiftedRm", 3852 (t2ADDrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 3853 pred:$p, cc_out:$s)>; 3854 3855 // Aliases for SUB without the ".w" optional width specifier. 3856 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $imm", 3857 (t2SUBri GPRnopc:$Rd, GPRnopc:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 3858 def : t2InstAlias<"sub${p} $Rd, $Rn, $imm", 3859 (t2SUBri12 GPRnopc:$Rd, GPR:$Rn, imm0_4095:$imm, pred:$p)>; 3860 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $Rm", 3861 (t2SUBrr GPRnopc:$Rd, GPRnopc:$Rn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3862 def : t2InstAlias<"sub${s}${p} $Rd, $Rn, $ShiftedRm", 3863 (t2SUBrs GPRnopc:$Rd, GPRnopc:$Rn, t2_so_reg:$ShiftedRm, 3864 pred:$p, cc_out:$s)>; 3865 3866 // Alias for compares without the ".w" optional width specifier. 3867 def : t2InstAlias<"cmn${p} $Rn, $Rm", 3868 (t2CMNzrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 3869 def : t2InstAlias<"teq${p} $Rn, $Rm", 3870 (t2TEQrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 3871 def : t2InstAlias<"tst${p} $Rn, $Rm", 3872 (t2TSTrr GPRnopc:$Rn, rGPR:$Rm, pred:$p)>; 3873 3874 // Memory barriers 3875 def : InstAlias<"dmb", (t2DMB 0xf)>, Requires<[IsThumb2, HasDB]>; 3876 def : InstAlias<"dsb", (t2DSB 0xf)>, Requires<[IsThumb2, HasDB]>; 3877 def : InstAlias<"isb", (t2ISB 0xf)>, Requires<[IsThumb2, HasDB]>; 3878 3879 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional 3880 // width specifier. 3881 def : t2InstAlias<"ldr${p} $Rt, $addr", 3882 (t2LDRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3883 def : t2InstAlias<"ldrb${p} $Rt, $addr", 3884 (t2LDRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3885 def : t2InstAlias<"ldrh${p} $Rt, $addr", 3886 (t2LDRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3887 def : t2InstAlias<"ldrsb${p} $Rt, $addr", 3888 (t2LDRSBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3889 def : t2InstAlias<"ldrsh${p} $Rt, $addr", 3890 (t2LDRSHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3891 3892 def : t2InstAlias<"ldr${p} $Rt, $addr", 3893 (t2LDRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 3894 def : t2InstAlias<"ldrb${p} $Rt, $addr", 3895 (t2LDRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 3896 def : t2InstAlias<"ldrh${p} $Rt, $addr", 3897 (t2LDRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 3898 def : t2InstAlias<"ldrsb${p} $Rt, $addr", 3899 (t2LDRSBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 3900 def : t2InstAlias<"ldrsh${p} $Rt, $addr", 3901 (t2LDRSHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 3902 3903 // Alias for MVN without the ".w" optional width specifier. 3904 def : t2InstAlias<"mvn${s}${p} $Rd, $Rm", 3905 (t2MVNr rGPR:$Rd, rGPR:$Rm, pred:$p, cc_out:$s)>; 3906 def : t2InstAlias<"mvn${s}${p} $Rd, $ShiftedRm", 3907 (t2MVNs rGPR:$Rd, t2_so_reg:$ShiftedRm, pred:$p, cc_out:$s)>; 3908 3909 // PKHBT/PKHTB with default shift amount. PKHTB is equivalent to PKHBT when the 3910 // shift amount is zero (i.e., unspecified). 3911 def : InstAlias<"pkhbt${p} $Rd, $Rn, $Rm", 3912 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>, 3913 Requires<[HasT2ExtractPack, IsThumb2]>; 3914 def : InstAlias<"pkhtb${p} $Rd, $Rn, $Rm", 3915 (t2PKHBT rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>, 3916 Requires<[HasT2ExtractPack, IsThumb2]>; 3917 3918 // PUSH/POP aliases for STM/LDM 3919 def : t2InstAlias<"push${p}.w $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 3920 def : t2InstAlias<"push${p} $regs", (t2STMDB_UPD SP, pred:$p, reglist:$regs)>; 3921 def : t2InstAlias<"pop${p}.w $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 3922 def : t2InstAlias<"pop${p} $regs", (t2LDMIA_UPD SP, pred:$p, reglist:$regs)>; 3923 3924 // Alias for REV/REV16/REVSH without the ".w" optional width specifier. 3925 def : t2InstAlias<"rev${p} $Rd, $Rm", (t2REV rGPR:$Rd, rGPR:$Rm, pred:$p)>; 3926 def : t2InstAlias<"rev16${p} $Rd, $Rm", (t2REV16 rGPR:$Rd, rGPR:$Rm, pred:$p)>; 3927 def : t2InstAlias<"revsh${p} $Rd, $Rm", (t2REVSH rGPR:$Rd, rGPR:$Rm, pred:$p)>; 3928 3929 3930 // Alias for RSB without the ".w" optional width specifier, and with optional 3931 // implied destination register. 3932 def : t2InstAlias<"rsb${s}${p} $Rd, $Rn, $imm", 3933 (t2RSBri rGPR:$Rd, rGPR:$Rn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 3934 def : t2InstAlias<"rsb${s}${p} $Rdn, $imm", 3935 (t2RSBri rGPR:$Rdn, rGPR:$Rdn, t2_so_imm:$imm, pred:$p, cc_out:$s)>; 3936 def : t2InstAlias<"rsb${s}${p} $Rdn, $Rm", 3937 (t2RSBrr rGPR:$Rdn, rGPR:$Rdn, rGPR:$Rm, pred:$p, cc_out:$s)>; 3938 def : t2InstAlias<"rsb${s}${p} $Rdn, $ShiftedRm", 3939 (t2RSBrs rGPR:$Rdn, rGPR:$Rdn, t2_so_reg:$ShiftedRm, pred:$p, 3940 cc_out:$s)>; 3941 3942 // SSAT/USAT optional shift operand. 3943 def : t2InstAlias<"ssat${p} $Rd, $sat_imm, $Rn", 3944 (t2SSAT rGPR:$Rd, imm1_32:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 3945 def : t2InstAlias<"usat${p} $Rd, $sat_imm, $Rn", 3946 (t2USAT rGPR:$Rd, imm0_31:$sat_imm, rGPR:$Rn, 0, pred:$p)>; 3947 3948 // STM w/o the .w suffix. 3949 def : t2InstAlias<"stm${p} $Rn, $regs", 3950 (t2STMIA GPR:$Rn, pred:$p, reglist:$regs)>; 3951 3952 // Alias for STR, STRB, and STRH without the ".w" optional 3953 // width specifier. 3954 def : t2InstAlias<"str${p} $Rt, $addr", 3955 (t2STRi12 GPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3956 def : t2InstAlias<"strb${p} $Rt, $addr", 3957 (t2STRBi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3958 def : t2InstAlias<"strh${p} $Rt, $addr", 3959 (t2STRHi12 rGPR:$Rt, t2addrmode_imm12:$addr, pred:$p)>; 3960 3961 def : t2InstAlias<"str${p} $Rt, $addr", 3962 (t2STRs GPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 3963 def : t2InstAlias<"strb${p} $Rt, $addr", 3964 (t2STRBs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 3965 def : t2InstAlias<"strh${p} $Rt, $addr", 3966 (t2STRHs rGPR:$Rt, t2addrmode_so_reg:$addr, pred:$p)>; 3967 3968 // Extend instruction optional rotate operand. 3969 def : t2InstAlias<"sxtab${p} $Rd, $Rn, $Rm", 3970 (t2SXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 3971 def : t2InstAlias<"sxtah${p} $Rd, $Rn, $Rm", 3972 (t2SXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 3973 def : t2InstAlias<"sxtab16${p} $Rd, $Rn, $Rm", 3974 (t2SXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 3975 3976 def : t2InstAlias<"sxtb${p} $Rd, $Rm", 3977 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 3978 def : t2InstAlias<"sxtb16${p} $Rd, $Rm", 3979 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 3980 def : t2InstAlias<"sxth${p} $Rd, $Rm", 3981 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 3982 def : t2InstAlias<"sxtb${p}.w $Rd, $Rm", 3983 (t2SXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 3984 def : t2InstAlias<"sxth${p}.w $Rd, $Rm", 3985 (t2SXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 3986 3987 def : t2InstAlias<"uxtab${p} $Rd, $Rn, $Rm", 3988 (t2UXTAB rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 3989 def : t2InstAlias<"uxtah${p} $Rd, $Rn, $Rm", 3990 (t2UXTAH rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 3991 def : t2InstAlias<"uxtab16${p} $Rd, $Rn, $Rm", 3992 (t2UXTAB16 rGPR:$Rd, rGPR:$Rn, rGPR:$Rm, 0, pred:$p)>; 3993 def : t2InstAlias<"uxtb${p} $Rd, $Rm", 3994 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 3995 def : t2InstAlias<"uxtb16${p} $Rd, $Rm", 3996 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 3997 def : t2InstAlias<"uxth${p} $Rd, $Rm", 3998 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 3999 4000 def : t2InstAlias<"uxtb${p}.w $Rd, $Rm", 4001 (t2UXTB rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4002 def : t2InstAlias<"uxth${p}.w $Rd, $Rm", 4003 (t2UXTH rGPR:$Rd, rGPR:$Rm, 0, pred:$p)>; 4004 4005 // Extend instruction w/o the ".w" optional width specifier. 4006 def : t2InstAlias<"uxtb${p} $Rd, $Rm$rot", 4007 (t2UXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4008 def : t2InstAlias<"uxtb16${p} $Rd, $Rm$rot", 4009 (t2UXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4010 def : t2InstAlias<"uxth${p} $Rd, $Rm$rot", 4011 (t2UXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4012 4013 def : t2InstAlias<"sxtb${p} $Rd, $Rm$rot", 4014 (t2SXTB rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4015 def : t2InstAlias<"sxtb16${p} $Rd, $Rm$rot", 4016 (t2SXTB16 rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4017 def : t2InstAlias<"sxth${p} $Rd, $Rm$rot", 4018 (t2SXTH rGPR:$Rd, rGPR:$Rm, rot_imm:$rot, pred:$p)>; 4019
