| /prebuilts/vndk/v27/x86/arch-x86-x86/shared/vndk-core/ |
| libvixl-arm64.so | |
| /prebuilts/vndk/v27/x86_64/arch-x86-x86_64/shared/vndk-core/ |
| libvixl-arm64.so | |
| /system/core/libpixelflinger/codeflinger/ |
| GGLAssembler.cpp | 266 LDRB(AL, parts.dither.reg, parts.dither.reg,
[all...] |
| MIPS64Assembler.cpp | 784 void ArmToMips64Assembler::LDRB(int cc __unused, int Rd, int Rn, uint32_t offset)
[all...] |
| /system/core/libpixelflinger/tests/arch-arm64/assembler/ |
| arm64_assembler_test.cpp | 586 case INSTR_LDRB: a64asm->LDRB(test.cond, Rd,Rn,op2); break;
[all...] |
| /system/core/libpixelflinger/tests/arch-mips64/assembler/ |
| mips64_assembler_test.cpp | 539 case INSTR_LDRB: a64asm->LDRB(test.cond, Rd,Rn,op2); break;
|
| /art/compiler/optimizing/ |
| intrinsics_arm64.cc | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrFormats.td | 640 // LDR/LDRB/STR/STRB/...
757 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
[all...] |
| ARMInstrInfo.td | [all...] |
| ARMInstrThumb.td | 707 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| ldst-opt.ll | 35 ; CHECK: ldrb w{{[0-9]+}}, [x{{[0-9]+}}, #32]!
677 ; CHECK: ldrb w{{[0-9]+}}, [x{{[0-9]+}}], #4
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrFormats.td | 511 // LDR/LDRB/STR/STRB/...
628 // FIXME: Merge with the above class when addrmode2 gets used for LDR, LDRB
[all...] |
| ARMInstrInfo.td | [all...] |
| /external/valgrind/none/tests/arm64/ |
| memory.stdout.exp | 5 ldrb w21, [x22, #56] :: rd 00000000000000a8 rn (hidden), cin 0, nzcv 00000000
198 ldrb w13, [x5, #56] with x5 = middle_of_block+3, x6=0
[all...] |
| /external/vixl/doc/aarch64/ |
| supported-instructions-aarch64.md | 594 ### LDRB ###
598 void ldrb(const Register& rt,
[all...] |
| /external/vixl/test/aarch32/ |
| test-assembler-cond-rd-memop-immediate-8192-a32.cc | 53 M(ldrb) \
[all...] |
| test-assembler-cond-rd-memop-rs-a32.cc | 53 M(ldrb) \
[all...] |
| test-assembler-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 53 M(ldrb) \
[all...] |
| test-assembler-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 53 M(ldrb) \
[all...] |
| test-simulator-cond-rd-memop-immediate-8192-a32.cc | 117 M(Ldrb) \
[all...] |
| test-simulator-cond-rd-memop-rs-a32.cc | 117 M(Ldrb) \
[all...] |
| test-simulator-cond-rd-memop-rs-shift-amount-1to31-a32.cc | 117 M(Ldrb) \
[all...] |
| test-simulator-cond-rd-memop-rs-shift-amount-1to32-a32.cc | 117 M(Ldrb) \
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| z8kgen.c | 311 {"------", 14, 8, "0011 0010 0000 ssss disp16", "ldrb disp16,rbs", 0},
312 {"------", 14, 8, "0011 0000 0000 dddd disp16", "ldrb rbd,disp16", 0},
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.td | [all...] |
