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  /external/vixl/src/aarch32/
disasm-aarch32.cc 1728 void Disassembler::ldrd(Condition cond, function in class:vixl::aarch32::Disassembler
1738 void Disassembler::ldrd(Condition cond, function in class:vixl::aarch32::Disassembler
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assembler-aarch32.h 2413 void ldrd(Register rt, Register rt2, const MemOperand& operand) { function in class:vixl::aarch32::Assembler
2423 void ldrd(Register rt, Register rt2, Location* location) { function in class:vixl::aarch32::Assembler
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disasm-aarch32.h 843 void ldrd(Condition cond,
848 void ldrd(Condition cond, Register rt, Register rt2, Location* location);
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  /prebuilts/go/darwin-x86/pkg/darwin_amd64/cmd/vendor/golang.org/x/arch/arm/
armasm.a 355 tables.go ADC_EQ@%  ADC_NE@%" ADC_CS@%|S ADC_CC@%& ADC_MI@%( ADC_PL@%* ADC_VS@%, ADC_VC@%. ADC_HI@%0 ADC_LS@%2 ADC_GE@%4 ADC_LT@%6 ADC_GT@%8 ADC_LE@%:ADC@%< ADC_ZZ@%>ADC_S_EQ@%@ADC_S_NE@%BADC_S_CS@%DADC_S_CC@%FADC_S_MI@%HADC_S_PL@%JADC_S_VS@%LADC_S_VC@%NADC_S_HI@%PADC_S_LS@%RADC_S_GE@%TADC_S_LT@%VADC_S_GT@%XADC_S_LE@%Z ADC_S@%\ADC_S_ZZ@%^ ADD_EQ@%` ADD_NE@%b ADD_CS@%d ADD_CC@%f ADD_MI@%h ADD_PL@%j ADD_VS@%l ADD_VC@%n ADD_HI@%p ADD_LS@%r ADD_GE@%t ADD_LT@%v ADD_GT@%x ADD_LE@%zADD@%|| ADD_ZZ@%~ADD_S_EQ@%?ADD_S_NE@%?ADD_S_CS@%?ADD_S_CC@%?ADD_S_MI@%?ADD_S_PL@%?ADD_S_VS@%?ADD_S_VC@%?ADD_S_HI@%?ADD_S_LS@%?ADD_S_GE@%?ADD_S_LT@%?ADD_S_GT@%?ADD_S_LE@%? ADD_S@%?ADD_S_ZZ@%? AND_EQ@%? AND_NE@%? AND_CS@%? AND_CC@%? AND_MI@%? AND_PL@%? AND_VS@%? AND_VC@%? AND_HI@%? AND_LS@%? AND_GE@%? AND_LT@%? AND_GT@%? AND_LE@%?AND@%? AND_ZZ@%?AND_S_EQ@%?AND_S_NE@%?AND_S_CS@%?AND_S_CC@%?AND_S_MI@%?AND_S_PL@%?AND_S_VS@%?AND_S_VC@%?AND_S_HI@%?AND_S_LS@%?AND_S_GE@%?AND_S_LT@%?AND_S_GT@%?AND_S_LE@%? AND_S@%?AND_S_ZZ@%? ASR_EQ@%? ASR_NE@%? ASR_CS@%? ASR_CC@%? ASR_MI@%? ASR_PL@%? ASR_VS@%? ASR_VC@%? ASR_HI@%? ASR_LS@%? ASR_GE@%? ASR_LT@%? ASR_GT@%? ASR_LE@%?ASR@%? ASR_ZZ@%?ASR_S_EQ@%?ASR_S_NE@%?ASR_S_CS@%?ASR_S_CC@%?ASR_S_MI@%?ASR_S_PL@%?ASR_S_VS@%?ASR_S_VC@%?ASR_S_HI@%?ASR_S_LS@%?ASR_S_GE@%?ASR_S_LT@%?ASR_S_GT@%?ASR_S_LE@%? ASR_S@%?ASR_S_ZZ@%?B_EQ@%?B_NE@%?B_CS@%?B_CC@%?B_MI@%?B_PL@%?B_VS@%?B_VC@%?B_HI@%?B_LS@%?B_GE@%?B_LT@%?B_GT@%?B_LE@%?B@%?B_ZZ@%? BFC_EQ@%? BFC_NE@%? BFC_CS@%? BFC_CC@%? BFC_MI@%? BFC_PL@%? BFC_VS@%? BFC_VC@%? BFC_HI@%? BFC_LS@%? BFC_GE@%? BFC_LT@%? BFC_GT@%? BFC_LE@%?BFC@%? BFC_ZZ@%? BFI_EQ@%? BFI_NE@%? BFI_CS@%? BFI_CC@%? BFI_MI@%? BFI_PL@%? BFI_VS@%? BFI_VC@%? BFI_HI@%? BFI_LS@%? BFI_GE@%? BFI_LT@%? BFI_GT@%? BFI_LE@%?BFI@%? BFI_ZZ@%? BIC_EQ@%? BIC_NE@%? BIC_CS@%? BIC_CC@%? BIC_MI@%? BIC_PL@%? BIC_VS@%? BIC_VC@%? BIC_HI@%? BIC_LS@%? BIC_GE@%? BIC_LT@%? BIC_GT@%? BIC_LE@%?BIC@%? BIC_ZZ@%?BIC_S_EQ@%?BIC_S_NE@%?BIC_S_CS@%?BIC_S_CC@%?BIC_S_MI@%?BIC_S_PL@%?BIC_S_VS@%?BIC_S_VC@%?BIC_S_HI@%?BIC_S_LS@%?BIC_S_GE@%?BIC_S_LT@%?BIC_S_GT@%?BIC_S_LE@%? BIC_S@%?BIC_S_ZZ@%? BKPT_EQ@%? BKPT_NE@%? BKPT_CS@%? BKPT_CC@%? BKPT_MI@%? BKPT_PL@%? BKPT_VS@%? BKPT_VC@%? BKPT_HI@%? BKPT_LS@%? BKPT_GE@%? BKPT_LT@%? BKPT_GT@%? BKPT_LE@%?BKPT@%? BKPT_ZZ@%? BL_EQ@%? BL_NE@%? BL_CS@%? BL_CC@%? BL_MI@%? BL_PL@%? BL_VS@%? BL_VC@%? BL_HI@%? BL_LS@%? BL_GE@%? BL_LT@%? BL_GT@%? BL_LE@%?BL@%? BL_ZZ@%? BLX_EQ@%? BLX_NE@%? BLX_CS@%? BLX_CC@%? BLX_MI@%? BLX_PL@%? BLX_VS@%? BLX_VC@%? BLX_HI@%? BLX_LS@%? BLX_GE@%? BLX_LT@%? BLX_GT@%? BLX_LE@%?BLX@%? BLX_ZZ@%? BX_EQ@%? BX_NE@%? BX_CS@%? BX_CC@%? BX_MI@%? BX_PL@%? BX_VS@%? BX_VC@%? BX_HI@%? BX_LS@%? BX_GE@%? BX_LT@%? BX_GT@%? BX_LE@%?BX@%? BX_ZZ@%? BXJ_EQ@%? BXJ_NE@%? BXJ_CS@%? BXJ_CC@%? BXJ_MI@%? BXJ_PL@%? BXJ_VS@%? BXJ_VC@%? BXJ_HI@%? BXJ_LS@%? BXJ_GE@%? BXJ_LT@%? BXJ_GT@%? BXJ_LE@%?BXJ@%? BXJ_ZZ@%? CLREX@%? CLZ_EQ@%? CLZ_NE@%? CLZ_CS@%? CLZ_CC@%? CLZ_MI@%? CLZ_PL@%? CLZ_VS@%? CLZ_VC@%? CLZ_HI@%? CLZ_LS@%? CLZ_GE@%? CLZ_LT@%? CLZ_GT@%? CLZ_LE@%?CLZ@%? CLZ_ZZ@%? CMN_EQ@%? CMN_NE@%? CMN_CS@%? CMN_CC@%? CMN_MI@%? CMN_PL@%? CMN_VS@%? CMN_VC@%? CMN_HI@%? CMN_LS@%? CMN_GE@%? CMN_LT@%? CMN_GT@%? CMN_LE@%?CMN@%? CMN_ZZ@%? CMP_EQ@%? CMP_NE@%? CMP_CS@%? CMP_CC@%? CMP_MI@%? CMP_PL@%? CMP_VS@%? CMP_VC@%? CMP_HI@%? CMP_LS@%? CMP_GE@%? CMP_LT@%? CMP_GT@%? CMP_LE@%?CMP@%? CMP_ZZ@%? DBG_EQ@%? DBG_NE@%? DBG_CS@%? DBG_CC@%? DBG_MI@%? DBG_PL@%? DBG_VS@%? DBG_VC@%? DBG_HI@%? DBG_LS@%? DBG_GE@%? DBG_LT@%? DBG_GT@%? DBG_LE@%?DBG@%? DBG_ZZ@%?DMB@%?DSB@%? EOR_EQ@%? EOR_NE@%? EOR_CS@%? EOR_CC@%? EOR_MI@%? EOR_PL@%? EOR_VS@%? EOR_VC@%? EOR_HI@%? EOR_LS@%? EOR_GE@%? EOR_LT@%? EOR_GT@%? EOR_LE@%?EOR@%? EOR_ZZ@%?EOR_S_EQ@%?EOR_S_NE@%?EOR_S_CS@%?EOR_S_CC@%?EOR_S_MI@%?EOR_S_PL@%?EOR_S_VS@%?EOR_S_VC@%?EOR_S_HI@%?EOR_S_LS@%?EOR_S_GE@%?EOR_S_LT@%?EOR_S_GT@%?EOR_S_LE@%? EOR_S@%?EOR_S_ZZ@%?ISB@%? LDM_EQ@%? LDM_NE@%? LDM_CS@%? LDM_CC@%? LDM_MI@%? LDM_PL@%? LDM_VS@%? LDM_VC@%? LDM_HI@%? LDM_LS@%? LDM_GE@%? LDM_LT@%? LDM_GT@%? LDM_LE@%?LDM@%? LDM_ZZ@%?LDMDA_EQ@%?LDMDA_NE@%?LDMDA_CS@%?LDMDA_CC@%?LDMDA_MI@%?LDMDA_PL@%?LDMDA_VS@%?LDMDA_VC@%?LDMDA_HI@%?LDMDA_LS@%?LDMDA_GE@%?LDMDA_LT@%?LDMDA_GT@%?LDMDA_LE@%? LDMDA@%?LDMDA_ZZ@%?LDMDB_EQ@%?LDMDB_NE@%?LDMDB_CS@%?LDMDB_CC@%?LDMDB_MI@%?LDMDB_PL@%?LDMDB_VS@%?LDMDB_VC@%?LDMDB_HI@%?LDMDB_LS@%?LDMDB_GE@%?LDMDB_LT@%?LDMDB_GT@%?LDMDB_LE@%? LDMDB@%?LDMDB_ZZ@%?LDMIB_EQ@%?LDMIB_NE@%?LDMIB_CS@%?LDMIB_CC@%?LDMIB_MI@%?LDMIB_PL@%?LDMIB_VS@%?LDMIB_VC@%?LDMIB_HI@%?LDMIB_LS@%?LDMIB_GE@%?LDMIB_LT@%?LDMIB_GT@%?LDMIB_LE@%? LDMIB@%?LDMIB_ZZ@%? LDR_EQ@%? LDR_NE@%? LDR_CS@%? LDR_CC@%? LDR_MI@%? LDR_PL@%? LDR_VS@%? LDR_VC@%? LDR_HI@%? LDR_LS@%? LDR_GE@%? LDR_LT@%? LDR_GT@%? LDR_LE@%?LDR@%? LDR_ZZ@%? LDRB_EQ@%? LDRB_NE@%? LDRB_CS@%? LDRB_CC@%? LDRB_MI@%? LDRB_PL@%? LDRB_VS@%? LDRB_VC@%? LDRB_HI@%? LDRB_LS@%? LDRB_GE@%? LDRB_LT@%? LDRB_GT@%? LDRB_LE@%?LDRB@%? LDRB_ZZ@%?LDRBT_EQ@%?LDRBT_NE@%?LDRBT_CS@%?LDRBT_CC@%?LDRBT_MI@%?LDRBT_PL@%?LDRBT_VS@%?LDRBT_VC@%?LDRBT_HI@%?LDRBT_LS@%?LDRBT_GE@%?LDRBT_LT@%?LDRBT_GT@%?LDRBT_LE@%? LDRBT@%?LDRBT_ZZ@%? LDRD_EQ@%? LDRD_NE@%? LDRD_CS@%? LDRD_CC@%? LDRD_MI@%? LDRD_PL@%? LDRD_VS@%? LDRD_VC@%? LDRD_HI@%? LDRD_LS@%? LDRD_GE@%? LDRD_LT@%? LDRD_GT@%? LDRD_LE@%?LDRD@%? LDRD_ZZ@%?LDREX_EQ@%? LDREX_NE@%? LDREX_CS@%? LDREX_CC@%? LDREX_MI@%? LDREX_PL@%? LDREX_VS@%? LDREX_VC@%? LDREX_HI@%? LDREX_LS@%? LDREX_GE@%? LDREX_LT@%? LDREX_GT@%? LDREX_LE@%?  LDREX@%? LDREX_ZZ@%? LDREXB_EQ@%? LDREXB_NE@%? LDREXB_CS@%? LDREXB_CC@%? LDREXB_MI@%? LDREXB_PL@%? LDREXB_VS@%? LDREXB_VC@%? LDREXB_HI@%? LDREXB_LS@%? LDREXB_GE@%? LDREXB_LT@%? LDREXB_GT@%? LDREXB_LE@%?  LDREXB@%? LDREXB_ZZ@%? LDREXD_EQ@%? LDREXD_NE@%? LDREXD_CS@%? LDREXD_CC@%? LDREXD_MI@%? LDREXD_PL@%? LDREXD_VS@%? LDREXD_VC@%? LDREXD_HI@%? LDREXD_LS@%? LDREXD_GE@%? LDREXD_LT@%? LDREXD_GT@%? LDREXD_LE@%?  LDREXD@%? LDREXD_ZZ@%? LDREXH_EQ@%? LDREXH_NE@%? LDREXH_CS@%? LDREXH_CC@%? LDREXH_MI@%? LDREXH_PL@%? LDREXH_VS@%? LDREXH_VC@%? LDREXH_HI@%? LDREXH_LS@%? LDREXH_GE@%? LDREXH_LT@%? LDREXH_GT@%? LDREXH_LE@%?  LDREXH@%? LDREXH_ZZ@%?  LDRH_EQ@%?
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  /prebuilts/go/linux-x86/pkg/linux_amd64/cmd/vendor/golang.org/x/arch/arm/
armasm.a 355 tables.go ADC_EQ@%  ADC_NE@%" ADC_CS@%|S ADC_CC@%& ADC_MI@%( ADC_PL@%* ADC_VS@%, ADC_VC@%. ADC_HI@%0 ADC_LS@%2 ADC_GE@%4 ADC_LT@%6 ADC_GT@%8 ADC_LE@%:ADC@%< ADC_ZZ@%>ADC_S_EQ@%@ADC_S_NE@%BADC_S_CS@%DADC_S_CC@%FADC_S_MI@%HADC_S_PL@%JADC_S_VS@%LADC_S_VC@%NADC_S_HI@%PADC_S_LS@%RADC_S_GE@%TADC_S_LT@%VADC_S_GT@%XADC_S_LE@%Z ADC_S@%\ADC_S_ZZ@%^ ADD_EQ@%` ADD_NE@%b ADD_CS@%d ADD_CC@%f ADD_MI@%h ADD_PL@%j ADD_VS@%l ADD_VC@%n ADD_HI@%p ADD_LS@%r ADD_GE@%t ADD_LT@%v ADD_GT@%x ADD_LE@%zADD@%|| ADD_ZZ@%~ADD_S_EQ@%?ADD_S_NE@%?ADD_S_CS@%?ADD_S_CC@%?ADD_S_MI@%?ADD_S_PL@%?ADD_S_VS@%?ADD_S_VC@%?ADD_S_HI@%?ADD_S_LS@%?ADD_S_GE@%?ADD_S_LT@%?ADD_S_GT@%?ADD_S_LE@%? ADD_S@%?ADD_S_ZZ@%? AND_EQ@%? AND_NE@%? AND_CS@%? AND_CC@%? AND_MI@%? AND_PL@%? AND_VS@%? AND_VC@%? AND_HI@%? AND_LS@%? AND_GE@%? AND_LT@%? AND_GT@%? AND_LE@%?AND@%? AND_ZZ@%?AND_S_EQ@%?AND_S_NE@%?AND_S_CS@%?AND_S_CC@%?AND_S_MI@%?AND_S_PL@%?AND_S_VS@%?AND_S_VC@%?AND_S_HI@%?AND_S_LS@%?AND_S_GE@%?AND_S_LT@%?AND_S_GT@%?AND_S_LE@%? AND_S@%?AND_S_ZZ@%? ASR_EQ@%? ASR_NE@%? ASR_CS@%? ASR_CC@%? ASR_MI@%? ASR_PL@%? ASR_VS@%? ASR_VC@%? ASR_HI@%? ASR_LS@%? ASR_GE@%? ASR_LT@%? ASR_GT@%? ASR_LE@%?ASR@%? ASR_ZZ@%?ASR_S_EQ@%?ASR_S_NE@%?ASR_S_CS@%?ASR_S_CC@%?ASR_S_MI@%?ASR_S_PL@%?ASR_S_VS@%?ASR_S_VC@%?ASR_S_HI@%?ASR_S_LS@%?ASR_S_GE@%?ASR_S_LT@%?ASR_S_GT@%?ASR_S_LE@%? ASR_S@%?ASR_S_ZZ@%?B_EQ@%?B_NE@%?B_CS@%?B_CC@%?B_MI@%?B_PL@%?B_VS@%?B_VC@%?B_HI@%?B_LS@%?B_GE@%?B_LT@%?B_GT@%?B_LE@%?B@%?B_ZZ@%? BFC_EQ@%? BFC_NE@%? BFC_CS@%? BFC_CC@%? BFC_MI@%? BFC_PL@%? BFC_VS@%? BFC_VC@%? BFC_HI@%? BFC_LS@%? BFC_GE@%? BFC_LT@%? BFC_GT@%? BFC_LE@%?BFC@%? BFC_ZZ@%? BFI_EQ@%? BFI_NE@%? BFI_CS@%? BFI_CC@%? BFI_MI@%? BFI_PL@%? BFI_VS@%? BFI_VC@%? BFI_HI@%? BFI_LS@%? BFI_GE@%? BFI_LT@%? BFI_GT@%? BFI_LE@%?BFI@%? BFI_ZZ@%? BIC_EQ@%? BIC_NE@%? BIC_CS@%? BIC_CC@%? BIC_MI@%? BIC_PL@%? BIC_VS@%? BIC_VC@%? BIC_HI@%? BIC_LS@%? BIC_GE@%? BIC_LT@%? BIC_GT@%? BIC_LE@%?BIC@%? BIC_ZZ@%?BIC_S_EQ@%?BIC_S_NE@%?BIC_S_CS@%?BIC_S_CC@%?BIC_S_MI@%?BIC_S_PL@%?BIC_S_VS@%?BIC_S_VC@%?BIC_S_HI@%?BIC_S_LS@%?BIC_S_GE@%?BIC_S_LT@%?BIC_S_GT@%?BIC_S_LE@%? BIC_S@%?BIC_S_ZZ@%? BKPT_EQ@%? BKPT_NE@%? BKPT_CS@%? BKPT_CC@%? BKPT_MI@%? BKPT_PL@%? BKPT_VS@%? BKPT_VC@%? BKPT_HI@%? BKPT_LS@%? BKPT_GE@%? BKPT_LT@%? BKPT_GT@%? BKPT_LE@%?BKPT@%? BKPT_ZZ@%? BL_EQ@%? BL_NE@%? BL_CS@%? BL_CC@%? BL_MI@%? BL_PL@%? BL_VS@%? BL_VC@%? BL_HI@%? BL_LS@%? BL_GE@%? BL_LT@%? BL_GT@%? BL_LE@%?BL@%? BL_ZZ@%? BLX_EQ@%? BLX_NE@%? BLX_CS@%? BLX_CC@%? BLX_MI@%? BLX_PL@%? BLX_VS@%? BLX_VC@%? BLX_HI@%? BLX_LS@%? BLX_GE@%? BLX_LT@%? BLX_GT@%? BLX_LE@%?BLX@%? BLX_ZZ@%? BX_EQ@%? BX_NE@%? BX_CS@%? BX_CC@%? BX_MI@%? BX_PL@%? BX_VS@%? BX_VC@%? BX_HI@%? BX_LS@%? BX_GE@%? BX_LT@%? BX_GT@%? BX_LE@%?BX@%? BX_ZZ@%? BXJ_EQ@%? BXJ_NE@%? BXJ_CS@%? BXJ_CC@%? BXJ_MI@%? BXJ_PL@%? BXJ_VS@%? BXJ_VC@%? BXJ_HI@%? BXJ_LS@%? BXJ_GE@%? BXJ_LT@%? BXJ_GT@%? BXJ_LE@%?BXJ@%? BXJ_ZZ@%? CLREX@%? CLZ_EQ@%? CLZ_NE@%? CLZ_CS@%? CLZ_CC@%? CLZ_MI@%? CLZ_PL@%? CLZ_VS@%? CLZ_VC@%? CLZ_HI@%? CLZ_LS@%? CLZ_GE@%? CLZ_LT@%? CLZ_GT@%? CLZ_LE@%?CLZ@%? CLZ_ZZ@%? CMN_EQ@%? CMN_NE@%? CMN_CS@%? CMN_CC@%? CMN_MI@%? CMN_PL@%? CMN_VS@%? CMN_VC@%? CMN_HI@%? CMN_LS@%? CMN_GE@%? CMN_LT@%? CMN_GT@%? CMN_LE@%?CMN@%? CMN_ZZ@%? CMP_EQ@%? CMP_NE@%? CMP_CS@%? CMP_CC@%? CMP_MI@%? CMP_PL@%? CMP_VS@%? CMP_VC@%? CMP_HI@%? CMP_LS@%? CMP_GE@%? CMP_LT@%? CMP_GT@%? CMP_LE@%?CMP@%? CMP_ZZ@%? DBG_EQ@%? DBG_NE@%? DBG_CS@%? DBG_CC@%? DBG_MI@%? DBG_PL@%? DBG_VS@%? DBG_VC@%? DBG_HI@%? DBG_LS@%? DBG_GE@%? DBG_LT@%? DBG_GT@%? DBG_LE@%?DBG@%? DBG_ZZ@%?DMB@%?DSB@%? EOR_EQ@%? EOR_NE@%? EOR_CS@%? EOR_CC@%? EOR_MI@%? EOR_PL@%? EOR_VS@%? EOR_VC@%? EOR_HI@%? EOR_LS@%? EOR_GE@%? EOR_LT@%? EOR_GT@%? EOR_LE@%?EOR@%? EOR_ZZ@%?EOR_S_EQ@%?EOR_S_NE@%?EOR_S_CS@%?EOR_S_CC@%?EOR_S_MI@%?EOR_S_PL@%?EOR_S_VS@%?EOR_S_VC@%?EOR_S_HI@%?EOR_S_LS@%?EOR_S_GE@%?EOR_S_LT@%?EOR_S_GT@%?EOR_S_LE@%? EOR_S@%?EOR_S_ZZ@%?ISB@%? LDM_EQ@%? LDM_NE@%? LDM_CS@%? LDM_CC@%? LDM_MI@%? LDM_PL@%? LDM_VS@%? LDM_VC@%? LDM_HI@%? LDM_LS@%? LDM_GE@%? LDM_LT@%? LDM_GT@%? LDM_LE@%?LDM@%? LDM_ZZ@%?LDMDA_EQ@%?LDMDA_NE@%?LDMDA_CS@%?LDMDA_CC@%?LDMDA_MI@%?LDMDA_PL@%?LDMDA_VS@%?LDMDA_VC@%?LDMDA_HI@%?LDMDA_LS@%?LDMDA_GE@%?LDMDA_LT@%?LDMDA_GT@%?LDMDA_LE@%? LDMDA@%?LDMDA_ZZ@%?LDMDB_EQ@%?LDMDB_NE@%?LDMDB_CS@%?LDMDB_CC@%?LDMDB_MI@%?LDMDB_PL@%?LDMDB_VS@%?LDMDB_VC@%?LDMDB_HI@%?LDMDB_LS@%?LDMDB_GE@%?LDMDB_LT@%?LDMDB_GT@%?LDMDB_LE@%? LDMDB@%?LDMDB_ZZ@%?LDMIB_EQ@%?LDMIB_NE@%?LDMIB_CS@%?LDMIB_CC@%?LDMIB_MI@%?LDMIB_PL@%?LDMIB_VS@%?LDMIB_VC@%?LDMIB_HI@%?LDMIB_LS@%?LDMIB_GE@%?LDMIB_LT@%?LDMIB_GT@%?LDMIB_LE@%? LDMIB@%?LDMIB_ZZ@%? LDR_EQ@%? LDR_NE@%? LDR_CS@%? LDR_CC@%? LDR_MI@%? LDR_PL@%? LDR_VS@%? LDR_VC@%? LDR_HI@%? LDR_LS@%? LDR_GE@%? LDR_LT@%? LDR_GT@%? LDR_LE@%?LDR@%? LDR_ZZ@%? LDRB_EQ@%? LDRB_NE@%? LDRB_CS@%? LDRB_CC@%? LDRB_MI@%? LDRB_PL@%? LDRB_VS@%? LDRB_VC@%? LDRB_HI@%? LDRB_LS@%? LDRB_GE@%? LDRB_LT@%? LDRB_GT@%? LDRB_LE@%?LDRB@%? LDRB_ZZ@%?LDRBT_EQ@%?LDRBT_NE@%?LDRBT_CS@%?LDRBT_CC@%?LDRBT_MI@%?LDRBT_PL@%?LDRBT_VS@%?LDRBT_VC@%?LDRBT_HI@%?LDRBT_LS@%?LDRBT_GE@%?LDRBT_LT@%?LDRBT_GT@%?LDRBT_LE@%? LDRBT@%?LDRBT_ZZ@%? LDRD_EQ@%? LDRD_NE@%? LDRD_CS@%? LDRD_CC@%? LDRD_MI@%? LDRD_PL@%? LDRD_VS@%? LDRD_VC@%? LDRD_HI@%? LDRD_LS@%? LDRD_GE@%? LDRD_LT@%? LDRD_GT@%? LDRD_LE@%?LDRD@%? LDRD_ZZ@%?LDREX_EQ@%? LDREX_NE@%? LDREX_CS@%? LDREX_CC@%? LDREX_MI@%? LDREX_PL@%? LDREX_VS@%? LDREX_VC@%? LDREX_HI@%? LDREX_LS@%? LDREX_GE@%? LDREX_LT@%? LDREX_GT@%? LDREX_LE@%?  LDREX@%? LDREX_ZZ@%? LDREXB_EQ@%? LDREXB_NE@%? LDREXB_CS@%? LDREXB_CC@%? LDREXB_MI@%? LDREXB_PL@%? LDREXB_VS@%? LDREXB_VC@%? LDREXB_HI@%? LDREXB_LS@%? LDREXB_GE@%? LDREXB_LT@%? LDREXB_GT@%? LDREXB_LE@%?  LDREXB@%? LDREXB_ZZ@%? LDREXD_EQ@%? LDREXD_NE@%? LDREXD_CS@%? LDREXD_CC@%? LDREXD_MI@%? LDREXD_PL@%? LDREXD_VS@%? LDREXD_VC@%? LDREXD_HI@%? LDREXD_LS@%? LDREXD_GE@%? LDREXD_LT@%? LDREXD_GT@%? LDREXD_LE@%?  LDREXD@%? LDREXD_ZZ@%? LDREXH_EQ@%? LDREXH_NE@%? LDREXH_CS@%? LDREXH_CC@%? LDREXH_MI@%? LDREXH_PL@%? LDREXH_VS@%? LDREXH_VC@%? LDREXH_HI@%? LDREXH_LS@%? LDREXH_GE@%? LDREXH_LT@%? LDREXH_GT@%? LDREXH_LE@%?  LDREXH@%? LDREXH_ZZ@%?  LDRH_EQ@%?
    [all...]
  /external/boringssl/src/crypto/curve25519/asm/
x25519-asm-arm.S 2111 ldrd r4,[sp,#0] label
2112 ldrd r6,[sp,#8] label
2113 ldrd r8,[sp,#16] label
2114 ldrd r10,[sp,#24] label
    [all...]
  /external/llvm/lib/Target/ARM/
Thumb2InstrInfo.cpp 189 // Thumb2 LDRD expects its dest-registers to be in rGPR. Not a problem for
ARMScheduleSwift.td 360 (instregex "t2LDRDi8", "LDRD$")>;
    [all...]
  /external/swiftshader/third_party/LLVM/include/llvm/MC/
MCInstrDesc.h 526 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
  /prebuilts/vndk/v27/x86/arch-x86-x86/shared/vndk-core/
libvixl-arm.so 
  /prebuilts/vndk/v27/x86_64/arch-x86-x86_64/shared/vndk-core/
libvixl-arm.so 
  /toolchain/binutils/binutils-2.27/gas/config/
tc-epiphany.c 437 #define LDSTODD _("ldrd/strd requires even:odd register pair")
  /toolchain/binutils/binutils-2.27/gas/testsuite/
ChangeLog-2011 760 * gas/arm/ldrd-unpredicatble.d: New testcase.
761 * gas/arm/ldrd-unpredicatble.s: Likewise.
762 * gas/arm/ldrd-unpredicatble.l: Likewise.
    [all...]
  /external/swiftshader/third_party/LLVM/test/MC/ARM/
basic-thumb2-instructions.s 725 @ LDRD
727 ldrd r3, r5, [r6, #24]
728 ldrd r3, r5, [r6, #24]!
729 ldrd r3, r5, [r6], #4
730 ldrd r3, r5, [r6], #-8
731 ldrd r3, r5, [r6]
732 ldrd r8, r1, [r3, #0]
734 @ CHECK: ldrd r3, r5, [r6, #24] @ encoding: [0xd6,0xe9,0x06,0x35]
735 @ CHECK: ldrd r3, r5, [r6, #24]! @ encoding: [0xf6,0xe9,0x06,0x35]
736 @ CHECK: ldrd r3, r5, [r6], #4 @ encoding: [0xf6,0xe8,0x01,0x35
    [all...]
  /external/libavc/encoder/arm/
ime_distortion_metrics_a9q.s 266 ldrd r6, r7, [sp, #16]
458 ldrd r4, r5, [sp, #16] @ load ref stride to r4, src stride to r5
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMCodeEmitter.cpp     [all...]
  /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
thumb2.txt 604 # LDRD(immediate)
606 # CHECK: ldrd r3, r5, [r6, #24]
607 # CHECK: ldrd r3, r5, [r6, #24]!
608 # CHECK: ldrd r3, r5, [r6], #4
609 # CHECK: ldrd r3, r5, [r6], #-8
610 # CHECK: ldrd r3, r5, [r6]
611 # CHECK: ldrd r8, r1, [r3]
622 # FIXME: LDRD(literal)
    [all...]
  /external/llvm/include/llvm/MC/
MCInstrDesc.h 459 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
  /external/swiftshader/third_party/LLVM/docs/
Atomics.html 274 does multiple memory operations, like <code>LDRD</code> on ARM).</dd>
  /external/swiftshader/third_party/subzero/src/
IceAssemblerARM32.h 758 // Emit ldrh/ldrd/strh/strd instruction with given address using encoding 3.
    [all...]
  /external/valgrind/memcheck/tests/
atomic_incs.c 652 "ldrd r2, r3, [r5, #8]" "\n\t" // n
  /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/MC/
MCInstrDesc.h 487 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
  /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/MC/
MCInstrDesc.h 487 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
  /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/MC/
MCInstrDesc.h 487 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,
  /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/MC/
MCInstrDesc.h 496 /// classes. e.g. ARM::LDRD's two def registers must be an even / odd pair,

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