| /external/llvm/test/CodeGen/WebAssembly/ |
| inline-asm.ll | 10 ; CHECK-NEXT: .param i32{{$}}
11 ; CHECK-NEXT: .result i32{{$}}
12 ; CHECK-NEXT: #APP{{$}}
13 ; CHECK-NEXT: # $0 = aaa($0){{$}}
14 ; CHECK-NEXT: #NO_APP{{$}}
15 ; CHECK-NEXT: return $0{{$}}
23 ; CHECK-NEXT: .param i32, i32{{$}}
24 ; CHECK-NEXT: #APP{{$}}
25 ; CHECK-NEXT: # 0($1) = bbb(0($0)){{$}}
26 ; CHECK-NEXT: #NO_APP{{$}
[all...] |
| call.ll | 18 ; CHECK-NEXT: .result i32{{$}}
19 ; CHECK-NEXT: {{^}} i32.call $push[[NUM:[0-9]+]]=, i32_nullary@FUNCTION{{$}}
20 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
27 ; CHECK-NEXT: .result i64{{$}}
28 ; CHECK-NEXT: {{^}} i64.call $push[[NUM:[0-9]+]]=, i64_nullary@FUNCTION{{$}}
29 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
36 ; CHECK-NEXT: .result f32{{$}}
37 ; CHECK-NEXT: {{^}} f32.call $push[[NUM:[0-9]+]]=, float_nullary@FUNCTION{{$}}
38 ; CHECK-NEXT: return $pop[[NUM]]{{$}}
45 ; CHECK-NEXT: .result f64{{$}
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| avx512dq-mask-op.ll | 7 ; CHECK-NEXT: kmovb %edi, %k0
8 ; CHECK-NEXT: knotb %k0, %k0
9 ; CHECK-NEXT: kmovb %k0, %eax
10 ; CHECK-NEXT: ## kill: %AL<def> %AL<kill> %EAX<kill>
11 ; CHECK-NEXT: retq
21 ; CHECK-NEXT: kmovb (%rdi), %k0
22 ; CHECK-NEXT: knotb %k0, %k0
23 ; CHECK-NEXT: kmovb %k0, (%rdi)
24 ; CHECK-NEXT: retq
36 ; CHECK-NEXT: movl %edi, %ea
[all...] |
| fixup-bw-copy.ll | 12 ; BWON64-NEXT: movl %edi, %eax
13 ; BWON64-NEXT: retq
17 ; BWOFF64-NEXT: movb %dil, %al
18 ; BWOFF64-NEXT: retq
22 ; X32-NEXT: movb {{[0-9]+}}(%esp), %al
23 ; X32-NEXT: retl
30 ; BWON64-NEXT: movl %edi, %eax
31 ; BWON64-NEXT: retq
35 ; BWOFF64-NEXT: movw %di, %ax
36 ; BWOFF64-NEXT: ret
[all...] |
| fma_patterns.ll | 15 ; FMA-NEXT: vfmadd213ss %xmm2, %xmm1, %xmm0
16 ; FMA-NEXT: retq
20 ; FMA4-NEXT: vfmaddss %xmm2, %xmm1, %xmm0, %xmm0
21 ; FMA4-NEXT: retq
25 ; AVX512-NEXT: vfmadd213ss %xmm2, %xmm0, %xmm1
26 ; AVX512-NEXT: vmovaps %zmm1, %zmm0
27 ; AVX512-NEXT: retq
36 ; FMA-NEXT: vfmadd213ps %xmm2, %xmm1, %xmm0
37 ; FMA-NEXT: retq
41 ; FMA4-NEXT: vfmaddps %xmm2, %xmm1, %xmm0, %xmm
[all...] |
| vector-popcnt-256.ll | 8 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm1
9 ; AVX1-NEXT: vmovaps {{.*#+}} xmm2 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15]
10 ; AVX1-NEXT: vandps %xmm2, %xmm1, %xmm3
11 ; AVX1-NEXT: vmovdqa {{.*#+}} xmm4 = [0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4]
12 ; AVX1-NEXT: vpshufb %xmm3, %xmm4, %xmm3
13 ; AVX1-NEXT: vpsrlw $4, %xmm1, %xmm1
14 ; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
15 ; AVX1-NEXT: vpshufb %xmm1, %xmm4, %xmm1
16 ; AVX1-NEXT: vpaddb %xmm3, %xmm1, %xmm1
17 ; AVX1-NEXT: vpxor %xmm3, %xmm3, %xmm
[all...] |
| sse2-intrinsics-x86.ll | 8 ; SSE-NEXT: addsd %xmm1, %xmm0
9 ; SSE-NEXT: retl
13 ; KNL-NEXT: vaddsd %xmm1, %xmm0, %xmm0
14 ; KNL-NEXT: retl
24 ; SSE-NEXT: cmpordpd %xmm1, %xmm0
25 ; SSE-NEXT: retl
29 ; KNL-NEXT: vcmpordpd %xmm1, %xmm0, %xmm0
30 ; KNL-NEXT: retl
40 ; SSE-NEXT: cmpordsd %xmm1, %xmm0
41 ; SSE-NEXT: ret
[all...] |
| vector-shift-shl-512.ll | 12 ; ALL-NEXT: vpsllvq %zmm1, %zmm0, %zmm0
13 ; ALL-NEXT: retq
21 ; ALL-NEXT: vpsllvd %zmm1, %zmm0, %zmm0
22 ; ALL-NEXT: retq
30 ; AVX512DQ-NEXT: vpxor %ymm4, %ymm4, %ymm4
31 ; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} ymm5 = ymm2[4],ymm4[4],ymm2[5],ymm4[5],ymm2[6],ymm4[6],ymm2[7],ymm4[7],ymm2[12],ymm4[12],ymm2[13],ymm4[13],ymm2[14],ymm4[14],ymm2[15],ymm4[15]
32 ; AVX512DQ-NEXT: vpunpckhwd {{.*#+}} ymm6 = ymm4[4],ymm0[4],ymm4[5],ymm0[5],ymm4[6],ymm0[6],ymm4[7],ymm0[7],ymm4[12],ymm0[12],ymm4[13],ymm0[13],ymm4[14],ymm0[14],ymm4[15],ymm0[15]
33 ; AVX512DQ-NEXT: vpsllvd %ymm5, %ymm6, %ymm5
34 ; AVX512DQ-NEXT: vpsrld $16, %ymm5, %ymm5
35 ; AVX512DQ-NEXT: vpunpcklwd {{.*#+}} ymm2 = ymm2[0],ymm4[0],ymm2[1],ymm4[1],ymm2[2],ymm4[2],ymm2[3],ymm4[3],ymm (…)
[all...] |
| sse41.ll | 9 ; X32-NEXT: pinsrd $1, {{[0-9]+}}(%esp), %xmm0
10 ; X32-NEXT: retl
14 ; X64-NEXT: pinsrd $1, %edi, %xmm0
15 ; X64-NEXT: retq
23 ; X32-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
24 ; X32-NEXT: retl
28 ; X64-NEXT: pinsrb $1, %edi, %xmm0
29 ; X64-NEXT: retq
37 ; X32-NEXT: movl L_g16$non_lazy_ptr, %eax
38 ; X32-NEXT: pmovzxbq {{.*#+}} xmm0 = mem[0],zero,zero,zero,zero,zero,zero,zero,mem[1],zero,zero,zero,zero, (…)
[all...] |
| setcc-lowering.ll | 12 ; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
13 ; AVX-NEXT: vextractf128 $1, %ymm0, %xmm1
14 ; AVX-NEXT: vpxor %xmm2, %xmm2, %xmm2
15 ; AVX-NEXT: vpcmpeqd %xmm2, %xmm1, %xmm1
16 ; AVX-NEXT: vmovdqa {{.*#+}} xmm3 = [0,1,4,5,8,9,12,13,8,9,12,13,12,13,14,15]
17 ; AVX-NEXT: vpshufb %xmm3, %xmm1, %xmm1
18 ; AVX-NEXT: vpcmpeqd %xmm2, %xmm0, %xmm0
19 ; AVX-NEXT: vpshufb %xmm3, %xmm0, %xmm0
20 ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0]
21 ; AVX-NEXT: vpor {{.*}}(%rip), %xmm0, %xmm
[all...] |
| vector-shuffle-128-v8.ll | 14 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
15 ; SSE-NEXT: retq
19 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,0,1,1]
20 ; AVX-NEXT: retq
27 ; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
28 ; SSE-NEXT: retq
32 ; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[3,2,1,0]
33 ; AVX-NEXT: retq
40 ; SSE2-NEXT: shufpd {{.*#+}} xmm0 = xmm0[1],xmm1[0]
41 ; SSE2-NEXT: ret
[all...] |
| i64-mem-copy.ll | 11 ; X64-NEXT: movq (%rsi), %rax
12 ; X64-NEXT: movq %rax, (%rdi)
13 ; X64-NEXT: retq
17 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
18 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
19 ; X32-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
20 ; X32-NEXT: movsd %xmm0, (%eax)
21 ; X32-NEXT: retl
33 ; X64-NEXT: paddw %xmm1, %xmm0
34 ; X64-NEXT: movq %xmm0, (%rdi
[all...] |
| vector-shuffle-sse1.ll | 9 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,0,1]
10 ; SSE1-NEXT: retq
17 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,0,2,0]
18 ; SSE1-NEXT: retq
25 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,3,0,0]
26 ; SSE1-NEXT: retq
33 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,0,0,0]
34 ; SSE1-NEXT: retq
41 ; SSE1-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,2,0,0]
42 ; SSE1-NEXT: ret
[all...] |
| /external/llvm/test/tools/llvm-profdata/ |
| compat.proftext | 14 # FUNC_COUNT_ONLY-NEXT: Counters: 1
15 # FUNC_COUNT_ONLY-NEXT: Function count: 97531
16 # FUNC_COUNT_ONLY-NEXT: Block counts: []
25 # SPACES-NEXT: Counters: 2
26 # SPACES-NEXT: Function count: 0
27 # SPACES-NEXT: Block counts: [0]
40 # LARGENUM-NEXT: Counters: 6
41 # LARGENUM-NEXT: Function count: 2305843009213693952
42 # LARGENUM-NEXT: Block counts: [1152921504606846976, 576460752303423488, 288230376151711744, 144115188075855872, 72057594037927936]
52 # FORMATV2-NEXT: foo
[all...] |
| /hardware/intel/common/wrs_omxil_core/utils/src/ |
| list.c | 27 entry->next = NULL;
70 while (list->next)
71 list = list->next;
104 list = list->next;
118 prev->next = new;
120 new->next = entry;
129 struct list *next; local
132 next = entry->next;
133 if (next)
195 struct list *prev, *next; local
[all...] |
| /external/llvm/test/CodeGen/XCore/ |
| llvm-intrinsics.ll | 14 ; CHECK-NEXT: retsp 0
23 ; CHECK-NEXT: ldaw r0, sp[0]
24 ; CHECK-NEXT: retsp 100
34 ; CHECK-NEXT: ldw r0, sp[0]
35 ; CHECK-NEXT: ldw lr, sp[0]
36 ; CHECK-NEXT: retsp 0
45 ; CHECK-NEXT: ldw r0, sp[100]
46 ; CHECK-NEXT: retsp 100
57 ; CHECK-NEXT: ldaw r1, sp[0]
58 ; CHECK-NEXT: add r0, r1, r
[all...] |
| /external/clang/test/CodeGen/ |
| ppc64-varargs-complex.c | 12 // CHECK-NEXT: %[[VAR41:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR40]], i64 16
13 // CHECK-NEXT: store i8* %[[VAR41]], i8** %[[VAR100]]
14 // CHECK-NEXT: %[[VAR1:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR40]], i64 4
15 // CHECK-NEXT: %[[VAR2:[A-Za-z0-9.]+]] = getelementptr inbounds i8, i8* %[[VAR40]], i64 12
16 // CHECK-NEXT: %[[VAR4:[A-Za-z0-9.]+]] = bitcast i8* %[[VAR1]] to i32*
17 // CHECK-NEXT: %[[VAR5:[A-Za-z0-9.]+]] = bitcast i8* %[[VAR2]] to i32*
18 // CHECK-NEXT: %[[VAR6:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR4]], align 4
19 // CHECK-NEXT: %[[VAR7:[A-Za-z0-9.]+]] = load i32, i32* %[[VAR5]], align 4
20 // CHECK-NEXT: %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR0:[A-Za-z0-9.]+]], i32 0, i32 0
21 // CHECK-NEXT: %[[VAR9:[A-Za-z0-9.]+]] = getelementptr inbounds { i32, i32 }, { i32, i32 }* %[[VAR0]], i32 0, i3 (…)
[all...] |
| complex-convert.c | 38 // CHECK-NEXT: %[[VAR2:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR1]]
39 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR2]], i[[CHSIZE]]* %[[SC1:[A-Za-z0-9.]+]], align [[CHALIGN]]
42 // CHECK-NEXT: %[[VAR3:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[CHSIZE]], i[[CHSIZE]] }, { i[[CHSIZE]], i[[CHSIZE]] }* %[[CUC:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
43 // CHECK-NEXT: %[[VAR4:[A-Za-z0-9.]+]] = load i[[CHSIZE]], i[[CHSIZE]]* %[[VAR3]]
44 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR4]], i[[CHSIZE]]* %[[SC1]], align [[CHALIGN]]
47 // CHECK-NEXT: %[[VAR5:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[[LLSIZE]] }* %[[CSLL:[A-Za-z0-9.]+]], i{{[0-9]+}} 0, i{{[0-9]+}} 0
48 // CHECK-NEXT: %[[VAR6:[A-Za-z0-9.]+]] = load i[[LLSIZE]], i[[LLSIZE]]* %[[VAR5]]
49 // CHECK-NEXT: %[[VAR7:[A-Za-z0-9.]+]] = trunc i[[LLSIZE]] %[[VAR6]] to i[[CHSIZE]]
50 // CHECK-NEXT: store i[[CHSIZE]] %[[VAR7]], i[[CHSIZE]]* %[[SC1]], align [[CHALIGN]]
53 // CHECK-NEXT: %[[VAR8:[A-Za-z0-9.]+]] = getelementptr inbounds { i[[LLSIZE]], i[[LLSIZE]] }, { i[[LLSIZE]], i[ (…)
[all...] |
| c11atomics-ios.c | 12 // CHECK-NEXT: [[X:%.*]] = alloca float
13 // CHECK-NEXT: [[F:%.*]] = alloca float
14 // CHECK-NEXT: store float* {{%.*}}, float** [[FP]]
16 // CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]]
17 // CHECK-NEXT: store float 1.000000e+00, float* [[T0]], align 4
20 // CHECK-NEXT: store float 2.000000e+00, float* [[X]], align 4
23 // CHECK-NEXT: [[T0:%.*]] = load float*, float** [[FP]]
24 // CHECK-NEXT: [[T1:%.*]] = bitcast float* [[T0]] to i32*
25 // CHECK-NEXT: [[T2:%.*]] = load atomic i32, i32* [[T1]] seq_cst, align 4
26 // CHECK-NEXT: [[T3:%.*]] = bitcast i32 [[T2]] to floa
[all...] |
| sparcv9-dwarf.c | 12 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 1)
13 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 2)
14 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 3)
15 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 4)
16 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 5)
17 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 6)
18 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 7)
19 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 8)
20 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i32 9)
21 // CHECK-NEXT: store i8 8, i8* getelementptr inbounds ([103 x i8], [103 x i8]* @dwarf_reg_size_table, i32 0, i3 (…)
[all...] |
| /dalvik/dx/tests/032-bb-live-code/ |
| expected.txt | 6 next 0004
15 next 0002
19 next 0007
20 next 0006
21 next 0004
26 next 0005
41 next 0002
44 next 0003
47 next 0004
61 next 000
[all...] |
| /external/clang/test/CodeGenObjC/ |
| ns_consume_null_check.m | 21 // CHECK-NEXT: [[SIX:%.*]] = bitcast
22 // CHECK-NEXT: [[SEVEN:%.*]] = icmp eq i8* [[SIX]], null
23 // CHECK-NEXT: br i1 [[SEVEN]], label [[NULLINIT:%.*]], label [[CALL_LABEL:%.*]]
25 // CHECK-NEXT: [[EIGHT:%.*]] = bitcast i8* [[FN]]
26 // CHECK-NEXT: [[CALL:%.*]] = call signext i8 [[EIGHT]]
27 // CHECK-NEXT: br label [[CONT:%.*]]
29 // CHECK-NEXT: br label [[CONT]]
41 // CHECK-NEXT: [[WEAKOBJ:%.*]] = alloca i8*, align 8
42 // CHECK-NEXT: [[RESULT:%.*]] = alloca { float, float }, align 4
45 // CHECK-NEXT: store i8* [[T0]], i8** [[OBJ]
[all...] |
| /external/clang/test/OpenMP/ |
| dump.cpp | 8 // CHECK-NEXT: | |-DeclRefExpr {{.+}} <col:27> 'int' lvalue Var {{.+}} 'ga' 'int'
9 // CHECK-NEXT: | `-DeclRefExpr {{.+}} <col:31> 'int' lvalue Var {{.+}} 'gb' 'int'
16 // CHECK-NEXT: | |-CompoundAssignOperator {{.+}} <col:47, col:58> 'int' lvalue '*=' ComputeLHSTy='int' ComputeResultTy='int'
17 // CHECK-NEXT: | | |-DeclRefExpr {{.+}} <col:47> 'int' lvalue Var {{.+}} 'omp_out' 'int'
18 // CHECK-NEXT: | | `-ImplicitCastExpr {{.+}} <col:58> 'int' <LValueToRValue>
19 // CHECK-NEXT: | | `-DeclRefExpr {{.+}} <col:58> 'int' lvalue Var {{.+}} 'omp_in' 'int'
20 // CHECK-NEXT: | |-VarDecl {{.+}} <col:35> col:35 implicit used omp_in 'int'
21 // CHECK-NEXT: | `-VarDecl {{.+}} <col:35> col:35 implicit used omp_out 'int'
22 // CHECK-NEXT: |-OMPDeclareReductionDecl {{.+}} <col:40> col:40 operator+ 'char' combiner
23 // CHECK-NEXT: | |-CompoundAssignOperator {{.+}} <col:47, col:58> 'char' lvalue '*=' ComputeLHSTy='int' ComputeR (…)
[all...] |
| /external/swiftshader/third_party/subzero/tests_lit/asan_tests/ |
| globalreplacement.ll | 33 ; DUMP-NEXT: @__$rz_array
34 ; DUMP-NEXT: @__$rz_sizes
35 ; DUMP-NEXT: @__$rz0
36 ; DUMP-NEXT: @global_malloc = internal global i32
38 ; DUMP-NEXT: @__$rz1
39 ; DUMP-NEXT: @__$rz2
40 ; DUMP-NEXT: @global_realloc = internal global i32
42 ; DUMP-NEXT: @__$rz3
43 ; DUMP-NEXT: @__$rz4
44 ; DUMP-NEXT: @global_calloc = internal global i3
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| saxpy10-a9.ll | 17 ; CHECK-NEXT: vldr
18 ; CHECK-NEXT: vmul
19 ; CHECK-NEXT: vadd
20 ; CHECK-NEXT: vadd
21 ; CHECK-NEXT: vldr
22 ; CHECK-NEXT: vldr
23 ; CHECK-NEXT: vadd
24 ; CHECK-NEXT: vadd
25 ; CHECK-NEXT: vmul
26 ; CHECK-NEXT: vld
[all...] |
