| /external/llvm/test/Transforms/LoopVectorize/X86/ |
| imprecise-through-phis.ll | 18 %i = phi i32 [0, %entry], [%i.next, %next.iter]
19 %tot = phi double [0.0, %entry], [%tot.next, %next.iter]
29 br label %next.iter
32 br label %next.iter
34 next.iter:
35 %tot.next = phi double [%tot, %no.add], [%tot.new, %do.add]
36 %i.next = add i32 %i, 1
37 %again = icmp ult i32 %i.next, 3
[all...] |
| /external/mesa3d/src/compiler/glsl/ |
| list.h | 11 * The above copyright notice and this permission notice (including the next
31 * \c next pointer being \c NULL.
33 * A list is empty if either the head sentinel's \c next pointer points to the
55 struct exec_node *next; member in struct:exec_node
61 exec_node() : next(NULL), prev(NULL)
115 n->next = NULL;
122 return n->next;
128 return n->next;
146 n->next->prev = n->prev;
147 n->prev->next = n->next
[all...] |
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| fused-alloca.ll | 28 ; CHECK-NEXT: sub esp,0x3c
29 ; CHECK-NEXT: mov eax,DWORD PTR [esp+0x40]
30 ; CHECK-NEXT: mov DWORD PTR [esp+0x10],eax
31 ; CHECK-NEXT: mov DWORD PTR [esp+0x18],eax
32 ; CHECK-NEXT: mov DWORD PTR [esp],eax
33 ; CHECK-NEXT: add esp,0x3c
58 ; CHECK-NEXT: push ebp
59 ; CHECK-NEXT: mov ebp,esp
60 ; CHECK-NEXT: sub esp,0xb8
61 ; CHECK-NEXT: and esp,0xffffffc
[all...] |
| /external/fio/ |
| flist.h | 22 * sometimes we already know the next/prev entries and we can
28 struct flist_head *next, *prev; member in struct:flist_head
37 (ptr)->next = (ptr); (ptr)->prev = (ptr); \
44 * the prev/next entries already!
48 struct flist_head *next)
50 next->prev = new_entry;
51 new_entry->next = next;
53 prev->next = new_entry;
67 __flist_add(new_entry, head, head->next);
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| lower-vec-shift.ll | 17 ; SSE-NEXT: psrlw
18 ; SSE-NEXT: movss
20 ; AVX-NEXT: vpsrlw
21 ; AVX-NEXT: vmovss
23 ; AVX2-NEXT: vpsrlw
24 ; AVX2-NEXT: vmovss
34 ; SSE-NEXT: psrlw
35 ; SSE-NEXT: movsd
37 ; AVX-NEXT: vpsrlw
38 ; AVX-NEXT: vmovs
[all...] |
| fast-isel-bitcasts-avx.ll | 8 ;CHECK-NEXT: .cfi_startproc
9 ;CHECK-NEXT: ret
16 ;CHECK-NEXT: .cfi_startproc
17 ;CHECK-NEXT: ret
24 ;CHECK-NEXT: .cfi_startproc
25 ;CHECK-NEXT: ret
32 ;CHECK-NEXT: .cfi_startproc
33 ;CHECK-NEXT: ret
40 ;CHECK-NEXT: .cfi_startproc
41 ;CHECK-NEXT: re
[all...] |
| fast-isel-bitcasts.ll | 9 ;CHECK-NEXT: .cfi_startproc
10 ;CHECK-NEXT: ret
17 ;CHECK-NEXT: .cfi_startproc
18 ;CHECK-NEXT: ret
25 ;CHECK-NEXT: .cfi_startproc
26 ;CHECK-NEXT: ret
33 ;CHECK-NEXT: .cfi_startproc
34 ;CHECK-NEXT: ret
41 ;CHECK-NEXT: .cfi_startproc
42 ;CHECK-NEXT: re
[all...] |
| merge-consecutive-loads-256.ll | 12 ; AVX-NEXT: vmovups 32(%rdi), %ymm0
13 ; AVX-NEXT: retq
17 ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %eax
18 ; X32-AVX-NEXT: vmovups 32(%eax), %ymm0
19 ; X32-AVX-NEXT: retl
31 ; AVX-NEXT: vmovaps 32(%rdi), %xmm0
32 ; AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1
33 ; AVX-NEXT: vinsertf128 $1, %xmm1, %ymm0, %ymm0
34 ; AVX-NEXT: retq
38 ; X32-AVX-NEXT: movl {{[0-9]+}}(%esp), %ea
[all...] |
| /external/clang/test/CodeGenCXX/ |
| microsoft-abi-vtables-multiple-nonvirtual-inheritance-return-adjustment.cpp | 28 // CHECK-NEXT: 0 | test1::C *test1::X::foo()
29 // CHECK-NEXT: [return adjustment (to type 'struct test1::B *'): 4 non-virtual]
30 // CHECK-NEXT: 1 | void test1::D::z()
31 // CHECK-NEXT: 2 | test1::C *test1::X::foo()
34 // CHECK-NEXT: 0 | [return adjustment (to type 'struct test1::B *'): 4 non-virtual]
37 // CHECK-NEXT: 2 | test1::C *test1::X::foo()
75 // CHECK-NEXT: 0 | test2::F *test2::X::foo()
76 // CHECK-NEXT: [return adjustment (to type 'struct test2::B *'): 4 non-virtual]
77 // CHECK-NEXT: 1 | void test2::D::z()
78 // CHECK-NEXT: 2 | test2::F *test2::X::foo(
[all...] |
| /external/llvm/test/Bitcode/ |
| thinlto-function-summary-callgraph-pgo.ll | 9 ; CHECK-NEXT: <VERSION
12 ; CHECK-NEXT: <PERMODULE_PROFILE {{.*}} op4=[[FUNCID:[0-9]+]] op5=1 op6=1/>
13 ; CHECK-NEXT: </GLOBALVAL_SUMMARY_BLOCK>
14 ; CHECK-NEXT: <VALUE_SYMTAB
15 ; CHECK-NEXT: <FNENTRY {{.*}} record string = 'main'
17 ; CHECK-NEXT: <ENTRY {{.*}} op0=[[FUNCID]] {{.*}} record string = 'func'
18 ; CHECK-NEXT: </VALUE_SYMTAB>
21 ; COMBINED-NEXT: <VERSION
22 ; COMBINED-NEXT: <COMBINED
25 ; COMBINED-NEXT: <COMBINED_PROFILE {{.*}} op5=[[FUNCID:[0-9]+]] op6=1 op7=1/
[all...] |
| thinlto-function-summary-callgraph.ll | 9 ; CHECK-NEXT: <VERSION
12 ; CHECK-NEXT: <PERMODULE {{.*}} op4=[[FUNCID:[0-9]+]] op5=1/>
13 ; CHECK-NEXT: </GLOBALVAL_SUMMARY_BLOCK>
14 ; CHECK-NEXT: <VALUE_SYMTAB
15 ; CHECK-NEXT: <FNENTRY {{.*}} record string = 'main'
17 ; CHECK-NEXT: <ENTRY {{.*}} op0=[[FUNCID]] {{.*}} record string = 'func'
18 ; CHECK-NEXT: </VALUE_SYMTAB>
21 ; COMBINED-NEXT: <VERSION
22 ; COMBINED-NEXT: <COMBINED
25 ; COMBINED-NEXT: <COMBINED {{.*}} op5=[[FUNCID:[0-9]+]] op6=1/
[all...] |
| /external/llvm/test/CodeGen/SystemZ/ |
| vec-perm-09.ll | 16 ; CHECK-VECTOR-NEXT: .byte 19
17 ; CHECK-VECTOR-NEXT: .byte 6
18 ; CHECK-VECTOR-NEXT: .byte 5
19 ; CHECK-VECTOR-NEXT: .byte 20
20 ; CHECK-VECTOR-NEXT: .byte 22
21 ; CHECK-VECTOR-NEXT: .byte 1
22 ; CHECK-VECTOR-NEXT: .byte 1
23 ; CHECK-VECTOR-NEXT: .byte 25
24 ; CHECK-VECTOR-NEXT: .byte 29
25 ; CHECK-VECTOR-NEXT: .byte 1
[all...] |
| vec-perm-12.ll | 17 ; CHECK-VECTOR-NEXT: .byte 13
18 ; CHECK-VECTOR-NEXT: .byte 14
19 ; CHECK-VECTOR-NEXT: .byte 15
20 ; CHECK-VECTOR-NEXT: .byte 8
21 ; CHECK-VECTOR-NEXT: .byte 9
22 ; CHECK-VECTOR-NEXT: .byte 10
23 ; CHECK-VECTOR-NEXT: .byte 11
24 ; CHECK-VECTOR-NEXT: .byte 4
25 ; CHECK-VECTOR-NEXT: .byte 5
26 ; CHECK-VECTOR-NEXT: .byte
[all...] |
| /external/llvm/test/CodeGen/XCore/ |
| ashr.ll | 7 ; CHECK-NEXT: ashr r0, r0, r1
14 ; CHECK-NEXT: ashr r0, r0, 24
21 ; CHECK-NEXT: ashr r0, r0, 32
32 ; CHECK-NEXT: ashr r0, r0, 32
33 ; CHECK-NEXT: bt r0
44 ; CHECK-NEXT: ashr r0, r0, 32
45 ; CHECK-NEXT: bt r0
53 ; CHECK-NEXT: ashr r0, r0, 32
54 ; CHECK-NEXT: bt r0
55 ; CHECK-NEXT: ldc r0, 1
[all...] |
| /external/llvm/test/MC/ARM/ |
| dwarf-asm-multiple-sections-dwarf-2.s | 33 // DWARF-NEXT: DW_AT_name [DW_FORM_string] ("a")
37 // DWARF-NEXT: Address Range Header: length = 0x00000024, version = 0x0002, cu_offset = 0x00000000, addr_size = 0x04, seg_size = 0x00
38 // DWARF-NEXT: [0x00000000 - 0x00000004)
39 // DWARF-NEXT: [0x00000000 - 0x00000004)
43 // DWARF-NEXT: 0x0000000000000004 7 0 1 0 0 is_stmt end_sequence
45 // DWARF-NEXT: 0x0000000000000004 11 0 1 0 0 is_stmt end_sequence
54 // RELOC-NEXT: 00000006 R_ARM_ABS32 .debug_abbrev
55 // RELOC-NEXT: 0000000c R_ARM_ABS32 .debug_line
56 // RELOC-NEXT: R_ARM_ABS32 .text
57 // RELOC-NEXT: R_ARM_ABS32 .tex
[all...] |
| /external/llvm/test/MC/AsmParser/ |
| section_names.s | 34 # CHECK-NEXT: Type: SHT_PROGBITS
36 # CHECK-NEXT: Type: SHT_PROGBITS
38 # CHECK-NEXT: Type: SHT_PROGBITS
40 # CHECK-NEXT: Type: SHT_INIT_ARRAY
42 # CHECK-NEXT: Type: SHT_PROGBITS
44 # CHECK-NEXT: Type: SHT_PROGBITS
46 # CHECK-NEXT: Type: SHT_FINI_ARRAY
48 # CHECK-NEXT: Type: SHT_PROGBITS
50 # CHECK-NEXT: Type: SHT_PROGBITS
52 # CHECK-NEXT: Type: SHT_PREINIT_ARRA
[all...] |
| /external/llvm/test/Transforms/InstCombine/ |
| 2008-11-20-DivMulRem.ll | 7 ; CHECK-NEXT: urem
11 ; CHECK-NEXT: ret
17 ; CHECK-NEXT: srem
21 ; CHECK-NEXT: ret
27 ; CHECK-NEXT: urem
30 ; CHECK-NEXT: sub
32 ; CHECK-NEXT: ret
38 ; CHECK-NEXT: urem
40 ; CHECK-NEXT: sub
42 ; CHECK-NEXT: ad
[all...] |
| log-pow.ll | 10 ; CHECK-NEXT: %log = call fast double @log(double %x)
11 ; CHECK-NEXT: %mul = fmul fast double %log, %y
12 ; CHECK-NEXT: ret double %mul
21 ; CHECK-NEXT: %pow = call double @llvm.pow.f64(double %x, double %y)
22 ; CHECK-NEXT: %call = call fast double @log(double %pow)
23 ; CHECK-NEXT: ret double %call
32 ; CHECK-NEXT: %call1 = call double %fptr()
33 ; CHECK-NEXT: %pow = call double @log(double %call1)
34 ; CHECK-NEXT: ret double %pow
43 ; CHECK-NEXT: %call2 = call fast double @exp2(double %x
[all...] |
| shift-shift.ll | 10 ; CHECK-NEXT: entry:
11 ; CHECK-NEXT: br label %loop
13 ; CHECK-NEXT: br label %loop
29 ; CHECK-NEXT: entry:
30 ; CHECK-NEXT: br label %loop
32 ; CHECK-NEXT: br label %loop
49 ; CHECK-NEXT: codeRepl:
50 ; CHECK-NEXT: br label %for.cond
52 ; CHECK-NEXT: [[STOREMERGE:%.*]] = phi i32 [ 0, %codeRepl ], [ 5, %for.cond ]
53 ; CHECK-NEXT: store i32 [[STOREMERGE]], i32* %g, align
[all...] |
| /external/llvm/test/Transforms/SafeStack/ |
| setjmp2.ll | 16 ; CHECK-NEXT: %[[DYNPTR:.*]] = alloca i8*
17 ; CHECK-NEXT: store i8* %[[SP]], i8** %[[DYNPTR]]
19 ; CHECK-NEXT: %[[ZEXT:.*]] = zext i32 %[[ARG]] to i64
20 ; CHECK-NEXT: %[[MUL:.*]] = mul i64 %[[ZEXT]], 4
21 ; CHECK-NEXT: %[[SP2:.*]] = load i8*, i8** @__safestack_unsafe_stack_ptr
22 ; CHECK-NEXT: %[[PTRTOINT:.*]] = ptrtoint i8* %[[SP2]] to i64
23 ; CHECK-NEXT: %[[SUB:.*]] = sub i64 %[[PTRTOINT]], %[[MUL]]
24 ; CHECK-NEXT: %[[AND:.*]] = and i64 %[[SUB]], -16
25 ; CHECK-NEXT: %[[INTTOPTR:.*]] = inttoptr i64 %[[AND]] to i8*
26 ; CHECK-NEXT: store i8* %[[INTTOPTR]], i8** @__safestack_unsafe_stack_pt
[all...] |
| /external/perfetto/src/base/ |
| string_splitter_unittest.cc | 35 EXPECT_FALSE(ss.Next());
43 EXPECT_FALSE(ss.Next());
51 EXPECT_TRUE(ss.Next());
54 EXPECT_FALSE(ss.Next());
59 EXPECT_TRUE(ss.Next());
62 EXPECT_FALSE(ss.Next());
66 EXPECT_TRUE(ss.Next());
69 EXPECT_FALSE(ss.Next());
73 EXPECT_TRUE(ss.Next());
76 EXPECT_FALSE(ss.Next());
[all...] |
| /external/swiftshader/third_party/LLVM/test/CodeGen/XCore/ |
| ashr.ll | 7 ; CHECK-NEXT: ashr r0, r0, r1
14 ; CHECK-NEXT: ashr r0, r0, 24
21 ; CHECK-NEXT: ashr r0, r0, 32
32 ; CHECK-NEXT: ashr r0, r0, 32
33 ; CHECK-NEXT: bf r0
44 ; CHECK-NEXT: ashr r0, r0, 32
45 ; CHECK-NEXT: bt r0
53 ; CHECK-NEXT: ashr r0, r0, 32
54 ; CHECK-NEXT: bf r0
55 ; CHECK-NEXT: ldc r0, 1
[all...] |
| /external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
| 2008-11-20-DivMulRem.ll | 7 ; CHECK-NEXT: urem
11 ; CHECK-NEXT: ret
17 ; CHECK-NEXT: srem
21 ; CHECK-NEXT: ret
27 ; CHECK-NEXT: urem
30 ; CHECK-NEXT: sub
32 ; CHECK-NEXT: ret
38 ; CHECK-NEXT: urem
40 ; CHECK-NEXT: sub
42 ; CHECK-NEXT: ad
[all...] |
| /external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/ |
| mov-reg.ll | 30 ; ASM-NEXT:.LtestMovWithAsr$entry:
31 ; IASM-NEXT:.LtestMovWithAsr$entry:
37 ; ASM-NEXT: sxtb r0, r0
38 ; DIS-NEXT: 0: e6af0070
39 ; IASM-NEXT: .byte 0x70
40 ; IASM-NEXT: .byte 0x0
41 ; IASM-NEXT: .byte 0xaf
42 ; IASM-NEXT: .byte 0xe6
45 ; ASM-NEXT: mov r1, r0, asr #31
46 ; DIS-NEXT: 4: e1a01fc
[all...] |
| /external/swiftshader/third_party/subzero/tests_lit/reader_tests/ |
| unnamed.ll | 29 ; CHECK-NEXT: __0:
30 ; CHECK-NEXT: ret i32 %__0
31 ; CHECK-NEXT: }
38 ; CHECK-NEXT: define internal void @hg() {
39 ; CHECK-NEXT: __0:
40 ; CHECK-NEXT: ret void
41 ; CHECK-NEXT: }
47 ; CHECK-NEXT: define internal void @Function1() {
48 ; CHECK-NEXT: __0:
49 ; CHECK-NEXT: ret voi
[all...] |
