| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_conditional_render.c | 84 OUT_BATCH(GEN7_MI_PREDICATE |
|
| brw_wm_state.c | 250 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
|
| brw_sampler_state.c | 71 OUT_BATCH(packet_headers[stage_state->stage] << 16 | (2 - 2));
72 OUT_BATCH(stage_state->sampler_offset);
|
| /external/tensorflow/tensorflow/core/kernels/ |
| fractional_avg_pool_op.cc | 244 const int64 out_batch = out_backprop.dim_size(0); variable
277 out_cols * out_rows * out_batch);
282 for (int64 b = 0; b < out_batch; ++b) {
|
| mkl_conv_ops.h | 237 int out_batch = GetTensorDim(input_shape, data_format_, 'N'); local
253 ShapeFromFormat(data_format_, out_batch, out_rows, out_cols, out_depth);
258 mkldnn_sizes[MklDnnDims::Dim_N] = out_batch;
|
| conv_ops.cc | 564 const int64 out_batch = GetTensorDim(*output, data_format, 'N'); local
638 output_desc.set_count(out_batch)
670 ShapeFromFormat(FORMAT_NCHW, out_batch, out_rows,
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_batchbuffer.c | 263 OUT_BATCH(MI_FLUSH);
|
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_blit.c | 450 OUT_BATCH(R200_CP_CMD_3D_DRAW_IMMD_2 | (12 << 16));
451 OUT_BATCH(RADEON_CP_VC_CNTL_PRIM_WALK_RING |
|
| r200_context.c | 151 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_context.c | 116 OUT_BATCH(CP_PACKET0(RADEON_RB3D_ZPASS_ADDR, 0));
|
| /external/tensorflow/tensorflow/contrib/lite/kernels/internal/reference/ |
| reference_ops.h | [all...] |
| /external/tensorflow/tensorflow/contrib/lite/kernels/internal/optimized/ |
| optimized_ops.h | [all...] |
