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  /device/linaro/bootloader/edk2/UefiCpuPkg/Include/Register/Msr/
SkylakeMsr.h 687 /// processor Voltage Regulator (VR).
    [all...]
XeonDMsr.h 818 /// Voltage Regulator.
    [all...]
HaswellMsr.h     [all...]
GoldmontMsr.h     [all...]
HaswellEMsr.h 911 /// Voltage Regulator.
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  /device/linaro/bootloader/edk2/Omap35xxPkg/MMCHSDxe/
MMCHS.c 362 //Configure voltage regulator for MMC1 in Power IC to output 3.0 voltage.
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  /frameworks/native/cmds/atrace/
atrace.cpp 206 { REQ, "events/regulator/enable" },
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  /hardware/broadcom/wlan/bcmdhd/dhdutil/include/
bcmdevs.h 420 #define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
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  /system/sepolicy/prebuilts/api/26.0/private/
file_contexts 509 /sys/kernel/debug/tracing/events/regulator/enable u:object_r:tracing_shell_writable_debug:s0
  /device/linaro/bootloader/edk2/ShellPkg/Library/UefiShellDebug1CommandsLib/SmbiosView/
SmbiosViewStrings.uni     [all...]
  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
meminit.c 602 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
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  /external/syslinux/gpxe/src/drivers/net/e1000/
e1000_hw.h     [all...]
  /external/syslinux/gpxe/src/drivers/net/
sky2.h     [all...]
  /frameworks/base/core/res/res/values-bs/
strings.xml     [all...]
  /external/jline/src/src/test/resources/jline/example/
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