1 /** @file 2 MSR Definitions for Intel processors based on the Skylake microarchitecture. 3 4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures 5 are provided for MSRs that contain one or more bit fields. If the MSR value 6 returned is a single 32-bit or 64-bit value, then a data structure is not 7 provided for that MSR. 8 9 Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> 10 This program and the accompanying materials 11 are licensed and made available under the terms and conditions of the BSD License 12 which accompanies this distribution. The full text of the license may be found at 13 http://opensource.org/licenses/bsd-license.php 14 15 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 16 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 17 18 @par Specification Reference: 19 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, 20 September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15. 21 22 **/ 23 24 #ifndef __SKYLAKE_MSR_H__ 25 #define __SKYLAKE_MSR_H__ 26 27 #include <Register/ArchitecturalMsr.h> 28 29 /** 30 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, 31 RW if MSR_PLATFORM_INFO.[28] = 1. 32 33 @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT (0x000001AD) 34 @param EAX Lower 32-bits of MSR value. 35 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. 36 @param EDX Upper 32-bits of MSR value. 37 Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER. 38 39 <b>Example usage</b> 40 @code 41 MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER Msr; 42 43 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT); 44 @endcode 45 @note MSR_SKYLAKE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM. 46 **/ 47 #define MSR_SKYLAKE_TURBO_RATIO_LIMIT 0x000001AD 48 49 /** 50 MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT 51 **/ 52 typedef union { 53 /// 54 /// Individual bit fields 55 /// 56 struct { 57 /// 58 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio 59 /// limit of 1 core active. 60 /// 61 UINT32 Maximum1C:8; 62 /// 63 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio 64 /// limit of 2 core active. 65 /// 66 UINT32 Maximum2C:8; 67 /// 68 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio 69 /// limit of 3 core active. 70 /// 71 UINT32 Maximum3C:8; 72 /// 73 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio 74 /// limit of 4 core active. 75 /// 76 UINT32 Maximum4C:8; 77 UINT32 Reserved:32; 78 } Bits; 79 /// 80 /// All bit fields as a 32-bit value 81 /// 82 UINT32 Uint32; 83 /// 84 /// All bit fields as a 64-bit value 85 /// 86 UINT64 Uint64; 87 } MSR_SKYLAKE_TURBO_RATIO_LIMIT_REGISTER; 88 89 90 /** 91 Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-4) 92 that points to the MSR containing the most recent branch record. 93 94 @param ECX MSR_SKYLAKE_LASTBRANCH_TOS (0x000001C9) 95 @param EAX Lower 32-bits of MSR value. 96 @param EDX Upper 32-bits of MSR value. 97 98 <b>Example usage</b> 99 @code 100 UINT64 Msr; 101 102 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS); 103 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_TOS, Msr); 104 @endcode 105 @note MSR_SKYLAKE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM. 106 **/ 107 #define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9 108 109 110 /** 111 Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of 112 an 128-bit external entropy value for key derivation of an enclave. 113 114 @param ECX MSR_SKYLAKE_SGXOWNER0 (0x00000300) 115 @param EAX Lower 32-bits of MSR value. 116 @param EDX Upper 32-bits of MSR value. 117 118 <b>Example usage</b> 119 @code 120 UINT64 Msr; 121 122 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER0); 123 @endcode 124 @note MSR_SKYLAKE_SGXOWNER0 is defined as MSR_SGXOWNER0 in SDM. 125 **/ 126 #define MSR_SKYLAKE_SGXOWNER0 0x00000300 127 128 129 /** 130 Package. Upper 64 Bit OwnerEpoch Component of SGX Key (RO). Upper 64 bits of 131 an 128-bit external entropy value for key derivation of an enclave. 132 133 @param ECX MSR_SKYLAKE_SGXOWNER1 (0x00000301) 134 @param EAX Lower 32-bits of MSR value. 135 @param EDX Upper 32-bits of MSR value. 136 137 <b>Example usage</b> 138 @code 139 UINT64 Msr; 140 141 Msr = AsmReadMsr64 (MSR_SKYLAKE_SGXOWNER1); 142 @endcode 143 @note MSR_SKYLAKE_SGXOWNER1 is defined as MSR_SGXOWNER1 in SDM. 144 **/ 145 #define MSR_SKYLAKE_SGXOWNER1 0x00000301 146 147 148 /** 149 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring 150 Version 4.". 151 152 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS (0x0000038E) 153 @param EAX Lower 32-bits of MSR value. 154 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. 155 @param EDX Upper 32-bits of MSR value. 156 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER. 157 158 <b>Example usage</b> 159 @code 160 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr; 161 162 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS); 163 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64); 164 @endcode 165 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM. 166 **/ 167 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 0x0000038E 168 169 /** 170 MSR information returned for MSR index #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS 171 **/ 172 typedef union { 173 /// 174 /// Individual bit fields 175 /// 176 struct { 177 /// 178 /// [Bit 0] Thread. Ovf_PMC0. 179 /// 180 UINT32 Ovf_PMC0:1; 181 /// 182 /// [Bit 1] Thread. Ovf_PMC1. 183 /// 184 UINT32 Ovf_PMC1:1; 185 /// 186 /// [Bit 2] Thread. Ovf_PMC2. 187 /// 188 UINT32 Ovf_PMC2:1; 189 /// 190 /// [Bit 3] Thread. Ovf_PMC3. 191 /// 192 UINT32 Ovf_PMC3:1; 193 /// 194 /// [Bit 4] Thread. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). 195 /// 196 UINT32 Ovf_PMC4:1; 197 /// 198 /// [Bit 5] Thread. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). 199 /// 200 UINT32 Ovf_PMC5:1; 201 /// 202 /// [Bit 6] Thread. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). 203 /// 204 UINT32 Ovf_PMC6:1; 205 /// 206 /// [Bit 7] Thread. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). 207 /// 208 UINT32 Ovf_PMC7:1; 209 UINT32 Reserved1:24; 210 /// 211 /// [Bit 32] Thread. Ovf_FixedCtr0. 212 /// 213 UINT32 Ovf_FixedCtr0:1; 214 /// 215 /// [Bit 33] Thread. Ovf_FixedCtr1. 216 /// 217 UINT32 Ovf_FixedCtr1:1; 218 /// 219 /// [Bit 34] Thread. Ovf_FixedCtr2. 220 /// 221 UINT32 Ovf_FixedCtr2:1; 222 UINT32 Reserved2:20; 223 /// 224 /// [Bit 55] Thread. Trace_ToPA_PMI. 225 /// 226 UINT32 Trace_ToPA_PMI:1; 227 UINT32 Reserved3:2; 228 /// 229 /// [Bit 58] Thread. LBR_Frz. 230 /// 231 UINT32 LBR_Frz:1; 232 /// 233 /// [Bit 59] Thread. CTR_Frz. 234 /// 235 UINT32 CTR_Frz:1; 236 /// 237 /// [Bit 60] Thread. ASCI. 238 /// 239 UINT32 ASCI:1; 240 /// 241 /// [Bit 61] Thread. Ovf_Uncore. 242 /// 243 UINT32 Ovf_Uncore:1; 244 /// 245 /// [Bit 62] Thread. Ovf_BufDSSAVE. 246 /// 247 UINT32 Ovf_BufDSSAVE:1; 248 /// 249 /// [Bit 63] Thread. CondChgd. 250 /// 251 UINT32 CondChgd:1; 252 } Bits; 253 /// 254 /// All bit fields as a 64-bit value 255 /// 256 UINT64 Uint64; 257 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_REGISTER; 258 259 260 /** 261 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring 262 Version 4.". 263 264 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET (0x00000390) 265 @param EAX Lower 32-bits of MSR value. 266 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 267 @param EDX Upper 32-bits of MSR value. 268 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER. 269 270 <b>Example usage</b> 271 @code 272 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER Msr; 273 274 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET); 275 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET, Msr.Uint64); 276 @endcode 277 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET is defined as IA32_PERF_GLOBAL_STATUS_RESET in SDM. 278 **/ 279 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 0x00000390 280 281 /** 282 MSR information returned for MSR index 283 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET 284 **/ 285 typedef union { 286 /// 287 /// Individual bit fields 288 /// 289 struct { 290 /// 291 /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0. 292 /// 293 UINT32 Ovf_PMC0:1; 294 /// 295 /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1. 296 /// 297 UINT32 Ovf_PMC1:1; 298 /// 299 /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2. 300 /// 301 UINT32 Ovf_PMC2:1; 302 /// 303 /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3. 304 /// 305 UINT32 Ovf_PMC3:1; 306 /// 307 /// [Bit 4] Thread. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4). 308 /// 309 UINT32 Ovf_PMC4:1; 310 /// 311 /// [Bit 5] Thread. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5). 312 /// 313 UINT32 Ovf_PMC5:1; 314 /// 315 /// [Bit 6] Thread. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6). 316 /// 317 UINT32 Ovf_PMC6:1; 318 /// 319 /// [Bit 7] Thread. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7). 320 /// 321 UINT32 Ovf_PMC7:1; 322 UINT32 Reserved1:24; 323 /// 324 /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0. 325 /// 326 UINT32 Ovf_FixedCtr0:1; 327 /// 328 /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1. 329 /// 330 UINT32 Ovf_FixedCtr1:1; 331 /// 332 /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2. 333 /// 334 UINT32 Ovf_FixedCtr2:1; 335 UINT32 Reserved2:20; 336 /// 337 /// [Bit 55] Thread. Set 1 to clear Trace_ToPA_PMI. 338 /// 339 UINT32 Trace_ToPA_PMI:1; 340 UINT32 Reserved3:2; 341 /// 342 /// [Bit 58] Thread. Set 1 to clear LBR_Frz. 343 /// 344 UINT32 LBR_Frz:1; 345 /// 346 /// [Bit 59] Thread. Set 1 to clear CTR_Frz. 347 /// 348 UINT32 CTR_Frz:1; 349 /// 350 /// [Bit 60] Thread. Set 1 to clear ASCI. 351 /// 352 UINT32 ASCI:1; 353 /// 354 /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore. 355 /// 356 UINT32 Ovf_Uncore:1; 357 /// 358 /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE. 359 /// 360 UINT32 Ovf_BufDSSAVE:1; 361 /// 362 /// [Bit 63] Thread. Set 1 to clear CondChgd. 363 /// 364 UINT32 CondChgd:1; 365 } Bits; 366 /// 367 /// All bit fields as a 64-bit value 368 /// 369 UINT64 Uint64; 370 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_RESET_REGISTER; 371 372 373 /** 374 See Table 35-2. See Section 18.2.4, "Architectural Performance Monitoring 375 Version 4.". 376 377 @param ECX MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET (0x00000391) 378 @param EAX Lower 32-bits of MSR value. 379 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 380 @param EDX Upper 32-bits of MSR value. 381 Described by the type MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER. 382 383 <b>Example usage</b> 384 @code 385 MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER Msr; 386 387 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET); 388 AsmWriteMsr64 (MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET, Msr.Uint64); 389 @endcode 390 @note MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET is defined as IA32_PERF_GLOBAL_STATUS_SET in SDM. 391 **/ 392 #define MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 0x00000391 393 394 /** 395 MSR information returned for MSR index 396 #MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET 397 **/ 398 typedef union { 399 /// 400 /// Individual bit fields 401 /// 402 struct { 403 /// 404 /// [Bit 0] Thread. Set 1 to cause Ovf_PMC0 = 1. 405 /// 406 UINT32 Ovf_PMC0:1; 407 /// 408 /// [Bit 1] Thread. Set 1 to cause Ovf_PMC1 = 1. 409 /// 410 UINT32 Ovf_PMC1:1; 411 /// 412 /// [Bit 2] Thread. Set 1 to cause Ovf_PMC2 = 1. 413 /// 414 UINT32 Ovf_PMC2:1; 415 /// 416 /// [Bit 3] Thread. Set 1 to cause Ovf_PMC3 = 1. 417 /// 418 UINT32 Ovf_PMC3:1; 419 /// 420 /// [Bit 4] Thread. Set 1 to cause Ovf_PMC4=1 (if CPUID.0AH:EAX[15:8] > 4). 421 /// 422 UINT32 Ovf_PMC4:1; 423 /// 424 /// [Bit 5] Thread. Set 1 to cause Ovf_PMC5=1 (if CPUID.0AH:EAX[15:8] > 5). 425 /// 426 UINT32 Ovf_PMC5:1; 427 /// 428 /// [Bit 6] Thread. Set 1 to cause Ovf_PMC6=1 (if CPUID.0AH:EAX[15:8] > 6). 429 /// 430 UINT32 Ovf_PMC6:1; 431 /// 432 /// [Bit 7] Thread. Set 1 to cause Ovf_PMC7=1 (if CPUID.0AH:EAX[15:8] > 7). 433 /// 434 UINT32 Ovf_PMC7:1; 435 UINT32 Reserved1:24; 436 /// 437 /// [Bit 32] Thread. Set 1 to cause Ovf_FixedCtr0 = 1. 438 /// 439 UINT32 Ovf_FixedCtr0:1; 440 /// 441 /// [Bit 33] Thread. Set 1 to cause Ovf_FixedCtr1 = 1. 442 /// 443 UINT32 Ovf_FixedCtr1:1; 444 /// 445 /// [Bit 34] Thread. Set 1 to cause Ovf_FixedCtr2 = 1. 446 /// 447 UINT32 Ovf_FixedCtr2:1; 448 UINT32 Reserved2:20; 449 /// 450 /// [Bit 55] Thread. Set 1 to cause Trace_ToPA_PMI = 1. 451 /// 452 UINT32 Trace_ToPA_PMI:1; 453 UINT32 Reserved3:2; 454 /// 455 /// [Bit 58] Thread. Set 1 to cause LBR_Frz = 1. 456 /// 457 UINT32 LBR_Frz:1; 458 /// 459 /// [Bit 59] Thread. Set 1 to cause CTR_Frz = 1. 460 /// 461 UINT32 CTR_Frz:1; 462 /// 463 /// [Bit 60] Thread. Set 1 to cause ASCI = 1. 464 /// 465 UINT32 ASCI:1; 466 /// 467 /// [Bit 61] Thread. Set 1 to cause Ovf_Uncore. 468 /// 469 UINT32 Ovf_Uncore:1; 470 /// 471 /// [Bit 62] Thread. Set 1 to cause Ovf_BufDSSAVE. 472 /// 473 UINT32 Ovf_BufDSSAVE:1; 474 UINT32 Reserved4:1; 475 } Bits; 476 /// 477 /// All bit fields as a 64-bit value 478 /// 479 UINT64 Uint64; 480 } MSR_SKYLAKE_IA32_PERF_GLOBAL_STATUS_SET_REGISTER; 481 482 483 /** 484 Thread. FrontEnd Precise Event Condition Select (R/W). 485 486 @param ECX MSR_SKYLAKE_PEBS_FRONTEND (0x000003F7) 487 @param EAX Lower 32-bits of MSR value. 488 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER. 489 @param EDX Upper 32-bits of MSR value. 490 Described by the type MSR_SKYLAKE_PEBS_FRONTEND_REGISTER. 491 492 <b>Example usage</b> 493 @code 494 MSR_SKYLAKE_PEBS_FRONTEND_REGISTER Msr; 495 496 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PEBS_FRONTEND); 497 AsmWriteMsr64 (MSR_SKYLAKE_PEBS_FRONTEND, Msr.Uint64); 498 @endcode 499 @note MSR_SKYLAKE_PEBS_FRONTEND is defined as MSR_PEBS_FRONTEND in SDM. 500 **/ 501 #define MSR_SKYLAKE_PEBS_FRONTEND 0x000003F7 502 503 /** 504 MSR information returned for MSR index #MSR_SKYLAKE_PEBS_FRONTEND 505 **/ 506 typedef union { 507 /// 508 /// Individual bit fields 509 /// 510 struct { 511 /// 512 /// [Bits 2:0] Event Code Select. 513 /// 514 UINT32 EventCodeSelect:3; 515 UINT32 Reserved1:1; 516 /// 517 /// [Bit 4] Event Code Select High. 518 /// 519 UINT32 EventCodeSelectHigh:1; 520 UINT32 Reserved2:3; 521 /// 522 /// [Bits 19:8] IDQ_Bubble_Length Specifier. 523 /// 524 UINT32 IDQ_Bubble_Length:12; 525 /// 526 /// [Bits 22:20] IDQ_Bubble_Width Specifier. 527 /// 528 UINT32 IDQ_Bubble_Width:3; 529 UINT32 Reserved3:9; 530 UINT32 Reserved4:32; 531 } Bits; 532 /// 533 /// All bit fields as a 32-bit value 534 /// 535 UINT32 Uint32; 536 /// 537 /// All bit fields as a 64-bit value 538 /// 539 UINT64 Uint64; 540 } MSR_SKYLAKE_PEBS_FRONTEND_REGISTER; 541 542 543 /** 544 Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL 545 Domains.". 546 547 @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639) 548 @param EAX Lower 32-bits of MSR value. 549 @param EDX Upper 32-bits of MSR value. 550 551 <b>Example usage</b> 552 @code 553 UINT64 Msr; 554 555 Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS); 556 @endcode 557 @note MSR_SKYLAKE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM. 558 **/ 559 #define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639 560 561 562 /** 563 Platform*. Platform Energy Counter. (R/O). This MSR is valid only if both 564 platform vendor hardware implementation and BIOS enablement support it. This 565 MSR will read 0 if not valid. 566 567 @param ECX MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER (0x0000064D) 568 @param EAX Lower 32-bits of MSR value. 569 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER. 570 @param EDX Upper 32-bits of MSR value. 571 Described by the type MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER. 572 573 <b>Example usage</b> 574 @code 575 MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER Msr; 576 577 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER); 578 @endcode 579 @note MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER is defined as MSR_PLATFORM_ENERGY_COUNTER in SDM. 580 **/ 581 #define MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 0x0000064D 582 583 /** 584 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER 585 **/ 586 typedef union { 587 /// 588 /// Individual bit fields 589 /// 590 struct { 591 /// 592 /// [Bits 31:0] Total energy consumed by all devices in the platform that 593 /// receive power from integrated power delivery mechanism, Included 594 /// platform devices are processor cores, SOC, memory, add-on or 595 /// peripheral devices that get powered directly from the platform power 596 /// delivery means. The energy units are specified in the 597 /// MSR_RAPL_POWER_UNIT.Enery_Status_Unit. 598 /// 599 UINT32 TotalEnergy:32; 600 UINT32 Reserved:32; 601 } Bits; 602 /// 603 /// All bit fields as a 32-bit value 604 /// 605 UINT32 Uint32; 606 /// 607 /// All bit fields as a 64-bit value 608 /// 609 UINT64 Uint64; 610 } MSR_SKYLAKE_PLATFORM_ENERGY_COUNTER_REGISTER; 611 612 613 /** 614 Thread. Productive Performance Count. (R/O). Hardware's view of workload 615 scalability. See Section 14.4.5.1. 616 617 @param ECX MSR_SKYLAKE_PPERF (0x0000064E) 618 @param EAX Lower 32-bits of MSR value. 619 @param EDX Upper 32-bits of MSR value. 620 621 <b>Example usage</b> 622 @code 623 UINT64 Msr; 624 625 Msr = AsmReadMsr64 (MSR_SKYLAKE_PPERF); 626 @endcode 627 @note MSR_SKYLAKE_PPERF is defined as MSR_PPERF in SDM. 628 **/ 629 #define MSR_SKYLAKE_PPERF 0x0000064E 630 631 632 /** 633 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency 634 refers to processor core frequency). 635 636 @param ECX MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS (0x0000064F) 637 @param EAX Lower 32-bits of MSR value. 638 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER. 639 @param EDX Upper 32-bits of MSR value. 640 Described by the type MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER. 641 642 <b>Example usage</b> 643 @code 644 MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER Msr; 645 646 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS); 647 AsmWriteMsr64 (MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS, Msr.Uint64); 648 @endcode 649 @note MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM. 650 **/ 651 #define MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 0x0000064F 652 653 /** 654 MSR information returned for MSR index #MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS 655 **/ 656 typedef union { 657 /// 658 /// Individual bit fields 659 /// 660 struct { 661 /// 662 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced below the 663 /// operating system request due to assertion of external PROCHOT. 664 /// 665 UINT32 PROCHOT_Status:1; 666 /// 667 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the 668 /// operating system request due to a thermal event. 669 /// 670 UINT32 ThermalStatus:1; 671 UINT32 Reserved1:2; 672 /// 673 /// [Bit 4] Residency State Regulation Status (R0) When set, frequency is 674 /// reduced below the operating system request due to residency state 675 /// regulation limit. 676 /// 677 UINT32 ResidencyStateRegulationStatus:1; 678 /// 679 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency 680 /// is reduced below the operating system request due to Running Average 681 /// Thermal Limit (RATL). 682 /// 683 UINT32 RunningAverageThermalLimitStatus:1; 684 /// 685 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced 686 /// below the operating system request due to a thermal alert from a 687 /// processor Voltage Regulator (VR). 688 /// 689 UINT32 VRThermAlertStatus:1; 690 /// 691 /// [Bit 7] VR Therm Design Current Status (R0) When set, frequency is 692 /// reduced below the operating system request due to VR thermal design 693 /// current limit. 694 /// 695 UINT32 VRThermDesignCurrentStatus:1; 696 /// 697 /// [Bit 8] Other Status (R0) When set, frequency is reduced below the 698 /// operating system request due to electrical or other constraints. 699 /// 700 UINT32 OtherStatus:1; 701 UINT32 Reserved2:1; 702 /// 703 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When 704 /// set, frequency is reduced below the operating system request due to 705 /// package/platform-level power limiting PL1. 706 /// 707 UINT32 PL1Status:1; 708 /// 709 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When 710 /// set, frequency is reduced below the operating system request due to 711 /// package/platform-level power limiting PL2/PL3. 712 /// 713 UINT32 PL2Status:1; 714 /// 715 /// [Bit 12] Max Turbo Limit Status (R0) When set, frequency is reduced 716 /// below the operating system request due to multi-core turbo limits. 717 /// 718 UINT32 MaxTurboLimitStatus:1; 719 /// 720 /// [Bit 13] Turbo Transition Attenuation Status (R0) When set, frequency 721 /// is reduced below the operating system request due to Turbo transition 722 /// attenuation. This prevents performance degradation due to frequent 723 /// operating ratio changes. 724 /// 725 UINT32 TurboTransitionAttenuationStatus:1; 726 UINT32 Reserved3:2; 727 /// 728 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 729 /// has asserted since the log bit was last cleared. This log bit will 730 /// remain set until cleared by software writing 0. 731 /// 732 UINT32 PROCHOT_Log:1; 733 /// 734 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 735 /// has asserted since the log bit was last cleared. This log bit will 736 /// remain set until cleared by software writing 0. 737 /// 738 UINT32 ThermalLog:1; 739 UINT32 Reserved4:2; 740 /// 741 /// [Bit 20] Residency State Regulation Log When set, indicates that the 742 /// Residency State Regulation Status bit has asserted since the log bit 743 /// was last cleared. This log bit will remain set until cleared by 744 /// software writing 0. 745 /// 746 UINT32 ResidencyStateRegulationLog:1; 747 /// 748 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that 749 /// the RATL Status bit has asserted since the log bit was last cleared. 750 /// This log bit will remain set until cleared by software writing 0. 751 /// 752 UINT32 RunningAverageThermalLimitLog:1; 753 /// 754 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 755 /// Alert Status bit has asserted since the log bit was last cleared. This 756 /// log bit will remain set until cleared by software writing 0. 757 /// 758 UINT32 VRThermAlertLog:1; 759 /// 760 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the 761 /// VR TDC Status bit has asserted since the log bit was last cleared. 762 /// This log bit will remain set until cleared by software writing 0. 763 /// 764 UINT32 VRThermalDesignCurrentLog:1; 765 /// 766 /// [Bit 24] Other Log When set, indicates that the Other Status bit has 767 /// asserted since the log bit was last cleared. This log bit will remain 768 /// set until cleared by software writing 0. 769 /// 770 UINT32 OtherLog:1; 771 UINT32 Reserved5:1; 772 /// 773 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, 774 /// indicates that the Package or Platform Level PL1 Power Limiting Status 775 /// bit has asserted since the log bit was last cleared. This log bit will 776 /// remain set until cleared by software writing 0. 777 /// 778 UINT32 PL1Log:1; 779 /// 780 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, 781 /// indicates that the Package or Platform Level PL2/PL3 Power Limiting 782 /// Status bit has asserted since the log bit was last cleared. This log 783 /// bit will remain set until cleared by software writing 0. 784 /// 785 UINT32 PL2Log:1; 786 /// 787 /// [Bit 28] Max Turbo Limit Log When set, indicates that the Max Turbo 788 /// Limit Status bit has asserted since the log bit was last cleared. This 789 /// log bit will remain set until cleared by software writing 0. 790 /// 791 UINT32 MaxTurboLimitLog:1; 792 /// 793 /// [Bit 29] Turbo Transition Attenuation Log When set, indicates that the 794 /// Turbo Transition Attenuation Status bit has asserted since the log bit 795 /// was last cleared. This log bit will remain set until cleared by 796 /// software writing 0. 797 /// 798 UINT32 TurboTransitionAttenuationLog:1; 799 UINT32 Reserved6:2; 800 UINT32 Reserved7:32; 801 } Bits; 802 /// 803 /// All bit fields as a 32-bit value 804 /// 805 UINT32 Uint32; 806 /// 807 /// All bit fields as a 64-bit value 808 /// 809 UINT64 Uint64; 810 } MSR_SKYLAKE_CORE_PERF_LIMIT_REASONS_REGISTER; 811 812 813 /** 814 Package. HDC Configuration (R/W).. 815 816 @param ECX MSR_SKYLAKE_PKG_HDC_CONFIG (0x00000652) 817 @param EAX Lower 32-bits of MSR value. 818 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER. 819 @param EDX Upper 32-bits of MSR value. 820 Described by the type MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER. 821 822 <b>Example usage</b> 823 @code 824 MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER Msr; 825 826 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG); 827 AsmWriteMsr64 (MSR_SKYLAKE_PKG_HDC_CONFIG, Msr.Uint64); 828 @endcode 829 @note MSR_SKYLAKE_PKG_HDC_CONFIG is defined as MSR_PKG_HDC_CONFIG in SDM. 830 **/ 831 #define MSR_SKYLAKE_PKG_HDC_CONFIG 0x00000652 832 833 /** 834 MSR information returned for MSR index #MSR_SKYLAKE_PKG_HDC_CONFIG 835 **/ 836 typedef union { 837 /// 838 /// Individual bit fields 839 /// 840 struct { 841 /// 842 /// [Bits 2:0] PKG_Cx_Monitor. Configures Package Cx state threshold for 843 /// MSR_PKG_HDC_DEEP_RESIDENCY. 844 /// 845 UINT32 PKG_Cx_Monitor:3; 846 UINT32 Reserved1:29; 847 UINT32 Reserved2:32; 848 } Bits; 849 /// 850 /// All bit fields as a 32-bit value 851 /// 852 UINT32 Uint32; 853 /// 854 /// All bit fields as a 64-bit value 855 /// 856 UINT64 Uint64; 857 } MSR_SKYLAKE_PKG_HDC_CONFIG_REGISTER; 858 859 860 /** 861 Core. Core HDC Idle Residency. (R/O). Core_Cx_Duty_Cycle_Cnt. 862 863 @param ECX MSR_SKYLAKE_CORE_HDC_RESIDENCY (0x00000653) 864 @param EAX Lower 32-bits of MSR value. 865 @param EDX Upper 32-bits of MSR value. 866 867 <b>Example usage</b> 868 @code 869 UINT64 Msr; 870 871 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_HDC_RESIDENCY); 872 @endcode 873 @note MSR_SKYLAKE_CORE_HDC_RESIDENCY is defined as MSR_CORE_HDC_RESIDENCY in SDM. 874 **/ 875 #define MSR_SKYLAKE_CORE_HDC_RESIDENCY 0x00000653 876 877 878 /** 879 Package. Accumulate the cycles the package was in C2 state and at least one 880 logical processor was in forced idle. (R/O). Pkg_C2_Duty_Cycle_Cnt. 881 882 @param ECX MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY (0x00000655) 883 @param EAX Lower 32-bits of MSR value. 884 @param EDX Upper 32-bits of MSR value. 885 886 <b>Example usage</b> 887 @code 888 UINT64 Msr; 889 890 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY); 891 @endcode 892 @note MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY is defined as MSR_PKG_HDC_SHALLOW_RESIDENCY in SDM. 893 **/ 894 #define MSR_SKYLAKE_PKG_HDC_SHALLOW_RESIDENCY 0x00000655 895 896 897 /** 898 Package. Package Cx HDC Idle Residency. (R/O). Pkg_Cx_Duty_Cycle_Cnt. 899 900 @param ECX MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY (0x00000656) 901 @param EAX Lower 32-bits of MSR value. 902 @param EDX Upper 32-bits of MSR value. 903 904 <b>Example usage</b> 905 @code 906 UINT64 Msr; 907 908 Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY); 909 @endcode 910 @note MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY is defined as MSR_PKG_HDC_DEEP_RESIDENCY in SDM. 911 **/ 912 #define MSR_SKYLAKE_PKG_HDC_DEEP_RESIDENCY 0x00000656 913 914 915 /** 916 Package. Core-count Weighted C0 Residency. (R/O). Increment at the same rate 917 as the TSC. The increment each cycle is weighted by the number of processor 918 cores in the package that reside in C0. If N cores are simultaneously in C0, 919 then each cycle the counter increments by N. 920 921 @param ECX MSR_SKYLAKE_WEIGHTED_CORE_C0 (0x00000658) 922 @param EAX Lower 32-bits of MSR value. 923 @param EDX Upper 32-bits of MSR value. 924 925 <b>Example usage</b> 926 @code 927 UINT64 Msr; 928 929 Msr = AsmReadMsr64 (MSR_SKYLAKE_WEIGHTED_CORE_C0); 930 @endcode 931 @note MSR_SKYLAKE_WEIGHTED_CORE_C0 is defined as MSR_WEIGHTED_CORE_C0 in SDM. 932 **/ 933 #define MSR_SKYLAKE_WEIGHTED_CORE_C0 0x00000658 934 935 936 /** 937 Package. Any Core C0 Residency. (R/O). Increment at the same rate as the 938 TSC. The increment each cycle is one if any processor core in the package is 939 in C0. 940 941 @param ECX MSR_SKYLAKE_ANY_CORE_C0 (0x00000659) 942 @param EAX Lower 32-bits of MSR value. 943 @param EDX Upper 32-bits of MSR value. 944 945 <b>Example usage</b> 946 @code 947 UINT64 Msr; 948 949 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_CORE_C0); 950 @endcode 951 @note MSR_SKYLAKE_ANY_CORE_C0 is defined as MSR_ANY_CORE_C0 in SDM. 952 **/ 953 #define MSR_SKYLAKE_ANY_CORE_C0 0x00000659 954 955 956 /** 957 Package. Any Graphics Engine C0 Residency. (R/O). Increment at the same rate 958 as the TSC. The increment each cycle is one if any processor graphic 959 device's compute engines are in C0. 960 961 @param ECX MSR_SKYLAKE_ANY_GFXE_C0 (0x0000065A) 962 @param EAX Lower 32-bits of MSR value. 963 @param EDX Upper 32-bits of MSR value. 964 965 <b>Example usage</b> 966 @code 967 UINT64 Msr; 968 969 Msr = AsmReadMsr64 (MSR_SKYLAKE_ANY_GFXE_C0); 970 @endcode 971 @note MSR_SKYLAKE_ANY_GFXE_C0 is defined as MSR_ANY_GFXE_C0 in SDM. 972 **/ 973 #define MSR_SKYLAKE_ANY_GFXE_C0 0x0000065A 974 975 976 /** 977 Package. Core and Graphics Engine Overlapped C0 Residency. (R/O). Increment 978 at the same rate as the TSC. The increment each cycle is one if at least one 979 compute engine of the processor graphics is in C0 and at least one processor 980 core in the package is also in C0. 981 982 @param ECX MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 (0x0000065B) 983 @param EAX Lower 32-bits of MSR value. 984 @param EDX Upper 32-bits of MSR value. 985 986 <b>Example usage</b> 987 @code 988 UINT64 Msr; 989 990 Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0); 991 @endcode 992 @note MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 is defined as MSR_CORE_GFXE_OVERLAP_C0 in SDM. 993 **/ 994 #define MSR_SKYLAKE_CORE_GFXE_OVERLAP_C0 0x0000065B 995 996 997 /** 998 Platform*. Platform Power Limit Control (R/W-L) Allows platform BIOS to 999 limit power consumption of the platform devices to the specified values. The 1000 Long Duration power consumption is specified via Platform_Power_Limit_1 and 1001 Platform_Power_Limit_1_Time. The Short Duration power consumption limit is 1002 specified via the Platform_Power_Limit_2 with duration chosen by the 1003 processor. The processor implements an exponential-weighted algorithm in the 1004 placement of the time windows. 1005 1006 @param ECX MSR_SKYLAKE_PLATFORM_POWER_LIMIT (0x0000065C) 1007 @param EAX Lower 32-bits of MSR value. 1008 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER. 1009 @param EDX Upper 32-bits of MSR value. 1010 Described by the type MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER. 1011 1012 <b>Example usage</b> 1013 @code 1014 MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER Msr; 1015 1016 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT); 1017 AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_POWER_LIMIT, Msr.Uint64); 1018 @endcode 1019 @note MSR_SKYLAKE_PLATFORM_POWER_LIMIT is defined as MSR_PLATFORM_POWER_LIMIT in SDM. 1020 **/ 1021 #define MSR_SKYLAKE_PLATFORM_POWER_LIMIT 0x0000065C 1022 1023 /** 1024 MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_POWER_LIMIT 1025 **/ 1026 typedef union { 1027 /// 1028 /// Individual bit fields 1029 /// 1030 struct { 1031 /// 1032 /// [Bits 14:0] Platform Power Limit #1. Average Power limit value which 1033 /// the platform must not exceed over a time window as specified by 1034 /// Power_Limit_1_TIME field. The default value is the Thermal Design 1035 /// Power (TDP) and varies with product skus. The unit is specified in 1036 /// MSR_RAPLPOWER_UNIT. 1037 /// 1038 UINT32 PlatformPowerLimit1:15; 1039 /// 1040 /// [Bit 15] Enable Platform Power Limit #1. When set, enables the 1041 /// processor to apply control policy such that the platform power does 1042 /// not exceed Platform Power limit #1 over the time window specified by 1043 /// Power Limit #1 Time Window. 1044 /// 1045 UINT32 EnablePlatformPowerLimit1:1; 1046 /// 1047 /// [Bit 16] Platform Clamping Limitation #1. When set, allows the 1048 /// processor to go below the OS requested P states in order to maintain 1049 /// the power below specified Platform Power Limit #1 value. This bit is 1050 /// writeable only when CPUID (EAX=6):EAX[4] is set. 1051 /// 1052 UINT32 PlatformClampingLimitation1:1; 1053 /// 1054 /// [Bits 23:17] Time Window for Platform Power Limit #1. Specifies the 1055 /// duration of the time window over which Platform Power Limit 1 value 1056 /// should be maintained for sustained long duration. This field is made 1057 /// up of two numbers from the following equation: Time Window = (float) 1058 /// ((1+(X/4))*(2^Y)), where: X. = POWER_LIMIT_1_TIME[23:22] Y. = 1059 /// POWER_LIMIT_1_TIME[21:17]. The maximum allowed value in this field is 1060 /// defined in MSR_PKG_POWER_INFO[PKG_MAX_WIN]. The default value is 0DH, 1061 /// The unit is specified in MSR_RAPLPOWER_UNIT[Time Unit]. 1062 /// 1063 UINT32 Time:7; 1064 UINT32 Reserved1:8; 1065 /// 1066 /// [Bits 46:32] Platform Power Limit #2. Average Power limit value which 1067 /// the platform must not exceed over the Short Duration time window 1068 /// chosen by the processor. The recommended default value is 1.25 times 1069 /// the Long Duration Power Limit (i.e. Platform Power Limit # 1). 1070 /// 1071 UINT32 PlatformPowerLimit2:15; 1072 /// 1073 /// [Bit 47] Enable Platform Power Limit #2. When set, enables the 1074 /// processor to apply control policy such that the platform power does 1075 /// not exceed Platform Power limit #2 over the Short Duration time window. 1076 /// 1077 UINT32 EnablePlatformPowerLimit2:1; 1078 /// 1079 /// [Bit 48] Platform Clamping Limitation #2. When set, allows the 1080 /// processor to go below the OS requested P states in order to maintain 1081 /// the power below specified Platform Power Limit #2 value. 1082 /// 1083 UINT32 PlatformClampingLimitation2:1; 1084 UINT32 Reserved2:14; 1085 /// 1086 /// [Bit 63] Lock. Setting this bit will lock all other bits of this MSR 1087 /// until system RESET. 1088 /// 1089 UINT32 Lock:1; 1090 } Bits; 1091 /// 1092 /// All bit fields as a 64-bit value 1093 /// 1094 UINT64 Uint64; 1095 } MSR_SKYLAKE_PLATFORM_POWER_LIMIT_REGISTER; 1096 1097 1098 /** 1099 Thread. Last Branch Record n From IP (R/W) One of 32 triplets of last 1100 branch record registers on the last branch record stack. This part of the 1101 stack contains pointers to the source instruction. See also: - Last Branch 1102 Record Stack TOS at 1C9H - Section 17.10. 1103 1104 @param ECX MSR_SKYLAKE_LASTBRANCH_n_FROM_IP 1105 @param EAX Lower 32-bits of MSR value. 1106 @param EDX Upper 32-bits of MSR value. 1107 1108 <b>Example usage</b> 1109 @code 1110 UINT64 Msr; 1111 1112 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP); 1113 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_FROM_IP, Msr); 1114 @endcode 1115 @note MSR_SKYLAKE_LASTBRANCH_16_FROM_IP is defined as MSR_LASTBRANCH_16_FROM_IP in SDM. 1116 MSR_SKYLAKE_LASTBRANCH_17_FROM_IP is defined as MSR_LASTBRANCH_17_FROM_IP in SDM. 1117 MSR_SKYLAKE_LASTBRANCH_18_FROM_IP is defined as MSR_LASTBRANCH_18_FROM_IP in SDM. 1118 MSR_SKYLAKE_LASTBRANCH_19_FROM_IP is defined as MSR_LASTBRANCH_19_FROM_IP in SDM. 1119 MSR_SKYLAKE_LASTBRANCH_20_FROM_IP is defined as MSR_LASTBRANCH_20_FROM_IP in SDM. 1120 MSR_SKYLAKE_LASTBRANCH_21_FROM_IP is defined as MSR_LASTBRANCH_21_FROM_IP in SDM. 1121 MSR_SKYLAKE_LASTBRANCH_22_FROM_IP is defined as MSR_LASTBRANCH_22_FROM_IP in SDM. 1122 MSR_SKYLAKE_LASTBRANCH_23_FROM_IP is defined as MSR_LASTBRANCH_23_FROM_IP in SDM. 1123 MSR_SKYLAKE_LASTBRANCH_24_FROM_IP is defined as MSR_LASTBRANCH_24_FROM_IP in SDM. 1124 MSR_SKYLAKE_LASTBRANCH_25_FROM_IP is defined as MSR_LASTBRANCH_25_FROM_IP in SDM. 1125 MSR_SKYLAKE_LASTBRANCH_26_FROM_IP is defined as MSR_LASTBRANCH_26_FROM_IP in SDM. 1126 MSR_SKYLAKE_LASTBRANCH_27_FROM_IP is defined as MSR_LASTBRANCH_27_FROM_IP in SDM. 1127 MSR_SKYLAKE_LASTBRANCH_28_FROM_IP is defined as MSR_LASTBRANCH_28_FROM_IP in SDM. 1128 MSR_SKYLAKE_LASTBRANCH_29_FROM_IP is defined as MSR_LASTBRANCH_29_FROM_IP in SDM. 1129 MSR_SKYLAKE_LASTBRANCH_30_FROM_IP is defined as MSR_LASTBRANCH_30_FROM_IP in SDM. 1130 MSR_SKYLAKE_LASTBRANCH_31_FROM_IP is defined as MSR_LASTBRANCH_31_FROM_IP in SDM. 1131 @{ 1132 **/ 1133 #define MSR_SKYLAKE_LASTBRANCH_16_FROM_IP 0x00000690 1134 #define MSR_SKYLAKE_LASTBRANCH_17_FROM_IP 0x00000691 1135 #define MSR_SKYLAKE_LASTBRANCH_18_FROM_IP 0x00000692 1136 #define MSR_SKYLAKE_LASTBRANCH_19_FROM_IP 0x00000693 1137 #define MSR_SKYLAKE_LASTBRANCH_20_FROM_IP 0x00000694 1138 #define MSR_SKYLAKE_LASTBRANCH_21_FROM_IP 0x00000695 1139 #define MSR_SKYLAKE_LASTBRANCH_22_FROM_IP 0x00000696 1140 #define MSR_SKYLAKE_LASTBRANCH_23_FROM_IP 0x00000697 1141 #define MSR_SKYLAKE_LASTBRANCH_24_FROM_IP 0x00000698 1142 #define MSR_SKYLAKE_LASTBRANCH_25_FROM_IP 0x00000699 1143 #define MSR_SKYLAKE_LASTBRANCH_26_FROM_IP 0x0000069A 1144 #define MSR_SKYLAKE_LASTBRANCH_27_FROM_IP 0x0000069B 1145 #define MSR_SKYLAKE_LASTBRANCH_28_FROM_IP 0x0000069C 1146 #define MSR_SKYLAKE_LASTBRANCH_29_FROM_IP 0x0000069D 1147 #define MSR_SKYLAKE_LASTBRANCH_30_FROM_IP 0x0000069E 1148 #define MSR_SKYLAKE_LASTBRANCH_31_FROM_IP 0x0000069F 1149 /// @} 1150 1151 1152 /** 1153 Package. Indicator of Frequency Clipping in the Processor Graphics (R/W) 1154 (frequency refers to processor graphics frequency). 1155 1156 @param ECX MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS (0x000006B0) 1157 @param EAX Lower 32-bits of MSR value. 1158 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. 1159 @param EDX Upper 32-bits of MSR value. 1160 Described by the type MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER. 1161 1162 <b>Example usage</b> 1163 @code 1164 MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER Msr; 1165 1166 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS); 1167 AsmWriteMsr64 (MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS, Msr.Uint64); 1168 @endcode 1169 @note MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS is defined as MSR_GRAPHICS_PERF_LIMIT_REASONS in SDM. 1170 **/ 1171 #define MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 0x000006B0 1172 1173 /** 1174 MSR information returned for MSR index 1175 #MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS 1176 **/ 1177 typedef union { 1178 /// 1179 /// Individual bit fields 1180 /// 1181 struct { 1182 /// 1183 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to 1184 /// assertion of external PROCHOT. 1185 /// 1186 UINT32 PROCHOT_Status:1; 1187 /// 1188 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a 1189 /// thermal event. 1190 /// 1191 UINT32 ThermalStatus:1; 1192 UINT32 Reserved1:3; 1193 /// 1194 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency 1195 /// is reduced due to running average thermal limit. 1196 /// 1197 UINT32 RunningAverageThermalLimitStatus:1; 1198 /// 1199 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due 1200 /// to a thermal alert from a processor Voltage Regulator. 1201 /// 1202 UINT32 VRThermAlertStatus:1; 1203 /// 1204 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is 1205 /// reduced due to VR TDC limit. 1206 /// 1207 UINT32 VRThermalDesignCurrentStatus:1; 1208 /// 1209 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to 1210 /// electrical or other constraints. 1211 /// 1212 UINT32 OtherStatus:1; 1213 UINT32 Reserved2:1; 1214 /// 1215 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When 1216 /// set, frequency is reduced due to package/platform-level power limiting 1217 /// PL1. 1218 /// 1219 UINT32 PL1Status:1; 1220 /// 1221 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When 1222 /// set, frequency is reduced due to package/platform-level power limiting 1223 /// PL2/PL3. 1224 /// 1225 UINT32 PL2Status:1; 1226 /// 1227 /// [Bit 12] Inefficient Operation Status (R0) When set, processor 1228 /// graphics frequency is operating below target frequency. 1229 /// 1230 UINT32 InefficientOperationStatus:1; 1231 UINT32 Reserved3:3; 1232 /// 1233 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 1234 /// has asserted since the log bit was last cleared. This log bit will 1235 /// remain set until cleared by software writing 0. 1236 /// 1237 UINT32 PROCHOT_Log:1; 1238 /// 1239 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 1240 /// has asserted since the log bit was last cleared. This log bit will 1241 /// remain set until cleared by software writing 0. 1242 /// 1243 UINT32 ThermalLog:1; 1244 UINT32 Reserved4:3; 1245 /// 1246 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that 1247 /// the RATL Status bit has asserted since the log bit was last cleared. 1248 /// This log bit will remain set until cleared by software writing 0. 1249 /// 1250 UINT32 RunningAverageThermalLimitLog:1; 1251 /// 1252 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 1253 /// Alert Status bit has asserted since the log bit was last cleared. This 1254 /// log bit will remain set until cleared by software writing 0. 1255 /// 1256 UINT32 VRThermAlertLog:1; 1257 /// 1258 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the 1259 /// VR Therm Alert Status bit has asserted since the log bit was last 1260 /// cleared. This log bit will remain set until cleared by software 1261 /// writing 0. 1262 /// 1263 UINT32 VRThermalDesignCurrentLog:1; 1264 /// 1265 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has 1266 /// asserted since the log bit was last cleared. This log bit will remain 1267 /// set until cleared by software writing 0. 1268 /// 1269 UINT32 OtherLog:1; 1270 UINT32 Reserved5:1; 1271 /// 1272 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, 1273 /// indicates that the Package/Platform Level PL1 Power Limiting Status 1274 /// bit has asserted since the log bit was last cleared. This log bit will 1275 /// remain set until cleared by software writing 0. 1276 /// 1277 UINT32 PL1Log:1; 1278 /// 1279 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, 1280 /// indicates that the Package/Platform Level PL2 Power Limiting Status 1281 /// bit has asserted since the log bit was last cleared. This log bit will 1282 /// remain set until cleared by software writing 0. 1283 /// 1284 UINT32 PL2Log:1; 1285 /// 1286 /// [Bit 28] Inefficient Operation Log When set, indicates that the 1287 /// Inefficient Operation Status bit has asserted since the log bit was 1288 /// last cleared. This log bit will remain set until cleared by software 1289 /// writing 0. 1290 /// 1291 UINT32 InefficientOperationLog:1; 1292 UINT32 Reserved6:3; 1293 UINT32 Reserved7:32; 1294 } Bits; 1295 /// 1296 /// All bit fields as a 32-bit value 1297 /// 1298 UINT32 Uint32; 1299 /// 1300 /// All bit fields as a 64-bit value 1301 /// 1302 UINT64 Uint64; 1303 } MSR_SKYLAKE_GRAPHICS_PERF_LIMIT_REASONS_REGISTER; 1304 1305 1306 /** 1307 Package. Indicator of Frequency Clipping in the Ring Interconnect (R/W) 1308 (frequency refers to ring interconnect in the uncore). 1309 1310 @param ECX MSR_SKYLAKE_RING_PERF_LIMIT_REASONS (0x000006B1) 1311 @param EAX Lower 32-bits of MSR value. 1312 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER. 1313 @param EDX Upper 32-bits of MSR value. 1314 Described by the type MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER. 1315 1316 <b>Example usage</b> 1317 @code 1318 MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER Msr; 1319 1320 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS); 1321 AsmWriteMsr64 (MSR_SKYLAKE_RING_PERF_LIMIT_REASONS, Msr.Uint64); 1322 @endcode 1323 @note MSR_SKYLAKE_RING_PERF_LIMIT_REASONS is defined as MSR_RING_PERF_LIMIT_REASONS in SDM. 1324 **/ 1325 #define MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 0x000006B1 1326 1327 /** 1328 MSR information returned for MSR index #MSR_SKYLAKE_RING_PERF_LIMIT_REASONS 1329 **/ 1330 typedef union { 1331 /// 1332 /// Individual bit fields 1333 /// 1334 struct { 1335 /// 1336 /// [Bit 0] PROCHOT Status (R0) When set, frequency is reduced due to 1337 /// assertion of external PROCHOT. 1338 /// 1339 UINT32 PROCHOT_Status:1; 1340 /// 1341 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced due to a 1342 /// thermal event. 1343 /// 1344 UINT32 ThermalStatus:1; 1345 UINT32 Reserved1:3; 1346 /// 1347 /// [Bit 5] Running Average Thermal Limit Status (R0) When set, frequency 1348 /// is reduced due to running average thermal limit. 1349 /// 1350 UINT32 RunningAverageThermalLimitStatus:1; 1351 /// 1352 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced due 1353 /// to a thermal alert from a processor Voltage Regulator. 1354 /// 1355 UINT32 VRThermAlertStatus:1; 1356 /// 1357 /// [Bit 7] VR Thermal Design Current Status (R0) When set, frequency is 1358 /// reduced due to VR TDC limit. 1359 /// 1360 UINT32 VRThermalDesignCurrentStatus:1; 1361 /// 1362 /// [Bit 8] Other Status (R0) When set, frequency is reduced due to 1363 /// electrical or other constraints. 1364 /// 1365 UINT32 OtherStatus:1; 1366 UINT32 Reserved2:1; 1367 /// 1368 /// [Bit 10] Package/Platform-Level Power Limiting PL1 Status (R0) When 1369 /// set, frequency is reduced due to package/Platform-level power limiting 1370 /// PL1. 1371 /// 1372 UINT32 PL1Status:1; 1373 /// 1374 /// [Bit 11] Package/Platform-Level PL2 Power Limiting Status (R0) When 1375 /// set, frequency is reduced due to package/Platform-level power limiting 1376 /// PL2/PL3. 1377 /// 1378 UINT32 PL2Status:1; 1379 UINT32 Reserved3:4; 1380 /// 1381 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit 1382 /// has asserted since the log bit was last cleared. This log bit will 1383 /// remain set until cleared by software writing 0. 1384 /// 1385 UINT32 PROCHOT_Log:1; 1386 /// 1387 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit 1388 /// has asserted since the log bit was last cleared. This log bit will 1389 /// remain set until cleared by software writing 0. 1390 /// 1391 UINT32 ThermalLog:1; 1392 UINT32 Reserved4:3; 1393 /// 1394 /// [Bit 21] Running Average Thermal Limit Log When set, indicates that 1395 /// the RATL Status bit has asserted since the log bit was last cleared. 1396 /// This log bit will remain set until cleared by software writing 0. 1397 /// 1398 UINT32 RunningAverageThermalLimitLog:1; 1399 /// 1400 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm 1401 /// Alert Status bit has asserted since the log bit was last cleared. This 1402 /// log bit will remain set until cleared by software writing 0. 1403 /// 1404 UINT32 VRThermAlertLog:1; 1405 /// 1406 /// [Bit 23] VR Thermal Design Current Log When set, indicates that the 1407 /// VR Therm Alert Status bit has asserted since the log bit was last 1408 /// cleared. This log bit will remain set until cleared by software 1409 /// writing 0. 1410 /// 1411 UINT32 VRThermalDesignCurrentLog:1; 1412 /// 1413 /// [Bit 24] Other Log When set, indicates that the OTHER Status bit has 1414 /// asserted since the log bit was last cleared. This log bit will remain 1415 /// set until cleared by software writing 0. 1416 /// 1417 UINT32 OtherLog:1; 1418 UINT32 Reserved5:1; 1419 /// 1420 /// [Bit 26] Package/Platform-Level PL1 Power Limiting Log When set, 1421 /// indicates that the Package/Platform Level PL1 Power Limiting Status 1422 /// bit has asserted since the log bit was last cleared. This log bit will 1423 /// remain set until cleared by software writing 0. 1424 /// 1425 UINT32 PL1Log:1; 1426 /// 1427 /// [Bit 27] Package/Platform-Level PL2 Power Limiting Log When set, 1428 /// indicates that the Package/Platform Level PL2 Power Limiting Status 1429 /// bit has asserted since the log bit was last cleared. This log bit will 1430 /// remain set until cleared by software writing 0. 1431 /// 1432 UINT32 PL2Log:1; 1433 UINT32 Reserved6:4; 1434 UINT32 Reserved7:32; 1435 } Bits; 1436 /// 1437 /// All bit fields as a 32-bit value 1438 /// 1439 UINT32 Uint32; 1440 /// 1441 /// All bit fields as a 64-bit value 1442 /// 1443 UINT64 Uint64; 1444 } MSR_SKYLAKE_RING_PERF_LIMIT_REASONS_REGISTER; 1445 1446 1447 /** 1448 Thread. Last Branch Record n To IP (R/W) One of 32 triplets of last branch 1449 record registers on the last branch record stack. This part of the stack 1450 contains pointers to the destination instruction. See also: - Last Branch 1451 Record Stack TOS at 1C9H - Section 17.10. 1452 1453 @param ECX MSR_SKYLAKE_LASTBRANCH_n_TO_IP 1454 @param EAX Lower 32-bits of MSR value. 1455 @param EDX Upper 32-bits of MSR value. 1456 1457 <b>Example usage</b> 1458 @code 1459 UINT64 Msr; 1460 1461 Msr = AsmReadMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP); 1462 AsmWriteMsr64 (MSR_SKYLAKE_LASTBRANCH_16_TO_IP, Msr); 1463 @endcode 1464 @note MSR_SKYLAKE_LASTBRANCH_16_TO_IP is defined as MSR_LASTBRANCH_16_TO_IP in SDM. 1465 MSR_SKYLAKE_LASTBRANCH_17_TO_IP is defined as MSR_LASTBRANCH_17_TO_IP in SDM. 1466 MSR_SKYLAKE_LASTBRANCH_18_TO_IP is defined as MSR_LASTBRANCH_18_TO_IP in SDM. 1467 MSR_SKYLAKE_LASTBRANCH_19_TO_IP is defined as MSR_LASTBRANCH_19_TO_IP in SDM. 1468 MSR_SKYLAKE_LASTBRANCH_20_TO_IP is defined as MSR_LASTBRANCH_20_TO_IP in SDM. 1469 MSR_SKYLAKE_LASTBRANCH_21_TO_IP is defined as MSR_LASTBRANCH_21_TO_IP in SDM. 1470 MSR_SKYLAKE_LASTBRANCH_22_TO_IP is defined as MSR_LASTBRANCH_22_TO_IP in SDM. 1471 MSR_SKYLAKE_LASTBRANCH_23_TO_IP is defined as MSR_LASTBRANCH_23_TO_IP in SDM. 1472 MSR_SKYLAKE_LASTBRANCH_24_TO_IP is defined as MSR_LASTBRANCH_24_TO_IP in SDM. 1473 MSR_SKYLAKE_LASTBRANCH_25_TO_IP is defined as MSR_LASTBRANCH_25_TO_IP in SDM. 1474 MSR_SKYLAKE_LASTBRANCH_26_TO_IP is defined as MSR_LASTBRANCH_26_TO_IP in SDM. 1475 MSR_SKYLAKE_LASTBRANCH_27_TO_IP is defined as MSR_LASTBRANCH_27_TO_IP in SDM. 1476 MSR_SKYLAKE_LASTBRANCH_28_TO_IP is defined as MSR_LASTBRANCH_28_TO_IP in SDM. 1477 MSR_SKYLAKE_LASTBRANCH_29_TO_IP is defined as MSR_LASTBRANCH_29_TO_IP in SDM. 1478 MSR_SKYLAKE_LASTBRANCH_30_TO_IP is defined as MSR_LASTBRANCH_30_TO_IP in SDM. 1479 MSR_SKYLAKE_LASTBRANCH_31_TO_IP is defined as MSR_LASTBRANCH_31_TO_IP in SDM. 1480 @{ 1481 **/ 1482 #define MSR_SKYLAKE_LASTBRANCH_16_TO_IP 0x000006D0 1483 #define MSR_SKYLAKE_LASTBRANCH_17_TO_IP 0x000006D1 1484 #define MSR_SKYLAKE_LASTBRANCH_18_TO_IP 0x000006D2 1485 #define MSR_SKYLAKE_LASTBRANCH_19_TO_IP 0x000006D3 1486 #define MSR_SKYLAKE_LASTBRANCH_20_TO_IP 0x000006D4 1487 #define MSR_SKYLAKE_LASTBRANCH_21_TO_IP 0x000006D5 1488 #define MSR_SKYLAKE_LASTBRANCH_22_TO_IP 0x000006D6 1489 #define MSR_SKYLAKE_LASTBRANCH_23_TO_IP 0x000006D7 1490 #define MSR_SKYLAKE_LASTBRANCH_24_TO_IP 0x000006D8 1491 #define MSR_SKYLAKE_LASTBRANCH_25_TO_IP 0x000006D9 1492 #define MSR_SKYLAKE_LASTBRANCH_26_TO_IP 0x000006DA 1493 #define MSR_SKYLAKE_LASTBRANCH_27_TO_IP 0x000006DB 1494 #define MSR_SKYLAKE_LASTBRANCH_28_TO_IP 0x000006DC 1495 #define MSR_SKYLAKE_LASTBRANCH_29_TO_IP 0x000006DD 1496 #define MSR_SKYLAKE_LASTBRANCH_30_TO_IP 0x000006DE 1497 #define MSR_SKYLAKE_LASTBRANCH_31_TO_IP 0x000006DF 1498 /// @} 1499 1500 1501 /** 1502 Thread. Last Branch Record n Additional Information (R/W) One of 32 triplet 1503 of last branch record registers on the last branch record stack. This part 1504 of the stack contains flag, TSX-related and elapsed cycle information. See 1505 also: - Last Branch Record Stack TOS at 1C9H - Section 17.7.1, "LBR 1506 Stack.". 1507 1508 @param ECX MSR_SKYLAKE_LBR_INFO_n 1509 @param EAX Lower 32-bits of MSR value. 1510 @param EDX Upper 32-bits of MSR value. 1511 1512 <b>Example usage</b> 1513 @code 1514 UINT64 Msr; 1515 1516 Msr = AsmReadMsr64 (MSR_SKYLAKE_LBR_INFO_0); 1517 AsmWriteMsr64 (MSR_SKYLAKE_LBR_INFO_0, Msr); 1518 @endcode 1519 @note MSR_SKYLAKE_LBR_INFO_0 is defined as MSR_LBR_INFO_0 in SDM. 1520 MSR_SKYLAKE_LBR_INFO_1 is defined as MSR_LBR_INFO_1 in SDM. 1521 MSR_SKYLAKE_LBR_INFO_2 is defined as MSR_LBR_INFO_2 in SDM. 1522 MSR_SKYLAKE_LBR_INFO_3 is defined as MSR_LBR_INFO_3 in SDM. 1523 MSR_SKYLAKE_LBR_INFO_4 is defined as MSR_LBR_INFO_4 in SDM. 1524 MSR_SKYLAKE_LBR_INFO_5 is defined as MSR_LBR_INFO_5 in SDM. 1525 MSR_SKYLAKE_LBR_INFO_6 is defined as MSR_LBR_INFO_6 in SDM. 1526 MSR_SKYLAKE_LBR_INFO_7 is defined as MSR_LBR_INFO_7 in SDM. 1527 MSR_SKYLAKE_LBR_INFO_8 is defined as MSR_LBR_INFO_8 in SDM. 1528 MSR_SKYLAKE_LBR_INFO_9 is defined as MSR_LBR_INFO_9 in SDM. 1529 MSR_SKYLAKE_LBR_INFO_10 is defined as MSR_LBR_INFO_10 in SDM. 1530 MSR_SKYLAKE_LBR_INFO_11 is defined as MSR_LBR_INFO_11 in SDM. 1531 MSR_SKYLAKE_LBR_INFO_12 is defined as MSR_LBR_INFO_12 in SDM. 1532 MSR_SKYLAKE_LBR_INFO_13 is defined as MSR_LBR_INFO_13 in SDM. 1533 MSR_SKYLAKE_LBR_INFO_14 is defined as MSR_LBR_INFO_14 in SDM. 1534 MSR_SKYLAKE_LBR_INFO_15 is defined as MSR_LBR_INFO_15 in SDM. 1535 MSR_SKYLAKE_LBR_INFO_16 is defined as MSR_LBR_INFO_16 in SDM. 1536 MSR_SKYLAKE_LBR_INFO_17 is defined as MSR_LBR_INFO_17 in SDM. 1537 MSR_SKYLAKE_LBR_INFO_18 is defined as MSR_LBR_INFO_18 in SDM. 1538 MSR_SKYLAKE_LBR_INFO_19 is defined as MSR_LBR_INFO_19 in SDM. 1539 MSR_SKYLAKE_LBR_INFO_20 is defined as MSR_LBR_INFO_20 in SDM. 1540 MSR_SKYLAKE_LBR_INFO_21 is defined as MSR_LBR_INFO_21 in SDM. 1541 MSR_SKYLAKE_LBR_INFO_22 is defined as MSR_LBR_INFO_22 in SDM. 1542 MSR_SKYLAKE_LBR_INFO_23 is defined as MSR_LBR_INFO_23 in SDM. 1543 MSR_SKYLAKE_LBR_INFO_24 is defined as MSR_LBR_INFO_24 in SDM. 1544 MSR_SKYLAKE_LBR_INFO_25 is defined as MSR_LBR_INFO_25 in SDM. 1545 MSR_SKYLAKE_LBR_INFO_26 is defined as MSR_LBR_INFO_26 in SDM. 1546 MSR_SKYLAKE_LBR_INFO_27 is defined as MSR_LBR_INFO_27 in SDM. 1547 MSR_SKYLAKE_LBR_INFO_28 is defined as MSR_LBR_INFO_28 in SDM. 1548 MSR_SKYLAKE_LBR_INFO_29 is defined as MSR_LBR_INFO_29 in SDM. 1549 MSR_SKYLAKE_LBR_INFO_30 is defined as MSR_LBR_INFO_30 in SDM. 1550 MSR_SKYLAKE_LBR_INFO_31 is defined as MSR_LBR_INFO_31 in SDM. 1551 @{ 1552 **/ 1553 #define MSR_SKYLAKE_LBR_INFO_0 0x00000DC0 1554 #define MSR_SKYLAKE_LBR_INFO_1 0x00000DC1 1555 #define MSR_SKYLAKE_LBR_INFO_2 0x00000DC2 1556 #define MSR_SKYLAKE_LBR_INFO_3 0x00000DC3 1557 #define MSR_SKYLAKE_LBR_INFO_4 0x00000DC4 1558 #define MSR_SKYLAKE_LBR_INFO_5 0x00000DC5 1559 #define MSR_SKYLAKE_LBR_INFO_6 0x00000DC6 1560 #define MSR_SKYLAKE_LBR_INFO_7 0x00000DC7 1561 #define MSR_SKYLAKE_LBR_INFO_8 0x00000DC8 1562 #define MSR_SKYLAKE_LBR_INFO_9 0x00000DC9 1563 #define MSR_SKYLAKE_LBR_INFO_10 0x00000DCA 1564 #define MSR_SKYLAKE_LBR_INFO_11 0x00000DCB 1565 #define MSR_SKYLAKE_LBR_INFO_12 0x00000DCC 1566 #define MSR_SKYLAKE_LBR_INFO_13 0x00000DCD 1567 #define MSR_SKYLAKE_LBR_INFO_14 0x00000DCE 1568 #define MSR_SKYLAKE_LBR_INFO_15 0x00000DCF 1569 #define MSR_SKYLAKE_LBR_INFO_16 0x00000DD0 1570 #define MSR_SKYLAKE_LBR_INFO_17 0x00000DD1 1571 #define MSR_SKYLAKE_LBR_INFO_18 0x00000DD2 1572 #define MSR_SKYLAKE_LBR_INFO_19 0x00000DD3 1573 #define MSR_SKYLAKE_LBR_INFO_20 0x00000DD4 1574 #define MSR_SKYLAKE_LBR_INFO_21 0x00000DD5 1575 #define MSR_SKYLAKE_LBR_INFO_22 0x00000DD6 1576 #define MSR_SKYLAKE_LBR_INFO_23 0x00000DD7 1577 #define MSR_SKYLAKE_LBR_INFO_24 0x00000DD8 1578 #define MSR_SKYLAKE_LBR_INFO_25 0x00000DD9 1579 #define MSR_SKYLAKE_LBR_INFO_26 0x00000DDA 1580 #define MSR_SKYLAKE_LBR_INFO_27 0x00000DDB 1581 #define MSR_SKYLAKE_LBR_INFO_28 0x00000DDC 1582 #define MSR_SKYLAKE_LBR_INFO_29 0x00000DDD 1583 #define MSR_SKYLAKE_LBR_INFO_30 0x00000DDE 1584 #define MSR_SKYLAKE_LBR_INFO_31 0x00000DDF 1585 /// @} 1586 1587 1588 /** 1589 Package. Uncore fixed counter control (R/W). 1590 1591 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTRL (0x00000394) 1592 @param EAX Lower 32-bits of MSR value. 1593 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER. 1594 @param EDX Upper 32-bits of MSR value. 1595 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER. 1596 1597 <b>Example usage</b> 1598 @code 1599 MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER Msr; 1600 1601 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL); 1602 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTRL, Msr.Uint64); 1603 @endcode 1604 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM. 1605 **/ 1606 #define MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 0x00000394 1607 1608 /** 1609 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTRL 1610 **/ 1611 typedef union { 1612 /// 1613 /// Individual bit fields 1614 /// 1615 struct { 1616 UINT32 Reserved1:20; 1617 /// 1618 /// [Bit 20] Enable overflow propagation. 1619 /// 1620 UINT32 EnableOverflow:1; 1621 UINT32 Reserved2:1; 1622 /// 1623 /// [Bit 22] Enable counting. 1624 /// 1625 UINT32 EnableCounting:1; 1626 UINT32 Reserved3:9; 1627 UINT32 Reserved4:32; 1628 } Bits; 1629 /// 1630 /// All bit fields as a 32-bit value 1631 /// 1632 UINT32 Uint32; 1633 /// 1634 /// All bit fields as a 64-bit value 1635 /// 1636 UINT64 Uint64; 1637 } MSR_SKYLAKE_UNC_PERF_FIXED_CTRL_REGISTER; 1638 1639 1640 /** 1641 Package. Uncore fixed counter. 1642 1643 @param ECX MSR_SKYLAKE_UNC_PERF_FIXED_CTR (0x00000395) 1644 @param EAX Lower 32-bits of MSR value. 1645 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER. 1646 @param EDX Upper 32-bits of MSR value. 1647 Described by the type MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER. 1648 1649 <b>Example usage</b> 1650 @code 1651 MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER Msr; 1652 1653 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR); 1654 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_FIXED_CTR, Msr.Uint64); 1655 @endcode 1656 @note MSR_SKYLAKE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM. 1657 **/ 1658 #define MSR_SKYLAKE_UNC_PERF_FIXED_CTR 0x00000395 1659 1660 /** 1661 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_FIXED_CTR 1662 **/ 1663 typedef union { 1664 /// 1665 /// Individual bit fields 1666 /// 1667 struct { 1668 /// 1669 /// [Bits 31:0] Current count. 1670 /// 1671 UINT32 CurrentCount:32; 1672 /// 1673 /// [Bits 43:32] Current count. 1674 /// 1675 UINT32 CurrentCountHi:12; 1676 UINT32 Reserved:20; 1677 } Bits; 1678 /// 1679 /// All bit fields as a 64-bit value 1680 /// 1681 UINT64 Uint64; 1682 } MSR_SKYLAKE_UNC_PERF_FIXED_CTR_REGISTER; 1683 1684 1685 /** 1686 Package. Uncore C-Box configuration information (R/O). 1687 1688 @param ECX MSR_SKYLAKE_UNC_CBO_CONFIG (0x00000396) 1689 @param EAX Lower 32-bits of MSR value. 1690 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER. 1691 @param EDX Upper 32-bits of MSR value. 1692 Described by the type MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER. 1693 1694 <b>Example usage</b> 1695 @code 1696 MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER Msr; 1697 1698 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_CONFIG); 1699 @endcode 1700 @note MSR_SKYLAKE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM. 1701 **/ 1702 #define MSR_SKYLAKE_UNC_CBO_CONFIG 0x00000396 1703 1704 /** 1705 MSR information returned for MSR index #MSR_SKYLAKE_UNC_CBO_CONFIG 1706 **/ 1707 typedef union { 1708 /// 1709 /// Individual bit fields 1710 /// 1711 struct { 1712 /// 1713 /// [Bits 3:0] Specifies the number of C-Box units with programmable 1714 /// counters (including processor cores and processor graphics),. 1715 /// 1716 UINT32 CBox:4; 1717 UINT32 Reserved1:28; 1718 UINT32 Reserved2:32; 1719 } Bits; 1720 /// 1721 /// All bit fields as a 32-bit value 1722 /// 1723 UINT32 Uint32; 1724 /// 1725 /// All bit fields as a 64-bit value 1726 /// 1727 UINT64 Uint64; 1728 } MSR_SKYLAKE_UNC_CBO_CONFIG_REGISTER; 1729 1730 1731 /** 1732 Package. Uncore Arb unit, performance counter 0. 1733 1734 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR0 (0x000003B0) 1735 @param EAX Lower 32-bits of MSR value. 1736 @param EDX Upper 32-bits of MSR value. 1737 1738 <b>Example usage</b> 1739 @code 1740 UINT64 Msr; 1741 1742 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0); 1743 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR0, Msr); 1744 @endcode 1745 @note MSR_SKYLAKE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM. 1746 **/ 1747 #define MSR_SKYLAKE_UNC_ARB_PERFCTR0 0x000003B0 1748 1749 1750 /** 1751 Package. Uncore Arb unit, performance counter 1. 1752 1753 @param ECX MSR_SKYLAKE_UNC_ARB_PERFCTR1 (0x000003B1) 1754 @param EAX Lower 32-bits of MSR value. 1755 @param EDX Upper 32-bits of MSR value. 1756 1757 <b>Example usage</b> 1758 @code 1759 UINT64 Msr; 1760 1761 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1); 1762 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFCTR1, Msr); 1763 @endcode 1764 @note MSR_SKYLAKE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM. 1765 **/ 1766 #define MSR_SKYLAKE_UNC_ARB_PERFCTR1 0x000003B1 1767 1768 1769 /** 1770 Package. Uncore Arb unit, counter 0 event select MSR. 1771 1772 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 (0x000003B2) 1773 @param EAX Lower 32-bits of MSR value. 1774 @param EDX Upper 32-bits of MSR value. 1775 1776 <b>Example usage</b> 1777 @code 1778 UINT64 Msr; 1779 1780 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0); 1781 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0, Msr); 1782 @endcode 1783 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM. 1784 **/ 1785 #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL0 0x000003B2 1786 1787 1788 /** 1789 Package. Uncore Arb unit, counter 1 event select MSR. 1790 1791 @param ECX MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 (0x000003B3) 1792 @param EAX Lower 32-bits of MSR value. 1793 @param EDX Upper 32-bits of MSR value. 1794 1795 <b>Example usage</b> 1796 @code 1797 UINT64 Msr; 1798 1799 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1); 1800 AsmWriteMsr64 (MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1, Msr); 1801 @endcode 1802 @note MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 is defined as MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 in SDM. 1803 **/ 1804 #define MSR_SKYLAKE_UNC_ARB_PERFEVTSEL1 0x000003B3 1805 1806 1807 /** 1808 Package. Uncore C-Box 0, counter 0 event select MSR. 1809 1810 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 (0x00000700) 1811 @param EAX Lower 32-bits of MSR value. 1812 @param EDX Upper 32-bits of MSR value. 1813 1814 <b>Example usage</b> 1815 @code 1816 UINT64 Msr; 1817 1818 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0); 1819 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0, Msr); 1820 @endcode 1821 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM. 1822 **/ 1823 #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL0 0x00000700 1824 1825 1826 /** 1827 Package. Uncore C-Box 0, counter 1 event select MSR. 1828 1829 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 (0x00000701) 1830 @param EAX Lower 32-bits of MSR value. 1831 @param EDX Upper 32-bits of MSR value. 1832 1833 <b>Example usage</b> 1834 @code 1835 UINT64 Msr; 1836 1837 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1); 1838 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1, Msr); 1839 @endcode 1840 @note MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM. 1841 **/ 1842 #define MSR_SKYLAKE_UNC_CBO_0_PERFEVTSEL1 0x00000701 1843 1844 1845 /** 1846 Package. Uncore C-Box 0, performance counter 0. 1847 1848 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 (0x00000706) 1849 @param EAX Lower 32-bits of MSR value. 1850 @param EDX Upper 32-bits of MSR value. 1851 1852 <b>Example usage</b> 1853 @code 1854 UINT64 Msr; 1855 1856 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0); 1857 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR0, Msr); 1858 @endcode 1859 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM. 1860 **/ 1861 #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR0 0x00000706 1862 1863 1864 /** 1865 Package. Uncore C-Box 0, performance counter 1. 1866 1867 @param ECX MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 (0x00000707) 1868 @param EAX Lower 32-bits of MSR value. 1869 @param EDX Upper 32-bits of MSR value. 1870 1871 <b>Example usage</b> 1872 @code 1873 UINT64 Msr; 1874 1875 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1); 1876 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_0_PERFCTR1, Msr); 1877 @endcode 1878 @note MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM. 1879 **/ 1880 #define MSR_SKYLAKE_UNC_CBO_0_PERFCTR1 0x00000707 1881 1882 1883 /** 1884 Package. Uncore C-Box 1, counter 0 event select MSR. 1885 1886 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 (0x00000710) 1887 @param EAX Lower 32-bits of MSR value. 1888 @param EDX Upper 32-bits of MSR value. 1889 1890 <b>Example usage</b> 1891 @code 1892 UINT64 Msr; 1893 1894 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0); 1895 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0, Msr); 1896 @endcode 1897 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM. 1898 **/ 1899 #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL0 0x00000710 1900 1901 1902 /** 1903 Package. Uncore C-Box 1, counter 1 event select MSR. 1904 1905 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 (0x00000711) 1906 @param EAX Lower 32-bits of MSR value. 1907 @param EDX Upper 32-bits of MSR value. 1908 1909 <b>Example usage</b> 1910 @code 1911 UINT64 Msr; 1912 1913 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1); 1914 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1, Msr); 1915 @endcode 1916 @note MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM. 1917 **/ 1918 #define MSR_SKYLAKE_UNC_CBO_1_PERFEVTSEL1 0x00000711 1919 1920 1921 /** 1922 Package. Uncore C-Box 1, performance counter 0. 1923 1924 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 (0x00000716) 1925 @param EAX Lower 32-bits of MSR value. 1926 @param EDX Upper 32-bits of MSR value. 1927 1928 <b>Example usage</b> 1929 @code 1930 UINT64 Msr; 1931 1932 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0); 1933 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR0, Msr); 1934 @endcode 1935 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM. 1936 **/ 1937 #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR0 0x00000716 1938 1939 1940 /** 1941 Package. Uncore C-Box 1, performance counter 1. 1942 1943 @param ECX MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 (0x00000717) 1944 @param EAX Lower 32-bits of MSR value. 1945 @param EDX Upper 32-bits of MSR value. 1946 1947 <b>Example usage</b> 1948 @code 1949 UINT64 Msr; 1950 1951 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1); 1952 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_1_PERFCTR1, Msr); 1953 @endcode 1954 @note MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM. 1955 **/ 1956 #define MSR_SKYLAKE_UNC_CBO_1_PERFCTR1 0x00000717 1957 1958 1959 /** 1960 Package. Uncore C-Box 2, counter 0 event select MSR. 1961 1962 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 (0x00000720) 1963 @param EAX Lower 32-bits of MSR value. 1964 @param EDX Upper 32-bits of MSR value. 1965 1966 <b>Example usage</b> 1967 @code 1968 UINT64 Msr; 1969 1970 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0); 1971 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0, Msr); 1972 @endcode 1973 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM. 1974 **/ 1975 #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL0 0x00000720 1976 1977 1978 /** 1979 Package. Uncore C-Box 2, counter 1 event select MSR. 1980 1981 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 (0x00000721) 1982 @param EAX Lower 32-bits of MSR value. 1983 @param EDX Upper 32-bits of MSR value. 1984 1985 <b>Example usage</b> 1986 @code 1987 UINT64 Msr; 1988 1989 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1); 1990 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1, Msr); 1991 @endcode 1992 @note MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM. 1993 **/ 1994 #define MSR_SKYLAKE_UNC_CBO_2_PERFEVTSEL1 0x00000721 1995 1996 1997 /** 1998 Package. Uncore C-Box 2, performance counter 0. 1999 2000 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 (0x00000726) 2001 @param EAX Lower 32-bits of MSR value. 2002 @param EDX Upper 32-bits of MSR value. 2003 2004 <b>Example usage</b> 2005 @code 2006 UINT64 Msr; 2007 2008 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0); 2009 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR0, Msr); 2010 @endcode 2011 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM. 2012 **/ 2013 #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR0 0x00000726 2014 2015 2016 /** 2017 Package. Uncore C-Box 2, performance counter 1. 2018 2019 @param ECX MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 (0x00000727) 2020 @param EAX Lower 32-bits of MSR value. 2021 @param EDX Upper 32-bits of MSR value. 2022 2023 <b>Example usage</b> 2024 @code 2025 UINT64 Msr; 2026 2027 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1); 2028 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_2_PERFCTR1, Msr); 2029 @endcode 2030 @note MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM. 2031 **/ 2032 #define MSR_SKYLAKE_UNC_CBO_2_PERFCTR1 0x00000727 2033 2034 2035 /** 2036 Package. Uncore C-Box 3, counter 0 event select MSR. 2037 2038 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 (0x00000730) 2039 @param EAX Lower 32-bits of MSR value. 2040 @param EDX Upper 32-bits of MSR value. 2041 2042 <b>Example usage</b> 2043 @code 2044 UINT64 Msr; 2045 2046 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0); 2047 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0, Msr); 2048 @endcode 2049 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM. 2050 **/ 2051 #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL0 0x00000730 2052 2053 2054 /** 2055 Package. Uncore C-Box 3, counter 1 event select MSR. 2056 2057 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 (0x00000731) 2058 @param EAX Lower 32-bits of MSR value. 2059 @param EDX Upper 32-bits of MSR value. 2060 2061 <b>Example usage</b> 2062 @code 2063 UINT64 Msr; 2064 2065 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1); 2066 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1, Msr); 2067 @endcode 2068 @note MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM. 2069 **/ 2070 #define MSR_SKYLAKE_UNC_CBO_3_PERFEVTSEL1 0x00000731 2071 2072 2073 /** 2074 Package. Uncore C-Box 3, performance counter 0. 2075 2076 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 (0x00000736) 2077 @param EAX Lower 32-bits of MSR value. 2078 @param EDX Upper 32-bits of MSR value. 2079 2080 <b>Example usage</b> 2081 @code 2082 UINT64 Msr; 2083 2084 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0); 2085 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR0, Msr); 2086 @endcode 2087 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM. 2088 **/ 2089 #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR0 0x00000736 2090 2091 2092 /** 2093 Package. Uncore C-Box 3, performance counter 1. 2094 2095 @param ECX MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 (0x00000737) 2096 @param EAX Lower 32-bits of MSR value. 2097 @param EDX Upper 32-bits of MSR value. 2098 2099 <b>Example usage</b> 2100 @code 2101 UINT64 Msr; 2102 2103 Msr = AsmReadMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1); 2104 AsmWriteMsr64 (MSR_SKYLAKE_UNC_CBO_3_PERFCTR1, Msr); 2105 @endcode 2106 @note MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM. 2107 **/ 2108 #define MSR_SKYLAKE_UNC_CBO_3_PERFCTR1 0x00000737 2109 2110 2111 /** 2112 Package. Uncore PMU global control. 2113 2114 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL (0x00000E01) 2115 @param EAX Lower 32-bits of MSR value. 2116 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER. 2117 @param EDX Upper 32-bits of MSR value. 2118 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER. 2119 2120 <b>Example usage</b> 2121 @code 2122 MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr; 2123 2124 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL); 2125 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64); 2126 @endcode 2127 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM. 2128 **/ 2129 #define MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 0x00000E01 2130 2131 /** 2132 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL 2133 **/ 2134 typedef union { 2135 /// 2136 /// Individual bit fields 2137 /// 2138 struct { 2139 /// 2140 /// [Bit 0] Slice 0 select. 2141 /// 2142 UINT32 PMI_Sel_Slice0:1; 2143 /// 2144 /// [Bit 1] Slice 1 select. 2145 /// 2146 UINT32 PMI_Sel_Slice1:1; 2147 /// 2148 /// [Bit 2] Slice 2 select. 2149 /// 2150 UINT32 PMI_Sel_Slice2:1; 2151 /// 2152 /// [Bit 3] Slice 3 select. 2153 /// 2154 UINT32 PMI_Sel_Slice3:1; 2155 /// 2156 /// [Bit 4] Slice 4select. 2157 /// 2158 UINT32 PMI_Sel_Slice4:1; 2159 UINT32 Reserved1:14; 2160 UINT32 Reserved2:10; 2161 /// 2162 /// [Bit 29] Enable all uncore counters. 2163 /// 2164 UINT32 EN:1; 2165 /// 2166 /// [Bit 30] Enable wake on PMI. 2167 /// 2168 UINT32 WakePMI:1; 2169 /// 2170 /// [Bit 31] Enable Freezing counter when overflow. 2171 /// 2172 UINT32 FREEZE:1; 2173 UINT32 Reserved3:32; 2174 } Bits; 2175 /// 2176 /// All bit fields as a 32-bit value 2177 /// 2178 UINT32 Uint32; 2179 /// 2180 /// All bit fields as a 64-bit value 2181 /// 2182 UINT64 Uint64; 2183 } MSR_SKYLAKE_UNC_PERF_GLOBAL_CTRL_REGISTER; 2184 2185 2186 /** 2187 Package. Uncore PMU main status. 2188 2189 @param ECX MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS (0x00000E02) 2190 @param EAX Lower 32-bits of MSR value. 2191 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER. 2192 @param EDX Upper 32-bits of MSR value. 2193 Described by the type MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER. 2194 2195 <b>Example usage</b> 2196 @code 2197 MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr; 2198 2199 Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS); 2200 AsmWriteMsr64 (MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64); 2201 @endcode 2202 @note MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM. 2203 **/ 2204 #define MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 0x00000E02 2205 2206 /** 2207 MSR information returned for MSR index #MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS 2208 **/ 2209 typedef union { 2210 /// 2211 /// Individual bit fields 2212 /// 2213 struct { 2214 /// 2215 /// [Bit 0] Fixed counter overflowed. 2216 /// 2217 UINT32 Fixed:1; 2218 /// 2219 /// [Bit 1] An ARB counter overflowed. 2220 /// 2221 UINT32 ARB:1; 2222 UINT32 Reserved1:1; 2223 /// 2224 /// [Bit 3] A CBox counter overflowed (on any slice). 2225 /// 2226 UINT32 CBox:1; 2227 UINT32 Reserved2:28; 2228 UINT32 Reserved3:32; 2229 } Bits; 2230 /// 2231 /// All bit fields as a 32-bit value 2232 /// 2233 UINT32 Uint32; 2234 /// 2235 /// All bit fields as a 64-bit value 2236 /// 2237 UINT64 Uint64; 2238 } MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER; 2239 2240 #endif 2241
