| /art/compiler/optimizing/ |
| intrinsics_mips.cc | 831 __ Sltu(TMP, out_lo, TMP);
[all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitNativeMIPS_common.c | 164 #define SLTU (HI(0) | LO(43))
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/mips32/ |
| valid-mips32.txt | 44 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
88 0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11
|
| valid-mips32-el.txt | 135 0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r2/ |
| valid-mips32r2.txt | 48 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
93 0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11
|
| valid-mips32r2-el.txt | 153 0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r3/ |
| valid-mips32r3.txt | 45 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
90 0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11
|
| valid-mips32r3-el.txt | 149 0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r5/ |
| valid-mips32r5.txt | 45 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
90 0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11
|
| valid-mips32r5-el.txt | 149 0x2b 0x18 0x65 0x00 # CHECK: sltu $3, $3, $5
|
| /external/llvm/test/MC/Disassembler/Mips/mips64/ |
| valid-mips64.txt | 64 0x00 0x65 0x18 0x2b # CHECK: sltu $3, $3, $5
119 0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11
|
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerMIPS32.cpp | 1004 void AssemblerMIPS32::sltu(const Operand *OpRd, const Operand *OpRs, function in class:Ice::MIPS32::AssemblerMIPS32
[all...] |
| IceInstMIPS32.cpp | 135 template <> const char *InstMIPS32Sltu::Opcode = "sltu";
[all...] |
| IceInstMIPS32.h | 266 Sltu,
[all...] |
| /external/v8/src/mips/ |
| constants-mips.h | 447 SLTU = ((5U << 3) + 3),
938 FunctionFieldToBitNumber(SLT) | FunctionFieldToBitNumber(SLTU) |
[all...] |
| disasm-mips.cc | [all...] |
| /external/v8/src/mips64/ |
| constants-mips64.h | 440 SLTU = ((5U << 3) + 3),
983 FunctionFieldToBitNumber(SLT) | FunctionFieldToBitNumber(SLTU) |
[all...] |
| /external/libyuv/files/source/ |
| row_dspr2.cc | 71 "sltu $v1, $t9, %[dst] \n"
122 "sltu $v1, $t9, %[dst] \n"
224 "sltu $v1, $t9, %[dst] \n"
295 "sltu $v1,$t9,%[dst] \n"
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSchedule.td | 275 def II_SLT_SLTU : InstrItinClass; // slt and sltu
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| valid-el.txt | 67 0xa3 0x00 0x90 0x1b # CHECK: sltu $3, $3, $5
|
| valid.txt | 67 0x00 0xa3 0x1b 0x90 # CHECK: sltu $3, $3, $5
|
| /external/llvm/test/MC/Disassembler/Mips/mips2/ |
| valid-mips2.txt | 57 0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11
|
| /external/llvm/test/MC/Disassembler/Mips/mips3/ |
| valid-mips3-el.txt | 161 0x2b 0xa0 0xab 0x02 # CHECK: sltu $20, $21, $11
|
| valid-mips3.txt | 85 0x02 0xab 0xa0 0x2b # CHECK: sltu $20, $21, $11
|
| /external/llvm/test/MC/Disassembler/Mips/mips4/ |
| valid-mips4-el.txt | 180 0x2b 0xa0 0xab 0x02 # CHECK: sltu $20, $21, $11
|
