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  /prebuilts/go/darwin-x86/src/cmd/asm/internal/arch/
arm64.go 156 case "SXTB":
  /prebuilts/go/linux-x86/src/cmd/asm/internal/arch/
arm64.go 156 case "SXTB":
  /system/core/libpixelflinger/codeflinger/
Arm64Disassembler.cpp 215 "sxtb","sxth","sxtw","sxtx"
  /external/capstone/suite/MC/AArch64/
basic-a64-instructions.s.cs 6 0x31,0x83,0x34,0x8b = add x17, x25, w20, sxtb
14 0xa2,0x80,0x21,0x0b = add w2, w5, w1, sxtb
18 0x62,0x80,0x25,0x8b = add x2, x3, w5, sxtb
26 0x31,0x83,0x34,0xcb = sub x17, x25, w20, sxtb
34 0xa2,0x80,0x21,0x4b = sub w2, w5, w1, sxtb
42 0x3f,0x8f,0x34,0xab = adds xzr, x25, w20, sxtb #3
50 0xa2,0x84,0x21,0x2b = adds w2, w5, w1, sxtb #1
58 0x3f,0x8f,0x34,0xeb = subs xzr, x25, w20, sxtb #3
66 0xa2,0x84,0x21,0x6b = subs w2, w5, w1, sxtb #1
74 0x3f,0x8f,0x34,0xeb = cmp x25, w20, sxtb #
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonIsetDx.td 393 // SA1_sxtb: Sxtb.
398 "$Rd = sxtb($Rs)"> {
  /external/vixl/test/aarch32/
test-assembler-cond-rd-operand-rn-t32.cc 60 M(sxtb) \
342 #include "aarch32/traces/assembler-cond-rd-operand-rn-sxtb-t32.h"
test-simulator-cond-rd-operand-rn-a32.cc 124 M(Sxtb) \
481 #include "aarch32/traces/simulator-cond-rd-operand-rn-sxtb-a32.h"
test-simulator-cond-rd-operand-rn-t32.cc 124 M(Sxtb) \
481 #include "aarch32/traces/simulator-cond-rd-operand-rn-sxtb-t32.h"
test-simulator-cond-rd-operand-rn-ror-amount-a32.cc 116 M(Sxtb) \
546 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-sxtb-a32.h"
    [all...]
test-simulator-cond-rd-operand-rn-ror-amount-t32.cc 116 M(Sxtb) \
546 #include "aarch32/traces/simulator-cond-rd-operand-rn-ror-amount-sxtb-t32.h"
    [all...]
  /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/testdata/
arm64enc.s 18 //TODO ADD R8.SXTB<<7, R23, R14 // ee9e288b
368 SXTB R13, R9 // a91d4093
arm64.s 45 CMNW R1.SXTB, R9 // 3f81212b
  /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/
arm64enc.s 18 //TODO ADD R8.SXTB<<7, R23, R14 // ee9e288b
368 SXTB R13, R9 // a91d4093
arm64.s 45 CMNW R1.SXTB, R9 // 3f81212b
  /external/llvm/test/MC/AArch64/
basic-a64-instructions.s 22 add x17, x25, w20, sxtb
30 // CHECK: add x17, x25, w20, sxtb // encoding: [0x31,0x83,0x34,0x8b]
40 add w2, w5, w1, sxtb
48 // CHECK: add w2, w5, w1, sxtb // encoding: [0xa2,0x80,0x21,0x0b]
54 add x2, x3, w5, sxtb #0
58 // CHECK: add x2, x3, w5, sxtb // encoding: [0x62,0x80,0x25,0x8b]
68 sub x17, x25, w20, sxtb
76 // CHECK: sub x17, x25, w20, sxtb // encoding: [0x31,0x83,0x34,0xcb]
85 sub w2, w5, w1, sxtb
93 // CHECK: sub w2, w5, w1, sxtb // encoding: [0xa2,0x80,0x21,0x4b
    [all...]
arm64-aliases.s 315 sxtb w1, w2
320 ; CHECK: sxtb w1, w2
325 sxtb x1, w2
332 ; CHECK: sxtb x1, w2
  /external/capstone/suite/MC/ARM/
basic-thumb2-instructions.s.cs     [all...]
  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonMCDuplexInfo.cpp 406 // Rd = sxth/sxtb/zxtb/zxth(Rs)
521 // Rd = sxth/sxtb/zxtb/zxth(Rs)
943 break; // 1,2 SUBInst $Rd = sxtb($Rs)
    [all...]
  /external/vixl/test/aarch64/
test-assembler-aarch64.cc 382 __ Add(sp, sp, Operand(x17, SXTB));
429 __ Mvn(x11, Operand(x2, SXTB, 1));
604 __ Mov(x24, Operand(x13, SXTB, 1));
658 __ Mov(w20, Operand(w11, SXTB, 1));
742 __ Orr(w10, w0, Operand(w1, SXTB));
836 __ Orn(w10, w0, Operand(w1, SXTB));
903 __ And(w10, w0, Operand(w1, SXTB));
1041 __ Bic(w10, w0, Operand(w1, SXTB));
    [all...]
  /art/compiler/optimizing/
common_arm64.h 334 case HDataProcWithShifterOp::kSXTB: return vixl::aarch64::SXTB;
  /external/llvm/test/CodeGen/AArch64/
atomic-ops.ll 504 ; CHECK-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
505 ; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxtb
601 ; CHECK-NEXT: sxtb w[[OLD_EXT:[0-9]+]], w[[OLD]]
602 ; CHECK-NEXT: cmp w[[OLD_EXT]], w0, sxtb
    [all...]
  /external/vixl/src/aarch32/
constants-aarch32.cc 452 return "sxtb";
  /prebuilts/vndk/v27/arm/arch-arm-armv7-a-neon/shared/vndk-core/
libvixl-arm.so 
  /prebuilts/vndk/v27/arm64/arch-arm-armv7-a-neon/shared/vndk-core/
libvixl-arm.so 
  /toolchain/binutils/binutils-2.27/opcodes/
aarch64-asm-2.c 116 case 612: /* sxtb */

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