1 //=- HexagonIsetDx.td - Target Desc. for Hexagon Target -*- tablegen -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file describes the Hexagon duplex instructions. 11 // 12 //===----------------------------------------------------------------------===// 13 14 // SA1_combine1i: Combines. 15 let isCodeGenOnly = 1, hasSideEffects = 0 in 16 def V4_SA1_combine1i: SUBInst < 17 (outs DoubleRegs:$Rdd), 18 (ins u2Imm:$u2), 19 "$Rdd = combine(#1, #$u2)"> { 20 bits<3> Rdd; 21 bits<2> u2; 22 23 let Inst{12-10} = 0b111; 24 let Inst{8} = 0b0; 25 let Inst{4-3} = 0b01; 26 let Inst{2-0} = Rdd; 27 let Inst{6-5} = u2; 28 } 29 30 // SL2_jumpr31_f: Indirect conditional jump if false. 31 // SL2_jumpr31_f -> SL2_jumpr31_fnew 32 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in 33 def V4_SL2_jumpr31_f: SUBInst < 34 (outs ), 35 (ins ), 36 "if (!p0) jumpr r31"> { 37 let Inst{12-6} = 0b1111111; 38 let Inst{2-0} = 0b101; 39 } 40 41 // SL2_deallocframe: Deallocate stack frame. 42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in 43 def V4_SL2_deallocframe: SUBInst < 44 (outs ), 45 (ins ), 46 "deallocframe"> { 47 let Inst{12-6} = 0b1111100; 48 let Inst{2} = 0b0; 49 } 50 51 // SL2_return_f: Deallocate stack frame and return. 52 // SL2_return_f -> SL2_return_fnew 53 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in 54 def V4_SL2_return_f: SUBInst < 55 (outs ), 56 (ins ), 57 "if (!p0) dealloc_return"> { 58 let Inst{12-6} = 0b1111101; 59 let Inst{2-0} = 0b101; 60 } 61 62 // SA1_combine3i: Combines. 63 let isCodeGenOnly = 1, hasSideEffects = 0 in 64 def V4_SA1_combine3i: SUBInst < 65 (outs DoubleRegs:$Rdd), 66 (ins u2Imm:$u2), 67 "$Rdd = combine(#3, #$u2)"> { 68 bits<3> Rdd; 69 bits<2> u2; 70 71 let Inst{12-10} = 0b111; 72 let Inst{8} = 0b0; 73 let Inst{4-3} = 0b11; 74 let Inst{2-0} = Rdd; 75 let Inst{6-5} = u2; 76 } 77 78 // SS2_storebi0: Store byte. 79 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in 80 def V4_SS2_storebi0: SUBInst < 81 (outs ), 82 (ins IntRegs:$Rs, u4_0Imm:$u4_0), 83 "memb($Rs + #$u4_0)=#0"> { 84 bits<4> Rs; 85 bits<4> u4_0; 86 87 let Inst{12-8} = 0b10010; 88 let Inst{7-4} = Rs; 89 let Inst{3-0} = u4_0; 90 } 91 92 // SA1_clrtnew: Clear if true. 93 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 94 def V4_SA1_clrtnew: SUBInst < 95 (outs IntRegs:$Rd), 96 (ins ), 97 "if (p0.new) $Rd = #0"> { 98 bits<4> Rd; 99 100 let Inst{12-9} = 0b1101; 101 let Inst{6-4} = 0b100; 102 let Inst{3-0} = Rd; 103 } 104 105 // SL2_loadruh_io: Load half. 106 let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in 107 def V4_SL2_loadruh_io: SUBInst < 108 (outs IntRegs:$Rd), 109 (ins IntRegs:$Rs, u3_1Imm:$u3_1), 110 "$Rd = memuh($Rs + #$u3_1)"> { 111 bits<4> Rd; 112 bits<4> Rs; 113 bits<4> u3_1; 114 115 let Inst{12-11} = 0b01; 116 let Inst{3-0} = Rd; 117 let Inst{7-4} = Rs; 118 let Inst{10-8} = u3_1{3-1}; 119 } 120 121 // SL2_jumpr31_tnew: Indirect conditional jump if true. 122 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in 123 def V4_SL2_jumpr31_tnew: SUBInst < 124 (outs ), 125 (ins ), 126 "if (p0.new) jumpr:nt r31"> { 127 let Inst{12-6} = 0b1111111; 128 let Inst{2-0} = 0b110; 129 } 130 131 // SA1_addi: Add. 132 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 1, opExtentBits = 7, opExtendable = 2 in 133 def V4_SA1_addi: SUBInst < 134 (outs IntRegs:$Rx), 135 (ins IntRegs:$_src_, s7Ext:$s7), 136 "$Rx = add($_src_, #$s7)" , 137 [] , 138 "$_src_ = $Rx"> { 139 bits<4> Rx; 140 bits<7> s7; 141 142 let Inst{12-11} = 0b00; 143 let Inst{3-0} = Rx; 144 let Inst{10-4} = s7; 145 } 146 147 // SL1_loadrub_io: Load byte. 148 let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in 149 def V4_SL1_loadrub_io: SUBInst < 150 (outs IntRegs:$Rd), 151 (ins IntRegs:$Rs, u4_0Imm:$u4_0), 152 "$Rd = memub($Rs + #$u4_0)"> { 153 bits<4> Rd; 154 bits<4> Rs; 155 bits<4> u4_0; 156 157 let Inst{12} = 0b1; 158 let Inst{3-0} = Rd; 159 let Inst{7-4} = Rs; 160 let Inst{11-8} = u4_0; 161 } 162 163 // SL1_loadri_io: Load word. 164 let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in 165 def V4_SL1_loadri_io: SUBInst < 166 (outs IntRegs:$Rd), 167 (ins IntRegs:$Rs, u4_2Imm:$u4_2), 168 "$Rd = memw($Rs + #$u4_2)"> { 169 bits<4> Rd; 170 bits<4> Rs; 171 bits<6> u4_2; 172 173 let Inst{12} = 0b0; 174 let Inst{3-0} = Rd; 175 let Inst{7-4} = Rs; 176 let Inst{11-8} = u4_2{5-2}; 177 } 178 179 // SA1_cmpeqi: Compareimmed. 180 let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in 181 def V4_SA1_cmpeqi: SUBInst < 182 (outs ), 183 (ins IntRegs:$Rs, u2Imm:$u2), 184 "p0 = cmp.eq($Rs, #$u2)"> { 185 bits<4> Rs; 186 bits<2> u2; 187 188 let Inst{12-8} = 0b11001; 189 let Inst{7-4} = Rs; 190 let Inst{1-0} = u2; 191 } 192 193 // SA1_combinerz: Combines. 194 let isCodeGenOnly = 1, hasSideEffects = 0 in 195 def V4_SA1_combinerz: SUBInst < 196 (outs DoubleRegs:$Rdd), 197 (ins IntRegs:$Rs), 198 "$Rdd = combine($Rs, #0)"> { 199 bits<3> Rdd; 200 bits<4> Rs; 201 202 let Inst{12-10} = 0b111; 203 let Inst{8} = 0b1; 204 let Inst{3} = 0b1; 205 let Inst{2-0} = Rdd; 206 let Inst{7-4} = Rs; 207 } 208 209 // SL2_return_t: Deallocate stack frame and return. 210 // SL2_return_t -> SL2_return_tnew 211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in 212 def V4_SL2_return_t: SUBInst < 213 (outs ), 214 (ins ), 215 "if (p0) dealloc_return"> { 216 let Inst{12-6} = 0b1111101; 217 let Inst{2-0} = 0b100; 218 } 219 220 // SS2_allocframe: Allocate stack frame. 221 let Defs = [R29, R30], Uses = [R30, R31, R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in 222 def V4_SS2_allocframe: SUBInst < 223 (outs ), 224 (ins u5_3Imm:$u5_3), 225 "allocframe(#$u5_3)"> { 226 bits<8> u5_3; 227 228 let Inst{12-9} = 0b1110; 229 let Inst{8-4} = u5_3{7-3}; 230 } 231 232 // SS2_storeh_io: Store half. 233 let isCodeGenOnly = 1, mayStore = 1, accessSize = HalfWordAccess in 234 def V4_SS2_storeh_io: SUBInst < 235 (outs ), 236 (ins IntRegs:$Rs, u3_1Imm:$u3_1, IntRegs:$Rt), 237 "memh($Rs + #$u3_1) = $Rt"> { 238 bits<4> Rs; 239 bits<4> u3_1; 240 bits<4> Rt; 241 242 let Inst{12-11} = 0b00; 243 let Inst{7-4} = Rs; 244 let Inst{10-8} = u3_1{3-1}; 245 let Inst{3-0} = Rt; 246 } 247 248 // SS2_storewi0: Store word. 249 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in 250 def V4_SS2_storewi0: SUBInst < 251 (outs ), 252 (ins IntRegs:$Rs, u4_2Imm:$u4_2), 253 "memw($Rs + #$u4_2)=#0"> { 254 bits<4> Rs; 255 bits<6> u4_2; 256 257 let Inst{12-8} = 0b10000; 258 let Inst{7-4} = Rs; 259 let Inst{3-0} = u4_2{5-2}; 260 } 261 262 // SS2_storewi1: Store word. 263 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in 264 def V4_SS2_storewi1: SUBInst < 265 (outs ), 266 (ins IntRegs:$Rs, u4_2Imm:$u4_2), 267 "memw($Rs + #$u4_2)=#1"> { 268 bits<4> Rs; 269 bits<6> u4_2; 270 271 let Inst{12-8} = 0b10001; 272 let Inst{7-4} = Rs; 273 let Inst{3-0} = u4_2{5-2}; 274 } 275 276 // SL2_jumpr31: Indirect conditional jump if true. 277 let Defs = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in 278 def V4_SL2_jumpr31: SUBInst < 279 (outs ), 280 (ins ), 281 "jumpr r31"> { 282 let Inst{12-6} = 0b1111111; 283 let Inst{2} = 0b0; 284 } 285 286 // SA1_combinezr: Combines. 287 let isCodeGenOnly = 1, hasSideEffects = 0 in 288 def V4_SA1_combinezr: SUBInst < 289 (outs DoubleRegs:$Rdd), 290 (ins IntRegs:$Rs), 291 "$Rdd = combine(#0, $Rs)"> { 292 bits<3> Rdd; 293 bits<4> Rs; 294 295 let Inst{12-10} = 0b111; 296 let Inst{8} = 0b1; 297 let Inst{3} = 0b0; 298 let Inst{2-0} = Rdd; 299 let Inst{7-4} = Rs; 300 } 301 302 // SL2_loadrh_io: Load half. 303 let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in 304 def V4_SL2_loadrh_io: SUBInst < 305 (outs IntRegs:$Rd), 306 (ins IntRegs:$Rs, u3_1Imm:$u3_1), 307 "$Rd = memh($Rs + #$u3_1)"> { 308 bits<4> Rd; 309 bits<4> Rs; 310 bits<4> u3_1; 311 312 let Inst{12-11} = 0b00; 313 let Inst{3-0} = Rd; 314 let Inst{7-4} = Rs; 315 let Inst{10-8} = u3_1{3-1}; 316 } 317 318 // SA1_addrx: Add. 319 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 320 def V4_SA1_addrx: SUBInst < 321 (outs IntRegs:$Rx), 322 (ins IntRegs:$_src_, IntRegs:$Rs), 323 "$Rx = add($_src_, $Rs)" , 324 [] , 325 "$_src_ = $Rx"> { 326 bits<4> Rx; 327 bits<4> Rs; 328 329 let Inst{12-8} = 0b11000; 330 let Inst{3-0} = Rx; 331 let Inst{7-4} = Rs; 332 } 333 334 // SA1_setin1: Set to -1. 335 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 336 def V4_SA1_setin1: SUBInst < 337 (outs IntRegs:$Rd), 338 (ins ), 339 "$Rd = #-1"> { 340 bits<4> Rd; 341 342 let Inst{12-9} = 0b1101; 343 let Inst{6} = 0b0; 344 let Inst{3-0} = Rd; 345 } 346 347 // SA1_sxth: Sxth. 348 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 349 def V4_SA1_sxth: SUBInst < 350 (outs IntRegs:$Rd), 351 (ins IntRegs:$Rs), 352 "$Rd = sxth($Rs)"> { 353 bits<4> Rd; 354 bits<4> Rs; 355 356 let Inst{12-8} = 0b10100; 357 let Inst{3-0} = Rd; 358 let Inst{7-4} = Rs; 359 } 360 361 // SA1_combine0i: Combines. 362 let isCodeGenOnly = 1, hasSideEffects = 0 in 363 def V4_SA1_combine0i: SUBInst < 364 (outs DoubleRegs:$Rdd), 365 (ins u2Imm:$u2), 366 "$Rdd = combine(#0, #$u2)"> { 367 bits<3> Rdd; 368 bits<2> u2; 369 370 let Inst{12-10} = 0b111; 371 let Inst{8} = 0b0; 372 let Inst{4-3} = 0b00; 373 let Inst{2-0} = Rdd; 374 let Inst{6-5} = u2; 375 } 376 377 // SA1_combine2i: Combines. 378 let isCodeGenOnly = 1, hasSideEffects = 0 in 379 def V4_SA1_combine2i: SUBInst < 380 (outs DoubleRegs:$Rdd), 381 (ins u2Imm:$u2), 382 "$Rdd = combine(#2, #$u2)"> { 383 bits<3> Rdd; 384 bits<2> u2; 385 386 let Inst{12-10} = 0b111; 387 let Inst{8} = 0b0; 388 let Inst{4-3} = 0b10; 389 let Inst{2-0} = Rdd; 390 let Inst{6-5} = u2; 391 } 392 393 // SA1_sxtb: Sxtb. 394 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 395 def V4_SA1_sxtb: SUBInst < 396 (outs IntRegs:$Rd), 397 (ins IntRegs:$Rs), 398 "$Rd = sxtb($Rs)"> { 399 bits<4> Rd; 400 bits<4> Rs; 401 402 let Inst{12-8} = 0b10101; 403 let Inst{3-0} = Rd; 404 let Inst{7-4} = Rs; 405 } 406 407 // SA1_clrf: Clear if false. 408 // SA1_clrf -> SA1_clrfnew 409 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 410 def V4_SA1_clrf: SUBInst < 411 (outs IntRegs:$Rd), 412 (ins ), 413 "if (!p0) $Rd = #0"> { 414 bits<4> Rd; 415 416 let Inst{12-9} = 0b1101; 417 let Inst{6-4} = 0b111; 418 let Inst{3-0} = Rd; 419 } 420 421 // SL2_loadrb_io: Load byte. 422 let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in 423 def V4_SL2_loadrb_io: SUBInst < 424 (outs IntRegs:$Rd), 425 (ins IntRegs:$Rs, u3_0Imm:$u3_0), 426 "$Rd = memb($Rs + #$u3_0)"> { 427 bits<4> Rd; 428 bits<4> Rs; 429 bits<3> u3_0; 430 431 let Inst{12-11} = 0b10; 432 let Inst{3-0} = Rd; 433 let Inst{7-4} = Rs; 434 let Inst{10-8} = u3_0; 435 } 436 437 // SA1_tfr: Tfr. 438 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 439 def V4_SA1_tfr: SUBInst < 440 (outs IntRegs:$Rd), 441 (ins IntRegs:$Rs), 442 "$Rd = $Rs"> { 443 bits<4> Rd; 444 bits<4> Rs; 445 446 let Inst{12-8} = 0b10000; 447 let Inst{3-0} = Rd; 448 let Inst{7-4} = Rs; 449 } 450 451 // SL2_loadrd_sp: Load dword. 452 let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in 453 def V4_SL2_loadrd_sp: SUBInst < 454 (outs DoubleRegs:$Rdd), 455 (ins u5_3Imm:$u5_3), 456 "$Rdd = memd(r29 + #$u5_3)"> { 457 bits<3> Rdd; 458 bits<8> u5_3; 459 460 let Inst{12-8} = 0b11110; 461 let Inst{2-0} = Rdd; 462 let Inst{7-3} = u5_3{7-3}; 463 } 464 465 // SA1_and1: And #1. 466 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 467 def V4_SA1_and1: SUBInst < 468 (outs IntRegs:$Rd), 469 (ins IntRegs:$Rs), 470 "$Rd = and($Rs, #1)"> { 471 bits<4> Rd; 472 bits<4> Rs; 473 474 let Inst{12-8} = 0b10010; 475 let Inst{3-0} = Rd; 476 let Inst{7-4} = Rs; 477 } 478 479 // SS2_storebi1: Store byte. 480 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in 481 def V4_SS2_storebi1: SUBInst < 482 (outs ), 483 (ins IntRegs:$Rs, u4_0Imm:$u4_0), 484 "memb($Rs + #$u4_0)=#1"> { 485 bits<4> Rs; 486 bits<4> u4_0; 487 488 let Inst{12-8} = 0b10011; 489 let Inst{7-4} = Rs; 490 let Inst{3-0} = u4_0; 491 } 492 493 // SA1_inc: Inc. 494 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 495 def V4_SA1_inc: SUBInst < 496 (outs IntRegs:$Rd), 497 (ins IntRegs:$Rs), 498 "$Rd = add($Rs, #1)"> { 499 bits<4> Rd; 500 bits<4> Rs; 501 502 let Inst{12-8} = 0b10001; 503 let Inst{3-0} = Rd; 504 let Inst{7-4} = Rs; 505 } 506 507 // SS2_stored_sp: Store dword. 508 let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = DoubleWordAccess in 509 def V4_SS2_stored_sp: SUBInst < 510 (outs ), 511 (ins s6_3Imm:$s6_3, DoubleRegs:$Rtt), 512 "memd(r29 + #$s6_3) = $Rtt"> { 513 bits<9> s6_3; 514 bits<3> Rtt; 515 516 let Inst{12-9} = 0b0101; 517 let Inst{8-3} = s6_3{8-3}; 518 let Inst{2-0} = Rtt; 519 } 520 521 // SS2_storew_sp: Store word. 522 let Uses = [R29], isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in 523 def V4_SS2_storew_sp: SUBInst < 524 (outs ), 525 (ins u5_2Imm:$u5_2, IntRegs:$Rt), 526 "memw(r29 + #$u5_2) = $Rt"> { 527 bits<7> u5_2; 528 bits<4> Rt; 529 530 let Inst{12-9} = 0b0100; 531 let Inst{8-4} = u5_2{6-2}; 532 let Inst{3-0} = Rt; 533 } 534 535 // SL2_jumpr31_fnew: Indirect conditional jump if false. 536 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in 537 def V4_SL2_jumpr31_fnew: SUBInst < 538 (outs ), 539 (ins ), 540 "if (!p0.new) jumpr:nt r31"> { 541 let Inst{12-6} = 0b1111111; 542 let Inst{2-0} = 0b111; 543 } 544 545 // SA1_clrt: Clear if true. 546 // SA1_clrt -> SA1_clrtnew 547 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 548 def V4_SA1_clrt: SUBInst < 549 (outs IntRegs:$Rd), 550 (ins ), 551 "if (p0) $Rd = #0"> { 552 bits<4> Rd; 553 554 let Inst{12-9} = 0b1101; 555 let Inst{6-4} = 0b110; 556 let Inst{3-0} = Rd; 557 } 558 559 // SL2_return: Deallocate stack frame and return. 560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in 561 def V4_SL2_return: SUBInst < 562 (outs ), 563 (ins ), 564 "dealloc_return"> { 565 let Inst{12-6} = 0b1111101; 566 let Inst{2} = 0b0; 567 } 568 569 // SA1_dec: Dec. 570 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 571 def V4_SA1_dec: SUBInst < 572 (outs IntRegs:$Rd), 573 (ins IntRegs:$Rs), 574 "$Rd = add($Rs,#-1)"> { 575 bits<4> Rd; 576 bits<4> Rs; 577 578 let Inst{12-8} = 0b10011; 579 let Inst{3-0} = Rd; 580 let Inst{7-4} = Rs; 581 } 582 583 // SA1_seti: Set immed. 584 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExtentSigned = 0, opExtentBits = 6, opExtendable = 1 in 585 def V4_SA1_seti: SUBInst < 586 (outs IntRegs:$Rd), 587 (ins u6Ext:$u6), 588 "$Rd = #$u6"> { 589 bits<4> Rd; 590 bits<6> u6; 591 592 let Inst{12-10} = 0b010; 593 let Inst{3-0} = Rd; 594 let Inst{9-4} = u6; 595 } 596 597 // SL2_jumpr31_t: Indirect conditional jump if true. 598 // SL2_jumpr31_t -> SL2_jumpr31_tnew 599 let Defs = [PC], Uses = [P0, R31], isCodeGenOnly = 1, isPredicated = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in 600 def V4_SL2_jumpr31_t: SUBInst < 601 (outs ), 602 (ins ), 603 "if (p0) jumpr r31"> { 604 let Inst{12-6} = 0b1111111; 605 let Inst{2-0} = 0b100; 606 } 607 608 // SA1_clrfnew: Clear if false. 609 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 610 def V4_SA1_clrfnew: SUBInst < 611 (outs IntRegs:$Rd), 612 (ins ), 613 "if (!p0.new) $Rd = #0"> { 614 bits<4> Rd; 615 616 let Inst{12-9} = 0b1101; 617 let Inst{6-4} = 0b101; 618 let Inst{3-0} = Rd; 619 } 620 621 // SS1_storew_io: Store word. 622 let isCodeGenOnly = 1, mayStore = 1, accessSize = WordAccess in 623 def V4_SS1_storew_io: SUBInst < 624 (outs ), 625 (ins IntRegs:$Rs, u4_2Imm:$u4_2, IntRegs:$Rt), 626 "memw($Rs + #$u4_2) = $Rt"> { 627 bits<4> Rs; 628 bits<6> u4_2; 629 bits<4> Rt; 630 631 let Inst{12} = 0b0; 632 let Inst{7-4} = Rs; 633 let Inst{11-8} = u4_2{5-2}; 634 let Inst{3-0} = Rt; 635 } 636 637 // SA1_zxtb: Zxtb. 638 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 639 def V4_SA1_zxtb: SUBInst < 640 (outs IntRegs:$Rd), 641 (ins IntRegs:$Rs), 642 "$Rd = and($Rs, #255)"> { 643 bits<4> Rd; 644 bits<4> Rs; 645 646 let Inst{12-8} = 0b10111; 647 let Inst{3-0} = Rd; 648 let Inst{7-4} = Rs; 649 } 650 651 // SA1_addsp: Add. 652 let Uses = [R29], isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 653 def V4_SA1_addsp: SUBInst < 654 (outs IntRegs:$Rd), 655 (ins u6_2Imm:$u6_2), 656 "$Rd = add(r29, #$u6_2)"> { 657 bits<4> Rd; 658 bits<8> u6_2; 659 660 let Inst{12-10} = 0b011; 661 let Inst{3-0} = Rd; 662 let Inst{9-4} = u6_2{7-2}; 663 } 664 665 // SL2_loadri_sp: Load word. 666 let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in 667 def V4_SL2_loadri_sp: SUBInst < 668 (outs IntRegs:$Rd), 669 (ins u5_2Imm:$u5_2), 670 "$Rd = memw(r29 + #$u5_2)"> { 671 bits<4> Rd; 672 bits<7> u5_2; 673 674 let Inst{12-9} = 0b1110; 675 let Inst{3-0} = Rd; 676 let Inst{8-4} = u5_2{6-2}; 677 } 678 679 // SS1_storeb_io: Store byte. 680 let isCodeGenOnly = 1, mayStore = 1, accessSize = ByteAccess in 681 def V4_SS1_storeb_io: SUBInst < 682 (outs ), 683 (ins IntRegs:$Rs, u4_0Imm:$u4_0, IntRegs:$Rt), 684 "memb($Rs + #$u4_0) = $Rt"> { 685 bits<4> Rs; 686 bits<4> u4_0; 687 bits<4> Rt; 688 689 let Inst{12} = 0b1; 690 let Inst{7-4} = Rs; 691 let Inst{11-8} = u4_0; 692 let Inst{3-0} = Rt; 693 } 694 695 // SL2_return_tnew: Deallocate stack frame and return. 696 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in 697 def V4_SL2_return_tnew: SUBInst < 698 (outs ), 699 (ins ), 700 "if (p0.new) dealloc_return:nt"> { 701 let Inst{12-6} = 0b1111101; 702 let Inst{2-0} = 0b110; 703 } 704 705 // SL2_return_fnew: Deallocate stack frame and return. 706 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, isPredicatedNew = 1, mayLoad = 1, accessSize = DoubleWordAccess, isBranch = 1, isIndirectBranch = 1 in 707 def V4_SL2_return_fnew: SUBInst < 708 (outs ), 709 (ins ), 710 "if (!p0.new) dealloc_return:nt"> { 711 let Inst{12-6} = 0b1111101; 712 let Inst{2-0} = 0b111; 713 } 714 715 // SA1_zxth: Zxth. 716 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in 717 def V4_SA1_zxth: SUBInst < 718 (outs IntRegs:$Rd), 719 (ins IntRegs:$Rs), 720 "$Rd = zxth($Rs)"> { 721 bits<4> Rd; 722 bits<4> Rs; 723 724 let Inst{12-8} = 0b10110; 725 let Inst{3-0} = Rd; 726 let Inst{7-4} = Rs; 727 } 728 729
