| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| vshiftins.ll | 71 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 63, i64 63 >)
143 %tmp3 = call <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2, <2 x i64> < i64 -64, i64 -64 >)
155 declare <2 x i64> @llvm.arm.neon.vshiftins.v2i64(<2 x i64>, <2 x i64>, <2 x i64>) nounwind readnone
|
| vld1.ll | 116 %tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)
130 declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*, i32) nounwind readonly
|
| vst1.ll | 116 call void @llvm.arm.neon.vst1.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1)
130 declare void @llvm.arm.neon.vst1.v2i64(i8*, <2 x i64>, i32) nounwind
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMInstrNEON.td | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 525 case MVT::v2i64:
536 case MVT::v2i64:
[all...] |
| AArch64InstrFormats.td | 78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
[all...] |
| /external/clang/test/CodeGen/ |
| aarch64-neon-2velem.c | 515 // CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2
541 // CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2
569 // CHECK: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) #2
[all...] |
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| sub_pixel_variance_msa.c | 412 src0 = (v16i8)__msa_ilvev_d((v2i64)src2, (v2i64)src0);
451 out = (v16u8)__msa_ilvev_d((v2i64)src1, (v2i64)src0);
453 out = (v16u8)__msa_ilvev_d((v2i64)src3, (v2i64)src2);
762 hz_out3 = (v8u16)__msa_pckod_d((v2i64)hz_out4, (v2i64)hz_out2);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXVector.td | 73 // Extract v2i64
78 (v2i64 V2I64Regs:$src), imm:$c))],
159 // Insert v2i64
262 def V2I64 : VecBinaryOp<V2AsmStr<!strconcat(asmstr, "64")>, OpNode, V2I64Regs,
296 def V2I64 : VecUnaryOp<V2UnaryStr<!strconcat(asmstr, "64")>, OpNode,
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.td | 291 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32], 128,
298 def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
301 def VSHRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
307 def VSRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
|
| /external/llvm/lib/Target/X86/ |
| X86InstrFragmentsSIMD.td | 303 SDTypeProfile<1, 3, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
306 SDTypeProfile<1, 4, [SDTCisVT<0, v2i64>, SDTCisSameAs<0,1>,
610 // NOTE: all 128-bit integer vector loads are promoted to v2i64
613 def loadv2i64 : PatFrag<(ops node:$ptr), (v2i64 (load node:$ptr))>;
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-vcmp.ll | 39 %tmp3 = call <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
45 declare <2 x i64> @llvm.aarch64.neon.facge.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone
70 %tmp3 = call <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double> %tmp1, <2 x double> %tmp2)
76 declare <2 x i64> @llvm.aarch64.neon.facgt.v2i64.v2f64(<2 x double>, <2 x double>) nounwind readnone
|
| arm64-ld1.ll | 223 %tmp2 = call %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2.v2i64.p0i64(i64* %A)
232 %tmp2 = call %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3.v2i64.p0i64(i64* %A)
241 %tmp2 = call %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4.v2i64.p0i64(i64* %A)
245 declare %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2.v2i64.p0i64(i64*) nounwind readonly
246 declare %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3.v2i64.p0i64(i64*) nounwind readonly
247 declare %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4.v2i64.p0i64(i64*) nounwind readonly
421 %tmp2 = call %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, i64 1, i64* %A)
430 %tmp2 = call %struct.__neon_int64x2x3_t @llvm.aarch64.neon.ld3lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, i64 1, i64* %A)
439 %tmp2 = call %struct.__neon_int64x2x4_t @llvm.aarch64.neon.ld4lane.v2i64.p0i64(<2 x i64> %L1, <2 x i64> %L2, <2 x i64> %L3, <2 x i64> %L4, i64 1, i64* %A)
443 declare %struct.__neon_int64x2x2_t @llvm.aarch64.neon.ld2lane.v2i64.p0i64(<2 x i64>, <2 x i64>, i64, i64*) nounwind readonl
[all...] |
| /external/llvm/test/CodeGen/SystemZ/ |
| vec-const-16.ll | 1 ; Test vector replicates that use VECTOR GENERATE MASK, v2i64 version.
|
| vec-move-01.ll | 29 ; Test v2i64 moves.
|
| vec-move-13.ll | 39 ; Test v2i64 insertion into 0.
|
| vec-perm-01.ll | 106 ; Test v2i64 splat of the first element.
116 ; Test v2i64 splat of the last element.
|
| vec-perm-08.ll | 112 ; Test a high1/low2 permute for v2i64.
122 ; Test low2/high1 permute for v2i64.
|
| /external/webp/src/dsp/ |
| lossless_msa.c | 50 pix_d = __msa_copy_s_d((v2i64)dst1, 0); \
57 uint64_t pix_d = __msa_copy_s_d((v2i64)dst0, 0); \
323 const uint64_t pix_d = __msa_copy_s_d((v2i64)dst0, 0);
328 const uint64_t pix_d = __msa_copy_s_d((v2i64)dst0, 0);
|
| /external/llvm/test/CodeGen/ARM/ |
| vst1.ll | 116 call void @llvm.arm.neon.vst1.p0i8.v2i64(i8* %tmp0, <2 x i64> %tmp1, i32 1)
139 declare void @llvm.arm.neon.vst1.p0i8.v2i64(i8*, <2 x i64>, i32) nounwind
|
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 96 v2i64 = 46, // 2 x i64
250 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
350 case v2i64:
415 case v2i64:
485 case v2i64:
634 if (NumElements == 2) return MVT::v2i64;
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ValueTypes.h | 67 v2i64 = 25, // 2 x i64 enumerator in enum:llvm::MVT::SimpleValueType
203 case v2i64:
235 case v2i64:
275 case v2i64:
358 if (NumElements == 2) return MVT::v2i64;
497 V==MVT::v2i64 || V==MVT::v4f32 || V==MVT::v2f64);
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 95 v2i64 = 46, // 2 x i64
248 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
347 case v2i64:
412 case v2i64:
482 case v2i64:
631 if (NumElements == 2) return MVT::v2i64;
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 95 v2i64 = 46, // 2 x i64
248 SimpleTy == MVT::v4i32 || SimpleTy == MVT::v2i64 ||
347 case v2i64:
412 case v2i64:
482 case v2i64:
631 if (NumElements == 2) return MVT::v2i64;
|
| /external/llvm/include/llvm/IR/ |
| IntrinsicsNVVM.td | [all...] |
