| /external/llvm/test/CodeGen/X86/ |
| vector-tzcnt-128.ll | 116 %out = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %in, i1 0)
233 %out = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %in, i1 -1)
[all...] |
| vector-lzcnt-128.ll | 143 %out = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %in, i1 0)
256 %out = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %in, i1 -1)
[all...] |
| /external/clang/test/CodeGen/ |
| builtins-systemz-vector.c | 159 // CHECK: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.*}}, i1 false)
168 // CHECK: call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %{{.*}}, i1 false)
308 // CHECK: call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}})
[all...] |
| systemz-abi-vector.c | 30 typedef __attribute__((vector_size(16))) long long v2i64; typedef
98 v2i64 pass_v2i64(v2i64 arg) { return arg; }
[all...] |
| aarch64-neon-intrinsics.c | [all...] |
| builtins-ppc-p8vector.c | 415 // CHECK: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.+}}, i1 false)
416 // CHECK-LE: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.+}}, i1 false)
419 // CHECK: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.+}}, i1 false)
420 // CHECK-LE: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.+}}, i1 false)
[all...] |
| aarch64-neon-ldst-one.c | 363 // CHECK: [[VLD2:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* [[TMP2]])
433 // CHECK: [[VLD2:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* [[TMP2]])
539 // CHECK: [[VLD2:%.*]] = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0i64(i64* [[TMP2]])
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 68 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
98 setOperationAction(ISD::ConstantPool, MVT::v2i64, Expand);
139 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) {
163 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
164 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 15 // ISD::SDIV of type v2i64 on x86-32. The type is legal (for example, addition
16 // on a v2i64 is legal), but ISD::SDIV isn't legal, so we have to unroll the
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/ |
| Intrinsics.gen | [all...] |
| Intrinsics.td | 131 def llvm_v2i64_ty : LLVMType<v2i64>; // 2 x i64
|
| /external/libvpx/libvpx/vpx_dsp/mips/ |
| avg_msa.c | 574 v2i64 sse_v;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64SchedM1.td | 347 def : InstRW<[M1WriteNALU2], (instregex "^(TRN|UZP)[12](v16i8|v8i16|v4i32|v2i64)")>;
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 147 VT != MVT::v2i64 && VT != MVT::v1i64)
476 addQRTypeForNEON(MVT::v2i64);
550 // Neon does not support some operations on v1i64 and v2i64 types.
555 setOperationAction(ISD::MUL, MVT::v2i64, Custom);
562 setOperationAction(ISD::SETCC, MVT::v2i64, Expand);
583 setOperationAction(ISD::CTPOP, MVT::v2i64, Expand);
586 setOperationAction(ISD::CTLZ, MVT::v2i64, Expand);
597 setOperationAction(ISD::CTTZ, MVT::v2i64, Custom);
607 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::v2i64, Custom);
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsRegisterInfo.td | 409 def MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128,
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCTargetTransformInfo.cpp | 371 (LT.second == MVT::v2f64 || LT.second == MVT::v2i64);
|
| README_ALTIVEC.txt | 330 v2i64 can be supported with VSX and P8Vector in the same manner as
|
| p9-instrs.txt | 413 [PO VRT EO VRB XO] vctzb vctzh vctzw vctzd (v16i8 v8i16 v4i32 v2i64)
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| masked-intrinsic-cost.ll | 300 declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)
|
| /external/llvm/test/CodeGen/ARM/ |
| big-endian-neon-bitconv.ll | 4 @v2i64 = global <2 x i64> zeroinitializer
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| bitwise.ll | 911 %2 = tail call <2 x i64> @llvm.ctpop.v2i64 (<2 x i64> %1)
967 %2 = tail call <2 x i64> @llvm.ctlz.v2i64 (<2 x i64> %1)
[all...] |
| /external/llvm/test/Transforms/SLPVectorizer/X86/ |
| bswap.ll | 31 ; AVX-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> [[TMP1]])
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86RegisterInfo.td | 460 def VR128 : RegisterClass<"X86", [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
|
| /external/webp/src/dsp/ |
| upsampling_msa.c | 184 out_m = __msa_copy_s_d((v2i64)out1, 0); \
|
