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  /external/libavc/common/arm/
ih264_intra_pred_luma_8x8_a9q.s 126 vaddl.u8 q9, d2, d6
127 vaddl.u8 q8, d6, d10
132 vqrshrun.s16 d6, q6, #2
133 vst1.8 {d6}, [r1]
661 vqrshrun.s16 d6, q12, #2
679 vst1.8 {d6[6]}, [r1], r3
781 vqrshrun.s16 d6, q12, #2
899 vqrshrun.s16 d6, q12, #2
908 vst1.8 {d6}, [r1], r3
1002 vqrshrun.s16 d6, q12, #
    [all...]
  /external/capstone/suite/MC/ARM/
neon-shift-encoding.s.cs 50 0x16,0x01,0xc9,0xf2 = vsra.s8 d16, d6, #7 package
66 0x16,0x01,0xc9,0xf3 = vsra.u8 d16, d6, #7 package
82 0x16,0x04,0xc9,0xf3 = vsri.8 d16, d6, #7 package
98 0x16,0x05,0xcf,0xf3 = vsli.8 d16, d6, #7 package
193 0x0d,0xd5,0x26,0xf2 = vrshl.s32 d13, d13, d6
213 0x16,0x60,0xa0,0xf3 = vshr.u32 d6, d6, #32 package
229 0x16,0x62,0xa0,0xf3 = vrshr.u32 d6, d6, #32 package
neon-v8.s.cs 6 0x06,0x40,0xbb,0xf3 = vcvta.s32.f32 d4, d6
  /external/libhevc/common/arm/
ihevc_inter_pred_luma_copy_w16out.s 193 vst1.16 {d6,d7},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp)
232 vst1.16 {d6,d7},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp)
248 vst1.16 {d6,d7},[r10],r5 @vst1q_s16(pi2_dst_tmp, tmp)
ihevc_intra_pred_chroma_horz.s 297 vdup.16 d6,d0[3]
303 vst1.8 {d6},[r2],r3
311 @vst1.8 {d6},[r2],r3
  /external/vixl/test/aarch32/
test-simulator-cond-dt-drt-drd-drn-drm-float-f64-a32.cc 507 {{F64, d6, d28, d7},
508 "F64 d6 d28 d7",
    [all...]
test-simulator-cond-dt-drt-drd-drn-drm-float-f64-t32.cc 507 {{F64, d6, d28, d7},
508 "F64 d6 d28 d7",
    [all...]
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/
vfp1_t2.d 138 0+200 <[^>]*> eeb5 6b40 (vcmp\.f64 d6, #0.0|fcmpzd d6)
155 0+240 <[^>]*> eeb0 6b4c (vmoveq\.f64|fcpydeq) d6, d12
162 0+25a <[^>]*> ee16 5b0b (vnmlseq\.f64|fmscdeq) d5, d6, d11
166 0+268 <[^>]*> ee16 7b4b (vnmlaeq\.f64|fnmscdeq) d7, d6, d11
179 0+296 <[^>]*> ed36 6b02 vldmdbeq r6!, {d6}
vldconst.s 119 vldr d6, =0x0000fff000000002
  /external/valgrind/none/tests/arm/
neon64.stdout.exp 54 vorr.i16 d6, #0x700 :: Qd 0x57555755 0x57555755
55 vorr.i16 d6, #0x700 :: Qd 0x07060704 0x07020700
143 vand d4, d6, d5 :: Qd 0x00570057 0x00570057 Qm (i8)0x000000ff Qn (i16)0x00000057
144 vand d4, d6, d5 :: Qd 0x00060004 0x00020000 Qm (i8)0x000000ff Qn (i16)0x00000057
152 vbic d4, d6, d5 :: Qd 0xffa8ffa8 0xffa8ffa8 Qm (i8)0x000000ff Qn (i16)0x00000057
153 vbic d4, d6, d5 :: Qd 0x07000500 0x03000100 Qm (i8)0x000000ff Qn (i16)0x00000057
179 veor d4, d6, d5 :: Qd 0xffa8ffa8 0xffa8ffa8 Qm (i8)0x000000ff Qn (i16)0x00000057
180 veor d4, d6, d5 :: Qd 0x07510553 0x03550157 Qm (i8)0x000000ff Qn (i16)0x00000057
196 vbsl d4, d6, d5 :: Qd 0x55575557 0x55575557 Qm (i8)0x000000ff Qn (i16)0x00000057
197 vbsl d4, d6, d5 :: Qd 0x05060506 0x01020102 Qm (i8)0x000000ff Qn (i16)0x0000005
    [all...]
  /frameworks/rs/cpu_ref/
rsCpuIntrinsics_neon_Blur.S 168 vertfetch_clamped 27, d6[3]
169 vertfetch_clamped 26, d6[2]
170 vertfetch_clamped 25, d6[1]
171 vertfetch_clamped 24, d6[0]
203 vertfetch_noclamp 27, d6[3]
204 vertfetch_noclamp 26, d6[2]
205 vertfetch_noclamp 25, d6[1]
206 vertfetch_noclamp 24, d6[0]
507 vmlal.u16 q14, d24, d6[1]
508 vmlal.u16 q15, d25, d6[1
    [all...]
  /external/clang/test/CXX/dcl.decl/dcl.init/dcl.init.list/
p7-0x.cpp 102 Agg<double> d6 = {1E315L}; // expected-error {{ cannot be narrowed }} expected-note {{silence}} local
p7-cxx11-nowarn.cpp 100 Agg<double> d6 = {1E315L}; // expected-warning {{ cannot be narrowed }} expected-note {{silence}} local
  /external/clang/test/Sema/
warn-unreachable.c 67 d6:
  /external/libhevc/common/arm64/
ihevc_intra_pred_luma_dc.s 172 uadalp v6.1d, v5.2s //accumulate all inp into d6 (end for nt==8)
190 uadalp v6.1d, v5.2s //accumulate all inp into d6
195 sshl d18, d6, d7 //(dc_val) shr by log2nt+1
446 add d6, d6 , d5 //accumulate all inp into d6 (end for nt==8)
448 sshl d18, d6, d7 //(dc_val) shr by log2nt+1
  /external/llvm/test/MC/ARM/
neon-mul-accum-encoding.s 62 vmls.i16 q4, q12, d6[2]
72 @ CHECK: vmls.i16 q4, q12, d6[2] @ encoding: [0xe6,0x84,0x98,0xf3]
neon-v8.s 12 vcvta.s32.f32 d4, d6
13 @ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0x06,0x40,0xbb,0xf3]
thumb-neon-v8.s 12 vcvta.s32.f32 d4, d6
13 @ CHECK: vcvta.s32.f32 d4, d6 @ encoding: [0xbb,0xff,0x06,0x40]
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/bfin/
flow2.d 45 54: d6 2f JUMP.S 0x0 .*
105 d6: e2 e0 04 10 LSETUP\(0xda <bottom_of_FIR_filter\+0xc>, 0xde <bottom_of_FIR_filter\+0x10>\) LC0 = P1 >> 0x1;
load.d 96 000000d6 <load_byte_zero_extend>:
97 d6: 05 99 R5 = B\[P0\] \(Z\);
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/crx/
load_stor_insn.d 83 d6: 78 56
103 10e: 0f d6 storw r6, 0x0\(r15\)
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/i386/
i386-intel.d 58 [ ]*[a-f0-9]+: 66 0f d6 0c 24 movq QWORD PTR \[esp\],xmm1
59 [ ]*[a-f0-9]+: 66 0f d6 0c 24 movq QWORD PTR \[esp\],xmm1
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/ppc/
altivec3.d 63 .*: (10 71 d6 02|02 d6 71 10) vextsh2w v3,v26
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/score/
branch_32.d 24 22a: 93ff 09d6 bgtu 0x0
124 1366: 93ff 11d6 beq 0x113c
174 1c04: 93ff 15d6 bne 0x19da
224 24a2: 93ff 19d6 bgt 0x2278
237 24d6: 9000 1a2e bgt 0x2704
322 35d6: 93ff 39de bcnz 0x33b4
324 35de: 93ff 39d6 bcnz 0x33b4
400 40d6: 9000 3c08 b 0x40de
tcond.d 157 1d6: 0805 tge!
238 2d6: 0e05 tcnz!

Completed in 801 milliseconds

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