1 @ Test file for ARM/GAS -- vldr reg, =... expressions. 2 .fpu neon 3 .text 4 .align 5 foo: 6 # test both low and high index of the 7 # Advanced SIMD and Floating-point reg. 8 .macro vlxr regtype const 9 .irp regindex, 0, 14, 28, 31 10 vldr \regtype\regindex, \const 11 .endr 12 .endm 13 14 .macro vlxreq regtype const 15 .irp regindex, 0, 14, 28, 31 16 vldreq \regtype\regindex, \const 17 .endr 18 .endm 19 20 .macro vlxrmi regtype const 21 .irp regindex, 0, 14, 28, 31 22 vldrmi \regtype\regindex, \const 23 .endr 24 .endm 25 26 vlxr s "=0" 27 vlxr s "=0xff000000" 28 vlxr s "=-1" 29 vlxr s "=0x0fff0000" 30 .pool 31 32 vlxr s "=0" 33 vlxr s "=0x00ff0000" 34 vlxr s "=0xff00ffff" 35 vlxr s "=0x00fff000" 36 .pool 37 38 vlxreq s "=0" 39 vlxreq s "=0x0000ff00" 40 vlxreq s "=0xffff00ff" 41 vlxreq s "=0x000fff00" 42 .pool 43 44 vlxrmi s "=0" 45 vlxrmi s "=0x000000ff" 46 vlxrmi s "=0xffffff00" 47 vlxrmi s "=0x0000fff0" 48 .pool 49 50 vlxr d "=0" 51 vlxr d "=0xca000000" 52 vlxr d "=-1" 53 vlxr d "=0x0fff0000" 54 .pool 55 56 vlxr d "=0" 57 vlxr d "=0x00ff0000" 58 vlxr d "=0xff0000ff" 59 vlxr d "=0x00fff000" 60 .pool 61 62 vlxreq d "=0" 63 vlxreq d "=0x0000ff00" 64 vlxreq d "=0xffff00ff" 65 vlxreq d "=0x000fff00" 66 .pool 67 68 vlxrmi d "=0" 69 vlxrmi d "=0x000000ff" 70 vlxrmi d "=0xffffff00" 71 vlxrmi d "=0x0000ffff" 72 .pool 73 74 vlxr d "=0" 75 vlxr d "=0xff00000000000000" 76 vlxr d "=-1" 77 vlxr d "=0x0fff000000000000" 78 .pool 79 80 vlxr d "=0" 81 vlxr d "=0x00ff00000000000" 82 vlxr d "=0xff00ffff0000000" 83 vlxr d "=0x00fff0000000000" 84 .pool 85 86 vlxreq d "=0" 87 vlxreq d "=0x0000ff0000000000" 88 vlxreq d "=0xffff00ff00000000" 89 vlxreq d "=0x000fff0000000000" 90 .pool 91 92 vlxrmi d "=0" 93 vlxrmi d "=0x000000ff00000000" 94 vlxrmi d "=0xffffff0000000000" 95 vlxrmi d "=0x0000fff000000000" 96 .pool 97 98 # pool should be aligned to 8-byte. 99 .p2align 3 100 vldr d1, =0x0000fff000000000 101 .pool 102 103 # no error when code is align already. 104 .p2align 3 105 add r0, r1, #0 106 vldr d1, =0x0000fff000000000 107 .pool 108 109 .p2align 3 110 vldr d1, =0x0000fff000000000 111 vldr s2, =0xff000000 112 # padding A 113 vldr d3, =0x0000fff000000001 114 # reuse padding slot A 115 vldr s4, =0xff000001 116 # reuse d3 117 vldr d5, =0x0000fff000000001 118 # new 8-byte entry 119 vldr d6, =0x0000fff000000002 120 # new 8-byte entry 121 vldr d7, =0x0000fff000000003 122 # new 4-byte entry 123 vldr s8, =0xff000002 124 # padding B 125 vldr d9, =0x0000fff000000004 126 # reuse padding slot B 127 vldr s10, =0xff000003 128 # new 8-byte entry 129 vldr d11, =0x0000fff000000005 130 # new 4 entry 131 vldr s12, =0xff000004 132 # new 4 entry 133 vldr s13, =0xff000005 134 # reuse value of s4 in pool 135 vldr s14, =0xff000001 136 # reuse high part of d1 in pool 137 vldr s15, =0x0000fff0 138 # 8-byte entry reuse two 4-byte entries. 139 # this reuse should only happen for 140 # little-endian 141 # d16 reuse s12, s13 142 vldr d16, =0xff000005ff000004 143 # d17 should not reuse high part of d11 and s12. 144 # because the it's align 8-byte aligned. 145 vldr d17, =0xff0000040000fff0 146 .pool 147
