| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| armv8-a-it-bad.l | 10 .*:52: IT blocks containing 16-bit Thumb instructions of the following class are deprecated in ARMv8: Hi-register ADD, MOV, CMP, BX, BLX using pc
|
| /prebuilts/go/darwin-x86/src/crypto/sha256/ |
| sha256block_amd64.s | 74 MOVL ((index-15)*4)(BP), BX; \
76 MOVL BX, CX; \
78 RORL $7, BX; \
83 XORL CX, BX; \
84 XORL DX, BX; \
85 ADDL ((index-16)*4)(BP), BX; \
86 ADDL BX, AX; \
114 // Calculate T2 in BX - uses BX, CX, DX and DI registers.
120 MOVL c, BX; \
[all...] |
| /prebuilts/go/linux-x86/src/crypto/sha256/ |
| sha256block_amd64.s | 74 MOVL ((index-15)*4)(BP), BX; \
76 MOVL BX, CX; \
78 RORL $7, BX; \
83 XORL CX, BX; \
84 XORL DX, BX; \
85 ADDL ((index-16)*4)(BP), BX; \
86 ADDL BX, AX; \
114 // Calculate T2 in BX - uses BX, CX, DX and DI registers.
120 MOVL c, BX; \
[all...] |
| /device/linaro/bootloader/edk2/IntelFrameworkModulePkg/Csm/LegacyBiosDxe/ |
| LegacyBios.c | 134 Regs.X.BX = (UINT16) Region;
147 *LegacyMemoryAddress = (VOID *) (UINTN) ((Regs.X.DS << 4) + Regs.X.BX);
423 Regs.X.BX = EFI_OFFSET (*((UINT32 *) &EfiToLegacy16InitTable));
470 Table->E820Pointer = (UINT32) (Regs.X.DS * 16 + Regs.X.BX);
531 TpmPointer = (UINT32) (Regs.X.DS * 16 + Regs.X.BX);
537 Table->TpmOffset = Regs.X.BX;
664 // presence of the PCI function set. [BX] will further indicate the version level, with enough
670 PciInterfaceVersion = Reg.X.BX;
[all...] |
| Thunk.c | 189 ThunkRegSet.X.BX = Regs->X.BX;
|
| LegacyBootSupport.c | 695 Regs.X.BX = (UINT16) Location;
724 Regs.X.BX
729 Legacy16Table->MpTablePtr = (UINT32) (Regs.X.DS * 16 + Regs.X.BX);
739 Legacy16Table->OemIntOffset = Regs.X.BX;
747 Legacy16Table->Oem32Offset = Regs.X.BX;
756 // Legacy16Table->Oem16Offset = Regs.X.BX;
773 TablePtr = (UINT32) (Regs.X.DS * 16 + Regs.X.BX);
948 Private->Legacy16Table->E820Pointer = (UINT32) (Regs.X.DS * 16 + Regs.X.BX);
[all...] |
| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| X86MCTargetDesc.cpp | 78 X86::DH, X86::BH, X86::AX, X86::CX, X86::DX, X86::BX,
299 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
311 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
348 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
349 return X86::BX;
384 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
420 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.cpp | 618 uint16_t BX = im(2);
619 RC[BX] = RC[BX].is(0) ? BT::BitValue::One
620 : RC[BX].is(1) ? BT::BitValue::Zero
627 uint16_t BX = im(2);
628 // Res.uw[1] = Rs[bx+1:], Res.uw[0] = Rs[0:bx]
630 RegisterCell RZ = RegisterCell(W0).fill(BX, W1, Zero)
631 .fill(W1+(W1-BX), W0, Zero);
632 RegisterCell BF1 = eXTR(rc(1), 0, BX), BF2 = eXTR(rc(1), BX, W1)
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/x86/ |
| obj6.go | 118 // MOVQ TLS, BX
119 // ... off(BX)(TLS*1) ...
144 // MOVQ 0(TLS), BX
146 // MOVQ TLS, BX
147 // MOVQ 0(BX)(TLS*1), BX
420 // to a PLT, so make sure the GOT pointer is loaded into BX.
721 // MOVQ g_panic(CX), BX
722 // TESTQ BX, BX
[all...] |
| /prebuilts/go/linux-x86/src/cmd/internal/obj/x86/ |
| obj6.go | 118 // MOVQ TLS, BX
119 // ... off(BX)(TLS*1) ...
144 // MOVQ 0(TLS), BX
146 // MOVQ TLS, BX
147 // MOVQ 0(BX)(TLS*1), BX
420 // to a PLT, so make sure the GOT pointer is loaded into BX.
721 // MOVQ g_panic(CX), BX
722 // TESTQ BX, BX
[all...] |
| /prebuilts/go/darwin-x86/src/crypto/elliptic/ |
| p256_asm_amd64.s | 1027 MOVQ n+48(FP), BX
1272 DECQ BX
1292 #define acc0 BX
1729 MOVQ in1+24(FP), BX
1735 MOVOU (16*0)(BX), X0
1736 MOVOU (16*1)(BX), X1
1737 MOVOU (16*2)(BX), X2
1738 MOVOU (16*3)(BX), X3
1739 MOVOU (16*4)(BX), X4
1740 MOVOU (16*5)(BX), X
[all...] |
| /prebuilts/go/linux-x86/src/crypto/elliptic/ |
| p256_asm_amd64.s | 1027 MOVQ n+48(FP), BX
1272 DECQ BX
1292 #define acc0 BX
1729 MOVQ in1+24(FP), BX
1735 MOVOU (16*0)(BX), X0
1736 MOVOU (16*1)(BX), X1
1737 MOVOU (16*2)(BX), X2
1738 MOVOU (16*3)(BX), X3
1739 MOVOU (16*4)(BX), X4
1740 MOVOU (16*5)(BX), X
[all...] |
| /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Thunk16/ |
| Thunk16Lib.h | 129 UINT16 BX;
|
| /external/sonivox/arm-wt-22k/lib_src/ |
| ARM-E_mastergain_gnu.s | 102 BX lr
|
| /external/syslinux/gpxe/src/arch/i386/drivers/net/ |
| undiload.c | 64 undi_loader.BX = undi->isapnp_csn;
|
| /device/linaro/bootloader/edk2/DuetPkg/BootSector/ |
| Gpt.asm | 56 mov bx, 07c00h ; BX = 0x7C00
62 lea si, [bx+si] ; BX = 0x7C00 + Offset(RelocatedStart)
64 mov sp, bx ; SP = 0x7C00
108 mov bx, 1 ; Read 1 Block
138 mov bx, 1 ; Read 1 Block
160 mov bx, 1 ; Read 1 Block
176 ; BX = Number of Blocks to Read (must < 127)
|
| Mbr.asm | 56 mov bx, 07c00h ; BX = 0x7C00
62 lea si, [bx+si] ; BX = 0x7C00 + Offset(RelocatedStart)
64 mov sp, bx ; SP = 0x7C00
145 mov bx, 7c00h ; ES:BX = 0000:7C00h
|
| Gpt.S | 57 movw $0x7c00, %bx # BX = 0x7C00
63 leaw (%bx,%si,), %si # BX = 0x7C00 + Offset(RelocatedStart)
65 movw %bx, %sp # SP = 0x7C00
110 movw $1, %bx # Read 1 Block
140 movw $1, %bx # Read 1 Block
162 movw $1, %bx # Read 1 Block
178 # BX = Number of Blocks to Read (must < 127)
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssembler.cpp | 148 BX(AL, LR);
156 BX(AL, LR);
274 void ARMAssembler::BX(int cc, int Rn)
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86RegisterInfo.cpp | 675 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
687 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
724 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
725 return X86::BX;
760 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
796 case X86::BH: case X86::BL: case X86::BX: case X86::EBX: case X86::RBX:
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/ |
| SmiEntry.S | 63 # The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
66 # base address register, it is actually BX that is referenced.
68 .byte 0xbb # mov bx, imm16
77 movl %eax, (%rdi) # mov cs:[bx], ax
|
| /device/linaro/bootloader/edk2/UefiCpuPkg/PiSmmCpuDxeSmm/X64/ |
| SmiEntry.S | 62 # The encoding of BX in 16-bit addressing mode is the same as of RDI in 64-
65 # base address register, it is actually BX that is referenced.
67 .byte 0xbb # mov bx, imm16
76 movl %eax, (%rdi) # mov cs:[bx], ax
|
| /external/aac/libFDK/src/arm/ |
| dct_arm.cpp | 247 BX lr
467 POP{r4 - r9} BX lr
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 370 baseReg = MCOperand::CreateReg(X86::BX);
374 baseReg = MCOperand::CreateReg(X86::BX);
|
| X86DisassemblerDecoder.h | 96 ENTRY(BX) \
110 ENTRY(BX) \
|
