| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 34 static unsigned translateShiftImm(unsigned imm) {
36 assert((imm & ~0x1f) == 0 && "Invalid shift encoding");
38 if (imm == 0)
40 return imm;
56 O << "<imm:";
121 O << ", " << markup("<imm:") << "#"
279 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">");
330 O << markup("<imm:") << "#-" << formatImm(-OffImm) << markup(">");
332 O << markup("<imm:") << "#" << formatImm(OffImm) << markup(">");
341 // REG 0 IMM,SH_OPC - e.g. R5, LSL #
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 82 unsigned &Reg, unsigned &Imm,
159 /// getLdStSORegOpValue - Return encoding info for 'reg +/- reg shop imm'
429 /// getAddrModeImmOpValue - Return encoding info for 'reg +/- imm' operand.
432 unsigned &Imm, SmallVectorImpl<MCFixup> &Fixups) const {
453 Imm = SImm;
845 // {20-16} = imm{15-12}
846 // {11-0} = imm{11-0}
[all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | 370 uint64_t Imm = CI->getZExtValue();
375 isPowerOf2_64(Imm)) {
376 Imm = Log2_64(Imm);
381 Op0IsKill, Imm, VT.getSimpleVT());
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceAssemblerMIPS32.h | 79 uint32_t Imm, const char *InsnName);
86 uint32_t Imm, const char *InsnName);
120 void addi(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
128 void addiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
135 void andi(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
253 void ori(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
265 void slti(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
267 void sltiu(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
311 void xori(const Operand *OpRt, const Operand *OpRs, const uint32_t Imm);
|
| /external/llvm/include/llvm/Analysis/ |
| TargetTransformInfoImpl.h | 200 bool isLegalAddImmediate(int64_t Imm) { return false; }
202 bool isLegalICmpImmediate(int64_t Imm) { return false; }
260 int getIntImmCodeSizeCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
265 unsigned getIntImmCost(const APInt &Imm, Type *Ty) { return TTI::TCC_Basic; }
267 unsigned getIntImmCost(unsigned Opcode, unsigned Idx, const APInt &Imm,
272 unsigned getIntImmCost(Intrinsic::ID IID, unsigned Idx, const APInt &Imm,
|
| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCCodeEmitter.cpp | 218 // Encode (imm, reg) as a memri, which has the low 16-bits as the
237 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
255 // Encode (imm, reg) as a memrix16, which has the low 12-bits as the
270 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
277 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 3;
278 return reverseBits(Imm | RegBits) >> 22;
286 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
293 uint32_t Imm = getMachineOpValue(MI, MO, Fixups, STI) >> 2
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 97 } Imm;
121 Imm = o.Imm;
148 return Imm.Val;
240 Op->Imm.Val = Val;
248 Op->Imm.Val = Val;
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| FastISel.h | 339 bool Op0IsKill, uint64_t Imm);
347 uint64_t Imm, MVT ImmType);
351 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
387 bool Op0IsKill, uint64_t Imm);
406 uint64_t Imm);
411 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| FastISel.h | 339 bool Op0IsKill, uint64_t Imm);
347 uint64_t Imm, MVT ImmType);
351 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
387 bool Op0IsKill, uint64_t Imm);
406 uint64_t Imm);
411 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/CodeGen/ |
| FastISel.h | 364 bool Op0IsKill, uint64_t Imm);
372 uint64_t Imm, MVT ImmType);
376 virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
412 bool Op0IsKill, uint64_t Imm);
431 uint64_t Imm);
436 const TargetRegisterClass *RC, uint64_t Imm);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 40 int AArch64TTIImpl::getIntImmCost(const APInt &Imm, Type *Ty) {
48 APInt ImmVal = Imm;
50 ImmVal = Imm.sext((BitSize + 63) & ~0x3fU);
65 const APInt &Imm, Type *Ty) {
122 int Cost = AArch64TTIImpl::getIntImmCost(Imm, Ty);
127 return AArch64TTIImpl::getIntImmCost(Imm, Ty);
131 const APInt &Imm, Type *Ty) {
151 int Cost = AArch64TTIImpl::getIntImmCost(Imm, Ty);
158 if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue()))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 113 SDValue XformMskToBitPosU5Imm(uint32_t Imm, const SDLoc &DL) {
115 bitPos = Log2_32(Imm);
123 SDValue XformMskToBitPosU4Imm(uint16_t Imm, const SDLoc &DL) {
124 return XformMskToBitPosU5Imm(Imm, DL);
129 SDValue XformMskToBitPosU3Imm(uint8_t Imm, const SDLoc &DL) {
130 return XformMskToBitPosU5Imm(Imm, DL);
142 inline SDValue XformM5ToU5Imm(signed Imm, const SDLoc &DL) {
143 assert((Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
144 return CurDAG->getTargetConstant(-Imm, DL, MVT::i32)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 114 uint64_t Imm);
119 uint64_t Imm);
122 uint64_t Imm);
331 uint64_t Imm) {
342 .addImm(Imm));
346 .addImm(Imm));
358 uint64_t Imm) {
371 .addImm(Imm));
376 .addImm(Imm));
386 uint64_t Imm) {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 304 /// result of adding register REG and immediate IMM.
305 unsigned Mips16InstrInfo::loadImmediate(unsigned FrameReg, int64_t Imm,
323 int32_t lo = Imm & 0xFFFF;
385 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
439 const MCInstrDesc &Mips16InstrInfo::AddiuSpImm(int64_t Imm) const {
440 if (validSpImm8(Imm))
447 (MachineBasicBlock &MBB, MachineBasicBlock::iterator I, int64_t Imm) const {
449 BuildMI(MBB, I, DL, AddiuSpImm(Imm)).addImm(Imm);
|
