/external/llvm/lib/Target/ARM/ |
ARMTargetMachine.cpp | 203 Subtarget(TT, CPU, FS, *this, isLittle), isLittle(isLittle) { 208 Subtarget.isTargetHardFloat() ? FloatABI::Hard : FloatABI::Soft; 214 if (Subtarget.isTargetGNUAEABI() || Subtarget.isTargetMuslAEABI()) 237 // function before we can generate a subtarget. We also need to use 238 // it as a key for the subtarget since that can be the only difference 243 // subtarget feature. 249 // This needs to be done before we create a new subtarget since any 274 if (!Subtarget.hasARMOps()) 275 report_fatal_error("CPU: '" + Subtarget.getCPUString() + "' does not [all...] |
ARMFastISel.cpp | 75 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 77 const ARMSubtarget *Subtarget; 92 Subtarget( 95 TM(funcInfo.MF->getTarget()), TII(*Subtarget->getInstrInfo()), 96 TLI(*Subtarget->getTargetLowering()) { 451 if (!Subtarget->hasVFP2()) return false; 479 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { 491 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { 508 if (Subtarget->useMovt(*FuncInfo.MF)) 549 bool IsIndirect = Subtarget->isGVIndirectSymbol(GV) [all...] |
ARMAsmPrinter.cpp | 91 (Subtarget->isTargetELF() 105 Subtarget = &MF.getSubtarget<ARMSubtarget>(); 138 if (Subtarget->isTargetCOFF()) { 565 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() || 566 Subtarget->isTargetMuslAEABI())) 573 static bool isV8M(const ARMSubtarget *Subtarget) { 575 return (Subtarget->hasV8MBaselineOps() && !Subtarget->hasV6T2Ops()) || 576 Subtarget->hasV8MMainlineOps() [all...] |
ARMBaseInstrInfo.h | 32 const ARMSubtarget &Subtarget; 112 const ARMSubtarget &getSubtarget() const { return Subtarget; } 170 const ARMSubtarget &Subtarget) const; 173 const ARMSubtarget &Subtarget) const; 498 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
MipsRegisterInfo.cpp | 46 : MipsGenRegisterInfo(Mips::RA), Subtarget(ST), TII(tii) {} 179 if (Subtarget.isSingleFloat()) 181 else if (!Subtarget.hasMips64()) 183 else if (Subtarget.isABI_N32()) 186 assert(Subtarget.isABI_N64()); 208 if (Subtarget.hasMips64()) {
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MipsISelLowering.cpp | 86 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 87 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()) { 102 if (!Subtarget->isSingleFloat()) { 159 if (!Subtarget->hasMips32r2()) 162 if (!Subtarget->hasMips64r2()) 203 if (Subtarget->isSingleFloat()) 206 if (!Subtarget->hasSEInReg()) { 211 if (!Subtarget->hasBitCount()) 214 if (!Subtarget->hasSwap() [all...] |
MipsAsmPrinter.cpp | 203 switch (Subtarget->getTargetABI()) { 426 if (Subtarget->isABI_EABI()) { 427 if (Subtarget->isGP32bit())
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MipsISelDAGToDAG.cpp | 52 /// Subtarget - Keep a pointer to the MipsSubtarget around so that we can 54 const MipsSubtarget &Subtarget; 59 TM(tm), Subtarget(tm.getSubtarget<MipsSubtarget>()) {} 271 if (Subtarget.hasMips32() && Node->getValueType(0) == MVT::i32)
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMISelDAGToDAG.cpp | 70 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 72 const ARMSubtarget *Subtarget; 79 Subtarget(&TM.getSubtarget<ARMSubtarget>()) { 344 if (!Subtarget->isCortexA8() && !Subtarget->isCortexA9()) 382 if (!Subtarget->isCortexA9()) 458 !(Subtarget->useMovt() && 494 (!Subtarget->isCortexA9() || N.hasOneUse())) { 558 !(Subtarget->isCortexA9() || N.getOperand(0).hasOneUse())) { 594 (!Subtarget->isCortexA9() || N.hasOneUse())) [all...] |
ARMSelectionDAGInfo.cpp | 22 Subtarget(&TM.getSubtarget<ARMSubtarget>()) { 41 // within a subtarget-specific limit. 46 if (!AlwaysInline && SizeVal > Subtarget->getMaxInlineSizeThreshold()) 148 if (!Subtarget->isAAPCS_ABI())
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ARMISelLowering.cpp | 178 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 184 if (Subtarget->isTargetDarwin()) { 186 if (Subtarget->isThumb() && Subtarget->hasVFP2()) { 266 if (Subtarget->isAAPCS_ABI()) { 426 if (Subtarget->getTargetTriple().getOS() == Triple::IOS && 427 !Subtarget->getTargetTriple().isOSVersionLT(5, 0)) { 432 if (Subtarget->isThumb1Only()) 436 if (!UseSoftFloat && Subtarget->hasVFP2() && !Subtarget->isThumb1Only()) [all...] |
ARMFastISel.cpp | 84 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 86 const ARMSubtarget *Subtarget; 102 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 522 if (!Subtarget->hasVFP2()) return false; 552 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getSExtValue())) { 599 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8); 624 if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) { [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64CallingConvention.h | 130 const AArch64Subtarget &Subtarget = static_cast<const AArch64Subtarget &>( 132 unsigned SlotAlign = Subtarget.isTargetDarwin() ? 1 : 8;
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/external/llvm/lib/Target/Mips/ |
MipsCCState.cpp | 59 const MipsSubtarget &Subtarget) { 61 if (Subtarget.inMips16HardFloat()) {
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MipsISelDAGToDAG.cpp | 50 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); 225 assert((Subtarget->systemSupportsUnalignedAccess() ||
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MipsInstrInfo.cpp | 34 Subtarget(STI), UncondBrOpc(UncondBr) {} 268 if (Subtarget.inMicroMipsMode()) { 274 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg()) 288 if (Subtarget.hasMips32r6() && (I->getNumOperands() > 1) && 297 if (Subtarget.hasMips32r6() || canUseShortMicroMipsCTI) { 406 // Subtarget.getABI().GetZeroReg() when those atomic sequences and others
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MipsLongBranch.cpp | 262 const MipsSubtarget &Subtarget = 265 static_cast<const MipsInstrInfo *>(Subtarget.getInstrInfo()); 279 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR; 336 if (Subtarget.isTargetNaCl()) 340 if (Subtarget.hasMips32r6()) 346 if (Subtarget.isTargetNaCl()) { 413 if (Subtarget.hasMips64r6())
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Mips16ISelDAGToDAG.cpp | 39 Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget()); 40 if (!Subtarget->inMips16Mode()) 74 const TargetInstrInfo &TII = *Subtarget->getInstrInfo();
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/external/llvm/lib/Target/Sparc/ |
SparcInstrInfo.cpp | 37 Subtarget(ST) {} 330 if (Subtarget.isV9()) { 340 if (Subtarget.isV9()) { 341 if (Subtarget.hasHardQuad()) { 481 Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass; 494 assert(Subtarget.isTargetLinux() && 497 const int64_t Offset = Subtarget.is64Bit() ? 0x28 : 0x14; 498 MI.setDesc(get(Subtarget.is64Bit() ? SP::LDXri : SP::LDri));
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SparcISelLowering.cpp | 200 if (Subtarget->is64Bit()) 371 if (Subtarget->is64Bit()) 671 Subtarget->getStackPointerBias()); 696 if (Subtarget->is64Bit()) [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
PTXSelectionDAGInfo.cpp | 22 Subtarget(&TM.getSubtarget<PTXSubtarget>()) { 41 // within a subtarget-specific limit. 61 EVT PointerType = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
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/external/llvm/lib/Target/PowerPC/ |
PPCFrameLowering.h | 25 const PPCSubtarget &Subtarget;
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/external/llvm/lib/Target/Lanai/ |
LanaiDelaySlotFiller.cpp | 50 const LanaiSubtarget &Subtarget = MF.getSubtarget<LanaiSubtarget>(); 51 TII = Subtarget.getInstrInfo(); 52 TRI = Subtarget.getRegisterInfo();
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/external/llvm/lib/Target/X86/ |
X86TargetMachine.cpp | 61 llvm_unreachable("unknown subtarget type"); 155 Subtarget(TT, CPU, FS, *this, Options.StackAlignmentOverride) { 162 if (Subtarget.isTargetWin64() || Subtarget.isTargetPS4()) 199 // function before we can generate a subtarget. We also need to use 200 // it as a key for the subtarget since that can be the only difference 205 // subtarget feature. 213 // This needs to be done before we create a new subtarget since any
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
PPCFrameLowering.cpp | 204 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 205 Subtarget.isDarwinABI()); 288 bool isPPC64 = Subtarget.isPPC64(); 290 bool isDarwinABI = Subtarget.isDarwinABI(); 301 if (Subtarget.isSVR4ABI()) { 531 bool isPPC64 = Subtarget.isPPC64(); 533 bool isDarwinABI = Subtarget.isDarwinABI(); 544 if (Subtarget.isSVR4ABI()) { 745 bool isPPC64 = Subtarget.isPPC64(); 746 bool isDarwinABI = Subtarget.isDarwinABI() [all...] |