| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neont2-mul-encoding.s | 7 @ CHECK: vmul.i16 d16, d16, d17 @ encoding: [0x50,0xef,0xb1,0x09]
8 vmul.i16 d16, d16, d17
15 @ CHECK: vmul.i16 q8, q8, q9 @ encoding: [0x50,0xef,0xf2,0x09]
16 vmul.i16 q8, q8, q9
|
| neon-sub-encoding.s | 5 @ CHECK: vsub.i16 d16, d17, d16 @ encoding: [0xa0,0x08,0x51,0xf3]
6 vsub.i16 d16, d17, d16
15 @ CHECK: vsub.i16 q8, q8, q9 @ encoding: [0xe2,0x08,0x50,0xf3]
16 vsub.i16 q8, q8, q9
97 @ CHECK: vsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf2]
98 vsubhn.i16 d16, q8, q9
103 @ CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3]
104 vrsubhn.i16 d16, q8, q9
|
| neont2-shift-encoding.s | 15 @ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0xdf,0xef,0x30,0x05]
16 vshl.i16 d16, d16, #15
31 @ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0xdf,0xef,0x70,0x05]
32 vshl.i16 q8, q8, #15
83 @ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0xf6,0xff,0x20,0x03]
84 vshll.i16 q8, d16, #16
87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
157 @ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x08]
158 vrshrn.i16 d16, q8, #
[all...] |
| /frameworks/av/media/libaudioprocessing/ |
| AudioResampler.cpp | 367 mX0L = mBuffer.i16[mBuffer.frameCount*2-2];
368 mX0R = mBuffer.i16[mBuffer.frameCount*2-1];
373 int16_t *in = mBuffer.i16;
417 mX0L = mBuffer.i16[mBuffer.frameCount*2-2];
418 mX0R = mBuffer.i16[mBuffer.frameCount*2-1];
464 mX0L = mBuffer.i16[mBuffer.frameCount-1];
468 int16_t *in = mBuffer.i16;
514 mX0L = mBuffer.i16[mBuffer.frameCount-1];
|
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/gc/ |
| float_test.go | 258 i64, i32, i16, i8 := int64(-1<<63), int32(-1<<31), int16(-1<<15), int8(-1<<7)
283 if float64(i16) != di16 {
284 t.Errorf("float64(i16) != di16")
307 if float32(i16) != si16 {
308 t.Errorf("float32(i16) != si16")
333 if int16(di16) != i16 {
334 t.Errorf("int16(di16) != i16")
357 if int16(si16) != i16 {
358 t.Errorf("int16(si16) != i16")
|
| /prebuilts/go/linux-x86/src/cmd/compile/internal/gc/ |
| float_test.go | 258 i64, i32, i16, i8 := int64(-1<<63), int32(-1<<31), int16(-1<<15), int8(-1<<7)
283 if float64(i16) != di16 {
284 t.Errorf("float64(i16) != di16")
307 if float32(i16) != si16 {
308 t.Errorf("float32(i16) != si16")
333 if int16(di16) != i16 {
334 t.Errorf("int16(di16) != i16")
357 if int16(si16) != i16 {
358 t.Errorf("int16(si16) != i16")
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| neon-cov.s | 88 regs2i_1 \op \opq \imm .i16
129 logic_imm_1 \op \opq 0x00ff .i16
130 logic_imm_1 \op \opq 0xff00 .i16
152 logic_imm_1 \op \opq 0xff00 .i16
153 logic_imm_1 \op \opq 0x00ff .i16
176 regs3_1 \op \opq .i16
208 regs2i_1 \op \opq 0 .i16
244 regs3_1 \op \opq .i16
249 sclr21_1 \op \opq .i16
261 dregs3_1 \op .i16
[all...] |
| neon-cov.d | 293 0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
294 0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
295 0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
296 0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
297 0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa500
298 0[0-9a-f]+ <[^>]+> f3820b35 vbic\.i16 d0, #42240 ; 0xa500
317 0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
318 0[0-9a-f]+ <[^>]+> f3820975 vbic\.i16 q0, #165 ; 0x00a5
319 0[0-9a-f]+ <[^>]+> f3820935 vbic\.i16 d0, #165 ; 0x00a5
320 0[0-9a-f]+ <[^>]+> f3820b75 vbic\.i16 q0, #42240 ; 0xa50
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_filters_luma_mode_11_to_17.s | 330 vrshrn.i16 d24, q12, #5 @round shft (row 0)
341 vrshrn.i16 d22, q11, #5 @round shft (row 1)
352 vrshrn.i16 d20, q10, #5 @round shft (row 2)
363 vrshrn.i16 d18, q9, #5 @round shft (row 3)
374 vrshrn.i16 d24, q12, #5 @round shft (row 4)
385 vrshrn.i16 d22, q11, #5 @round shft (row 5)
396 vrshrn.i16 d20, q10, #5 @round shft (row 6)
397 vrshrn.i16 d18, q9, #5 @round shft (row 7)
453 vrshrn.i16 d24, q11, #5 @round shft (row 5)
474 vrshrn.i16 d20, q10, #5 @(from previous loop)round shft (row 6
[all...] |
| ihevc_intra_pred_luma_mode_3_to_9.s | 220 vrshrn.i16 d24, q12, #5 @round shft (row 0)
231 vrshrn.i16 d22, q11, #5 @round shft (row 1)
242 vrshrn.i16 d20, q10, #5 @round shft (row 2)
253 vrshrn.i16 d18, q9, #5 @round shft (row 3)
264 vrshrn.i16 d24, q12, #5 @round shft (row 4)
275 vrshrn.i16 d22, q11, #5 @round shft (row 5)
286 vrshrn.i16 d20, q10, #5 @round shft (row 6)
287 vrshrn.i16 d18, q9, #5 @round shft (row 7)
343 vrshrn.i16 d22, q11, #5 @round shft (row 5)
365 vrshrn.i16 d20, q10, #5 @(from previous loop)round shft (row 6
[all...] |
| ihevc_intra_pred_filters_chroma_mode_11_to_17.s | 332 vrshrn.i16 d24, q12, #5 @round shft (row 0)
343 vrshrn.i16 d22, q11, #5 @round shft (row 1)
354 vrshrn.i16 d20, q10, #5 @round shft (row 2)
365 vrshrn.i16 d18, q9, #5 @round shft (row 3)
378 vrshrn.i16 d24, q12, #5 @round shft (row 4)
389 vrshrn.i16 d22, q11, #5 @round shft (row 5)
400 vrshrn.i16 d20, q10, #5 @round shft (row 6)
401 vrshrn.i16 d18, q9, #5 @round shft (row 7)
463 vrshrn.i16 d24, q11, #5 @round shft (row 5)
492 vrshrn.i16 d20, q10, #5 @(from previous loop)round shft (row 6
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 48 if (VT==MVT::i16) retval=2;
108 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
115 // SPU has no sign or zero extended loads for i1, i8, i16:
125 setTruncStoreAction(MVT::i128, MVT::i16, Expand);
171 setOperationAction(ISD::SELECT_CC, MVT::i16, Custom);
186 setOperationAction(ISD::SREM, MVT::i16, Expand);
187 setOperationAction(ISD::UREM, MVT::i16, Expand);
188 setOperationAction(ISD::SDIV, MVT::i16, Expand);
189 setOperationAction(ISD::UDIV, MVT::i16, Expand);
190 setOperationAction(ISD::SDIVREM, MVT::i16, Expand)
[all...] |
| /external/flatbuffers/tests/MyGame/Example/ |
| TypeAliases.php | 191 public static function createTypeAliases(FlatBufferBuilder $builder, $i8, $u8, $i16, $u16, $i32, $u32, $i64, $u64, $f32, $f64, $v8, $vf64)
196 self::addI16($builder, $i16);
235 public static function addI16(FlatBufferBuilder $builder, $i16)
237 $builder->addShortX(2, $i16, 0);
|
| /external/libmpeg2/common/arm/ |
| impeg2_mem_func.s | 151 vmov.i16 q0, #0
|
| /prebuilts/go/darwin-x86/test/ |
| bounds.go | 27 i16 int16
70 use(s[i16])
71 use(a1[i16])
72 use(a1k[i16])
73 use(a100k[i16])
74 use(p1[i16])
75 use(p1k[i16])
76 use(p100k[i16])
26 i16 int16 var
|
| /prebuilts/go/linux-x86/test/ |
| bounds.go | 27 i16 int16
70 use(s[i16])
71 use(a1[i16])
72 use(a1k[i16])
73 use(a100k[i16])
74 use(p1[i16])
75 use(p1k[i16])
76 use(p100k[i16])
26 i16 int16 var
|
| /external/libavc/encoder/arm/ |
| ih264e_evaluate_intra4x4_modes_a9q.s | 159 vadd.i16 d28, d29, d28
185 vadd.i16 d28, d29, d28
221 vadd.i16 d28, d29, d28
270 vadd.i16 d28, d29, d28
299 vadd.i16 d28, d29, d28
337 vadd.i16 d28, d29, d28
374 vadd.i16 d28, d29, d28
402 vadd.i16 d28, d29, d28
427 vmov.i16 d28[0], r14
438 vadd.i16 d28, d29, d2
[all...] |
| ih264e_evaluate_intra16x16_modes_a9q.s | 183 vadd.i16 q9, q9, q8 @/VERT
184 vadd.i16 d18, d19, d18 @/VERT
186 vadd.i16 q14, q13, q14 @/HORZ
187 vadd.i16 d28, d29, d28 @/HORZ
193 vadd.i16 q12, q11, q12 @/DC
196 vadd.i16 d24, d24, d25 @/DC
|
| ih264e_evaluate_intra_chroma_modes_a9q.s | 237 vadd.i16 q9, q9, q8 @/VERT
238 vadd.i16 q7, q13, q7 @/HORZ
239 vadd.i16 q12, q11, q12 @/DC
240 vadd.i16 d18, d19, d18 @/VERT
241 vadd.i16 d14, d15, d14 @/HORZ
242 vadd.i16 d24, d24, d25 @/DC
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| loopfilter_16_neon.asm | 517 vsub.i16 q15, q10
519 vadd.i16 q15, q14
523 vsub.i16 q15, q10
524 vadd.i16 q15, q14
530 vadd.i16 q15, q14
536 vadd.i16 q15, q14
542 vadd.i16 q15, q14
565 vadd.i16 q12, q13
566 vadd.i16 q15, q14
568 vadd.i16 q15, q1
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | 746 case MVT::i16:
774 case MVT::i16:
803 case MVT::i16:
826 case MVT::i16:
855 case MVT::i16:
878 case MVT::i16:
992 case MVT::i16
[all...] |
| /external/llvm/test/MC/ARM/ |
| neont2-shift-encoding.s | 15 @ CHECK: vshl.i16 d16, d16, #15 @ encoding: [0xdf,0xef,0x30,0x05]
16 vshl.i16 d16, d16, #15
31 @ CHECK: vshl.i16 q8, q8, #15 @ encoding: [0xdf,0xef,0x70,0x05]
32 vshl.i16 q8, q8, #15
83 @ CHECK: vshll.i16 q8, d16, #16 @ encoding: [0xf6,0xff,0x20,0x03]
84 vshll.i16 q8, d16, #16
87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
157 @ CHECK: vrshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x70,0x08]
158 vrshrn.i16 d16, q8, #
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| BlackfinISelLowering.cpp | 51 addRegisterClass(MVT::i16, BF::D16RegisterClass);
67 // i16 registers don't do much
68 setOperationAction(ISD::AND, MVT::i16, Promote);
69 setOperationAction(ISD::OR, MVT::i16, Promote);
70 setOperationAction(ISD::XOR, MVT::i16, Promote);
71 setOperationAction(ISD::CTPOP, MVT::i16, Promote);
74 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
75 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
76 setOperationAction(ISD::SETCC, MVT::i16, Promote);
79 setOperationAction(ISD::SDIV, MVT::i16, Expand)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXSelectionDAGInfo.cpp | 101 VT = MVT::i16;
123 VT = MVT::i16;
|
| /frameworks/av/media/mtp/ |
| MtpProperty.cpp | 82 mDefaultValue.u.i16 = defaultValue;
263 mMinimumValue.u.i16 = min;
264 mMaximumValue.u.i16 = max;
265 mStepSize.u.i16 = step;
314 mEnumValues[i].u.i16 = value;
400 buffer += std::to_string(value.u.i16);
452 if (!packet.getInt16(value.u.i16)) return false;
507 packet.putInt16(value.u.i16);
|
