| /external/tensorflow/tensorflow/contrib/lite/kernels/ |
| embedding_lookup_sparse.cc | 166 const int dim = dense_shape->data.i32[i];
188 int idx = ids->data.i32[i];
200 output_bucket += indices->data.i32[example_indices_offset + k] * stride;
201 stride *= dense_shape->data.i32[k];
|
| hashtable_lookup.cc | 116 pointer = bsearch(&(lookup->data.i32[i]), key->data.i32, num_rows,
|
| /frameworks/av/camera/ |
| CameraUtils.cpp | 56 int orientation = entry.data.i32[0];
|
| /frameworks/rs/script_api/ |
| rs_debug.spec | 28 t: i32, u32, i64, u64, f64
44 t: i32, u32, i64, u64
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 242 MVT::i32, AM.Disp,
245 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
248 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
252 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32,
255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32);
260 Segment = CurDAG->getRegister(0, MVT::i32);
270 /// i32.
272 return CurDAG->getTargetConstant(Imm, MVT::i32);
[all...] |
| X86ISelLowering.cpp | 107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32);
180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
229 addRegisterClass(MVT::i32, X86::GR32RegisterClass);
236 setTruncStoreAction(MVT::i64, MVT::i32, Expand);
239 setTruncStoreAction(MVT::i32, MVT::i16, Expand);
240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom);
275 // SSE has no i16 to fp conversion, only i32
[all...] |
| /external/llvm/test/MC/ARM/ |
| neont2-shift-encoding.s | 17 @ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0xff,0xef,0x30,0x05]
18 vshl.i32 d16, d16, #31
33 @ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0xff,0xef,0x70,0x05]
34 vshl.i32 q8, q8, #31
85 @ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0xfa,0xff,0x20,0x03]
86 vshll.i32 q8, d16, #32
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
159 @ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x70,0x08]
160 vrshrn.i32 d16, q8, #1
[all...] |
| neont2-mul-encoding.s | 7 vmul.i32 d16, d16, d17
11 vmul.i32 q8, q8, q9
19 @ CHECK: vmul.i32 d16, d16, d17 @ encoding: [0x60,0xef,0xb1,0x09]
23 @ CHECK: vmul.i32 q8, q8, q9 @ encoding: [0x60,0xef,0xf2,0x09]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neont2-shift-encoding.s | 17 @ CHECK: vshl.i32 d16, d16, #31 @ encoding: [0xff,0xef,0x30,0x05]
18 vshl.i32 d16, d16, #31
33 @ CHECK: vshl.i32 q8, q8, #31 @ encoding: [0xff,0xef,0x70,0x05]
34 vshl.i32 q8, q8, #31
85 @ CHECK: vshll.i32 q8, d16, #32 @ encoding: [0xfa,0xff,0x20,0x03]
86 vshll.i32 q8, d16, #32
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
159 @ CHECK: vrshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x70,0x08]
160 vrshrn.i32 d16, q8, #1
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelLowering.cpp | 126 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
132 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Expand);
133 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Expand);
134 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Expand);
135 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Expand);
136 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Expand);
137 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Expand);
138 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Expand);
139 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Expand);
140 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Expand)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 259 MVT::i32, AM.Disp,
262 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32,
266 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
270 Disp = CurDAG->getMCSymbol(AM.MCSym, MVT::i32);
273 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
275 Disp = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
278 Disp = CurDAG->getTargetConstant(AM.Disp, DL, MVT::i32);
283 Segment = CurDAG->getRegister(0, MVT::i32);
367 /// Return a target constant with the specified value, of type i32.
369 return CurDAG->getTargetConstant(Imm, DL, MVT::i32);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64ISelDAGToDAG.cpp | 276 Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32);
277 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32);
302 if (N.getValueType() == MVT::i32)
310 return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val,
357 Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32);
380 else if (SrcVT == MVT::i32)
392 else if (SrcVT == MVT::i32)
552 if (N.getValueType() == MVT::i32)
556 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32);
558 dl, MVT::i32, N, SubReg)
[all...] |
| AArch64ISelLowering.cpp | 57 static const MVT MVT_CC = MVT::i32;
71 addRegisterClass(MVT::i32, &AArch64::GPR32allRegClass);
108 setOperationAction(ISD::SETCC, MVT::i32, Custom);
113 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
117 setOperationAction(ISD::SELECT, MVT::i32, Custom);
121 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
138 setOperationAction(ISD::XOR, MVT::i32, Custom);
167 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
170 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
173 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 82 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
107 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
118 isPPC64 ? MVT::i64 : MVT::i32);
121 isPPC64 ? MVT::i64 : MVT::i32);
157 setOperationAction(ISD::SREM, MVT::i32, Expand);
158 setOperationAction(ISD::UREM, MVT::i32, Expand);
163 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
164 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand)
[all...] |
| /external/mesa3d/src/amd/common/ |
| ac_llvm_util.c | 160 ctx->i32 = LLVMIntTypeInContext(ctx->context, 32);
289 LLVMValueRef index = LLVMConstInt(ctx->i32, i, false);
358 LLVMConstInt(ctx->i32, 0, 0), "");
360 LLVMConstInt(ctx->i32, 1, 0), "");
362 LLVMConstInt(ctx->i32, 2, 0), "");
364 LLVMConstInt(ctx->i32, 3, 0), "");
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXISelLowering.cpp | 40 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
98 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 SDValue Index = DAG.getTargetConstant(i, MVT::i32);
309 else if (RegVT == MVT::i32) {
377 Ops[Ins.size()+3] = DAG.getTargetConstant(OutVals.size(), MVT::i32);
392 Ops[1] = DAG.getTargetConstant(Ins.size(), MVT::i32);
|
| PTXSelectionDAGInfo.cpp | 54 EVT VT = MVT::i32;
61 EVT PointerType = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
|
| /external/boringssl/src/crypto/poly1305/ |
| poly1305_arm_asm.S | 250 # asm 1: vshl.i32 >5y12=reg128#12,<y12=reg128#2,#2
251 # asm 2: vshl.i32 >5y12=q11,<y12=q1,#2
252 vshl.i32 q11,q1,#2
255 # asm 1: vshl.i32 >5y34=reg128#13,<y34=reg128#3,#2
256 # asm 2: vshl.i32 >5y34=q12,<y34=q2,#2
257 vshl.i32 q12,q2,#2
260 # asm 1: vadd.i32 >5y12=reg128#12,<5y12=reg128#12,<y12=reg128#2
261 # asm 2: vadd.i32 >5y12=q11,<5y12=q11,<y12=q1
262 vadd.i32 q11,q11,q1
265 # asm 1: vadd.i32 >5y34=reg128#13,<5y34=reg128#13,<y34=reg128#
[all...] |
| /external/llvm/test/Bindings/OCaml/ |
| irreader.ml | 37 let buf = MemoryBuffer.of_string "@foo = global i32 42" in
|
| /frameworks/av/media/mtp/ |
| MtpProperty.cpp | 88 mDefaultValue.u.i32 = defaultValue;
273 mMinimumValue.u.i32 = min;
274 mMaximumValue.u.i32 = max;
275 mStepSize.u.i32 = step;
320 mEnumValues[i].u.i32 = value;
406 buffer += std::to_string(value.u.i32);
460 if (!packet.getInt32(value.u.i32)) return false;
515 packet.putInt32(value.u.i32);
|
| /packages/apps/Test/connectivity/sl4n/rapidjson/include/rapidjson/msinttypes/ |
| stdint.h | 67 #define INT32_C(val) val##i32
278 #define INT32_C(val) val##i32
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| neon-addressing-bad.l | 30 [^:]*:38: Error: immediate out of range for shift -- `vshl.i32 d0,d0,#32'
|
| neon-cond-bad.l | 4 [^:]*:12: Error: instruction cannot be conditional -- `vmoveq\.i32 q0,#0'
5 [^:]*:13: Error: instruction cannot be conditional -- `vmoveq\.i32 d0,#0'
|
| /external/boringssl/ios-arm/crypto/fipsmodule/ |
| sha1-armv4-large.S | 525 vadd.i32 q8,q0,q14
527 vadd.i32 q9,q1,q14
529 vadd.i32 q10,q2,q14
539 vadd.i32 q13,q3,q14
562 vadd.i32 q8,q12,q12
586 vadd.i32 q13,q8,q14
609 vadd.i32 q9,q12,q12
633 vadd.i32 q13,q9,q14
655 vadd.i32 q10,q12,q12
679 vadd.i32 q13,q10,q1
[all...] |
| /external/boringssl/linux-arm/crypto/fipsmodule/ |
| sha1-armv4-large.S | 522 vadd.i32 q8,q0,q14
524 vadd.i32 q9,q1,q14
526 vadd.i32 q10,q2,q14
536 vadd.i32 q13,q3,q14
559 vadd.i32 q8,q12,q12
583 vadd.i32 q13,q8,q14
606 vadd.i32 q9,q12,q12
630 vadd.i32 q13,q9,q14
652 vadd.i32 q10,q12,q12
676 vadd.i32 q13,q10,q1
[all...] |
