1 //===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines a DAG pattern matching instruction selector for X86, 11 // converting from a legalized dag to a X86 dag. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "x86-isel" 16 #include "X86.h" 17 #include "X86InstrBuilder.h" 18 #include "X86MachineFunctionInfo.h" 19 #include "X86RegisterInfo.h" 20 #include "X86Subtarget.h" 21 #include "X86TargetMachine.h" 22 #include "llvm/Instructions.h" 23 #include "llvm/Intrinsics.h" 24 #include "llvm/Support/CFG.h" 25 #include "llvm/Type.h" 26 #include "llvm/CodeGen/FunctionLoweringInfo.h" 27 #include "llvm/CodeGen/MachineConstantPool.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineFrameInfo.h" 30 #include "llvm/CodeGen/MachineInstrBuilder.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/Target/TargetMachine.h" 34 #include "llvm/Target/TargetOptions.h" 35 #include "llvm/Support/Debug.h" 36 #include "llvm/Support/ErrorHandling.h" 37 #include "llvm/Support/MathExtras.h" 38 #include "llvm/Support/raw_ostream.h" 39 #include "llvm/ADT/SmallPtrSet.h" 40 #include "llvm/ADT/Statistic.h" 41 using namespace llvm; 42 43 STATISTIC(NumLoadMoved, "Number of loads moved below TokenFactor"); 44 45 //===----------------------------------------------------------------------===// 46 // Pattern Matcher Implementation 47 //===----------------------------------------------------------------------===// 48 49 namespace { 50 /// X86ISelAddressMode - This corresponds to X86AddressMode, but uses 51 /// SDValue's instead of register numbers for the leaves of the matched 52 /// tree. 53 struct X86ISelAddressMode { 54 enum { 55 RegBase, 56 FrameIndexBase 57 } BaseType; 58 59 // This is really a union, discriminated by BaseType! 60 SDValue Base_Reg; 61 int Base_FrameIndex; 62 63 unsigned Scale; 64 SDValue IndexReg; 65 int32_t Disp; 66 SDValue Segment; 67 const GlobalValue *GV; 68 const Constant *CP; 69 const BlockAddress *BlockAddr; 70 const char *ES; 71 int JT; 72 unsigned Align; // CP alignment. 73 unsigned char SymbolFlags; // X86II::MO_* 74 75 X86ISelAddressMode() 76 : BaseType(RegBase), Base_FrameIndex(0), Scale(1), IndexReg(), Disp(0), 77 Segment(), GV(0), CP(0), BlockAddr(0), ES(0), JT(-1), Align(0), 78 SymbolFlags(X86II::MO_NO_FLAG) { 79 } 80 81 bool hasSymbolicDisplacement() const { 82 return GV != 0 || CP != 0 || ES != 0 || JT != -1 || BlockAddr != 0; 83 } 84 85 bool hasBaseOrIndexReg() const { 86 return IndexReg.getNode() != 0 || Base_Reg.getNode() != 0; 87 } 88 89 /// isRIPRelative - Return true if this addressing mode is already RIP 90 /// relative. 91 bool isRIPRelative() const { 92 if (BaseType != RegBase) return false; 93 if (RegisterSDNode *RegNode = 94 dyn_cast_or_null<RegisterSDNode>(Base_Reg.getNode())) 95 return RegNode->getReg() == X86::RIP; 96 return false; 97 } 98 99 void setBaseReg(SDValue Reg) { 100 BaseType = RegBase; 101 Base_Reg = Reg; 102 } 103 104 void dump() { 105 dbgs() << "X86ISelAddressMode " << this << '\n'; 106 dbgs() << "Base_Reg "; 107 if (Base_Reg.getNode() != 0) 108 Base_Reg.getNode()->dump(); 109 else 110 dbgs() << "nul"; 111 dbgs() << " Base.FrameIndex " << Base_FrameIndex << '\n' 112 << " Scale" << Scale << '\n' 113 << "IndexReg "; 114 if (IndexReg.getNode() != 0) 115 IndexReg.getNode()->dump(); 116 else 117 dbgs() << "nul"; 118 dbgs() << " Disp " << Disp << '\n' 119 << "GV "; 120 if (GV) 121 GV->dump(); 122 else 123 dbgs() << "nul"; 124 dbgs() << " CP "; 125 if (CP) 126 CP->dump(); 127 else 128 dbgs() << "nul"; 129 dbgs() << '\n' 130 << "ES "; 131 if (ES) 132 dbgs() << ES; 133 else 134 dbgs() << "nul"; 135 dbgs() << " JT" << JT << " Align" << Align << '\n'; 136 } 137 }; 138 } 139 140 namespace { 141 //===--------------------------------------------------------------------===// 142 /// ISel - X86 specific code to select X86 machine instructions for 143 /// SelectionDAG operations. 144 /// 145 class X86DAGToDAGISel : public SelectionDAGISel { 146 /// X86Lowering - This object fully describes how to lower LLVM code to an 147 /// X86-specific SelectionDAG. 148 const X86TargetLowering &X86Lowering; 149 150 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can 151 /// make the right decision when generating code for different targets. 152 const X86Subtarget *Subtarget; 153 154 /// OptForSize - If true, selector should try to optimize for code size 155 /// instead of performance. 156 bool OptForSize; 157 158 public: 159 explicit X86DAGToDAGISel(X86TargetMachine &tm, CodeGenOpt::Level OptLevel) 160 : SelectionDAGISel(tm, OptLevel), 161 X86Lowering(*tm.getTargetLowering()), 162 Subtarget(&tm.getSubtarget<X86Subtarget>()), 163 OptForSize(false) {} 164 165 virtual const char *getPassName() const { 166 return "X86 DAG->DAG Instruction Selection"; 167 } 168 169 virtual void EmitFunctionEntryCode(); 170 171 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const; 172 173 virtual void PreprocessISelDAG(); 174 175 inline bool immSext8(SDNode *N) const { 176 return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue()); 177 } 178 179 // i64immSExt32 predicate - True if the 64-bit immediate fits in a 32-bit 180 // sign extended field. 181 inline bool i64immSExt32(SDNode *N) const { 182 uint64_t v = cast<ConstantSDNode>(N)->getZExtValue(); 183 return (int64_t)v == (int32_t)v; 184 } 185 186 // Include the pieces autogenerated from the target description. 187 #include "X86GenDAGISel.inc" 188 189 private: 190 SDNode *Select(SDNode *N); 191 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 192 SDNode *SelectAtomicLoadAdd(SDNode *Node, EVT NVT); 193 SDNode *SelectAtomicLoadArith(SDNode *Node, EVT NVT); 194 195 bool FoldOffsetIntoAddress(uint64_t Offset, X86ISelAddressMode &AM); 196 bool MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM); 197 bool MatchWrapper(SDValue N, X86ISelAddressMode &AM); 198 bool MatchAddress(SDValue N, X86ISelAddressMode &AM); 199 bool MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 200 unsigned Depth); 201 bool MatchAddressBase(SDValue N, X86ISelAddressMode &AM); 202 bool SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, 203 SDValue &Scale, SDValue &Index, SDValue &Disp, 204 SDValue &Segment); 205 bool SelectLEAAddr(SDValue N, SDValue &Base, 206 SDValue &Scale, SDValue &Index, SDValue &Disp, 207 SDValue &Segment); 208 bool SelectTLSADDRAddr(SDValue N, SDValue &Base, 209 SDValue &Scale, SDValue &Index, SDValue &Disp, 210 SDValue &Segment); 211 bool SelectScalarSSELoad(SDNode *Root, SDValue N, 212 SDValue &Base, SDValue &Scale, 213 SDValue &Index, SDValue &Disp, 214 SDValue &Segment, 215 SDValue &NodeWithChain); 216 217 bool TryFoldLoad(SDNode *P, SDValue N, 218 SDValue &Base, SDValue &Scale, 219 SDValue &Index, SDValue &Disp, 220 SDValue &Segment); 221 222 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for 223 /// inline asm expressions. 224 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, 225 char ConstraintCode, 226 std::vector<SDValue> &OutOps); 227 228 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI); 229 230 inline void getAddressOperands(X86ISelAddressMode &AM, SDValue &Base, 231 SDValue &Scale, SDValue &Index, 232 SDValue &Disp, SDValue &Segment) { 233 Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ? 234 CurDAG->getTargetFrameIndex(AM.Base_FrameIndex, TLI.getPointerTy()) : 235 AM.Base_Reg; 236 Scale = getI8Imm(AM.Scale); 237 Index = AM.IndexReg; 238 // These are 32-bit even in 64-bit mode since RIP relative offset 239 // is 32-bit. 240 if (AM.GV) 241 Disp = CurDAG->getTargetGlobalAddress(AM.GV, DebugLoc(), 242 MVT::i32, AM.Disp, 243 AM.SymbolFlags); 244 else if (AM.CP) 245 Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, 246 AM.Align, AM.Disp, AM.SymbolFlags); 247 else if (AM.ES) 248 Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags); 249 else if (AM.JT != -1) 250 Disp = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags); 251 else if (AM.BlockAddr) 252 Disp = CurDAG->getBlockAddress(AM.BlockAddr, MVT::i32, 253 true, AM.SymbolFlags); 254 else 255 Disp = CurDAG->getTargetConstant(AM.Disp, MVT::i32); 256 257 if (AM.Segment.getNode()) 258 Segment = AM.Segment; 259 else 260 Segment = CurDAG->getRegister(0, MVT::i32); 261 } 262 263 /// getI8Imm - Return a target constant with the specified value, of type 264 /// i8. 265 inline SDValue getI8Imm(unsigned Imm) { 266 return CurDAG->getTargetConstant(Imm, MVT::i8); 267 } 268 269 /// getI32Imm - Return a target constant with the specified value, of type 270 /// i32. 271 inline SDValue getI32Imm(unsigned Imm) { 272 return CurDAG->getTargetConstant(Imm, MVT::i32); 273 } 274 275 /// getGlobalBaseReg - Return an SDNode that returns the value of 276 /// the global base register. Output instructions required to 277 /// initialize the global base register, if necessary. 278 /// 279 SDNode *getGlobalBaseReg(); 280 281 /// getTargetMachine - Return a reference to the TargetMachine, casted 282 /// to the target-specific type. 283 const X86TargetMachine &getTargetMachine() { 284 return static_cast<const X86TargetMachine &>(TM); 285 } 286 287 /// getInstrInfo - Return a reference to the TargetInstrInfo, casted 288 /// to the target-specific type. 289 const X86InstrInfo *getInstrInfo() { 290 return getTargetMachine().getInstrInfo(); 291 } 292 }; 293 } 294 295 296 bool 297 X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const { 298 if (OptLevel == CodeGenOpt::None) return false; 299 300 if (!N.hasOneUse()) 301 return false; 302 303 if (N.getOpcode() != ISD::LOAD) 304 return true; 305 306 // If N is a load, do additional profitability checks. 307 if (U == Root) { 308 switch (U->getOpcode()) { 309 default: break; 310 case X86ISD::ADD: 311 case X86ISD::SUB: 312 case X86ISD::AND: 313 case X86ISD::XOR: 314 case X86ISD::OR: 315 case ISD::ADD: 316 case ISD::ADDC: 317 case ISD::ADDE: 318 case ISD::AND: 319 case ISD::OR: 320 case ISD::XOR: { 321 SDValue Op1 = U->getOperand(1); 322 323 // If the other operand is a 8-bit immediate we should fold the immediate 324 // instead. This reduces code size. 325 // e.g. 326 // movl 4(%esp), %eax 327 // addl $4, %eax 328 // vs. 329 // movl $4, %eax 330 // addl 4(%esp), %eax 331 // The former is 2 bytes shorter. In case where the increment is 1, then 332 // the saving can be 4 bytes (by using incl %eax). 333 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1)) 334 if (Imm->getAPIntValue().isSignedIntN(8)) 335 return false; 336 337 // If the other operand is a TLS address, we should fold it instead. 338 // This produces 339 // movl %gs:0, %eax 340 // leal i@NTPOFF(%eax), %eax 341 // instead of 342 // movl $i@NTPOFF, %eax 343 // addl %gs:0, %eax 344 // if the block also has an access to a second TLS address this will save 345 // a load. 346 // FIXME: This is probably also true for non TLS addresses. 347 if (Op1.getOpcode() == X86ISD::Wrapper) { 348 SDValue Val = Op1.getOperand(0); 349 if (Val.getOpcode() == ISD::TargetGlobalTLSAddress) 350 return false; 351 } 352 } 353 } 354 } 355 356 return true; 357 } 358 359 /// MoveBelowCallOrigChain - Replace the original chain operand of the call with 360 /// load's chain operand and move load below the call's chain operand. 361 static void MoveBelowOrigChain(SelectionDAG *CurDAG, SDValue Load, 362 SDValue Call, SDValue OrigChain) { 363 SmallVector<SDValue, 8> Ops; 364 SDValue Chain = OrigChain.getOperand(0); 365 if (Chain.getNode() == Load.getNode()) 366 Ops.push_back(Load.getOperand(0)); 367 else { 368 assert(Chain.getOpcode() == ISD::TokenFactor && 369 "Unexpected chain operand"); 370 for (unsigned i = 0, e = Chain.getNumOperands(); i != e; ++i) 371 if (Chain.getOperand(i).getNode() == Load.getNode()) 372 Ops.push_back(Load.getOperand(0)); 373 else 374 Ops.push_back(Chain.getOperand(i)); 375 SDValue NewChain = 376 CurDAG->getNode(ISD::TokenFactor, Load.getDebugLoc(), 377 MVT::Other, &Ops[0], Ops.size()); 378 Ops.clear(); 379 Ops.push_back(NewChain); 380 } 381 for (unsigned i = 1, e = OrigChain.getNumOperands(); i != e; ++i) 382 Ops.push_back(OrigChain.getOperand(i)); 383 CurDAG->UpdateNodeOperands(OrigChain.getNode(), &Ops[0], Ops.size()); 384 CurDAG->UpdateNodeOperands(Load.getNode(), Call.getOperand(0), 385 Load.getOperand(1), Load.getOperand(2)); 386 Ops.clear(); 387 Ops.push_back(SDValue(Load.getNode(), 1)); 388 for (unsigned i = 1, e = Call.getNode()->getNumOperands(); i != e; ++i) 389 Ops.push_back(Call.getOperand(i)); 390 CurDAG->UpdateNodeOperands(Call.getNode(), &Ops[0], Ops.size()); 391 } 392 393 /// isCalleeLoad - Return true if call address is a load and it can be 394 /// moved below CALLSEQ_START and the chains leading up to the call. 395 /// Return the CALLSEQ_START by reference as a second output. 396 /// In the case of a tail call, there isn't a callseq node between the call 397 /// chain and the load. 398 static bool isCalleeLoad(SDValue Callee, SDValue &Chain, bool HasCallSeq) { 399 if (Callee.getNode() == Chain.getNode() || !Callee.hasOneUse()) 400 return false; 401 LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.getNode()); 402 if (!LD || 403 LD->isVolatile() || 404 LD->getAddressingMode() != ISD::UNINDEXED || 405 LD->getExtensionType() != ISD::NON_EXTLOAD) 406 return false; 407 408 // Now let's find the callseq_start. 409 while (HasCallSeq && Chain.getOpcode() != ISD::CALLSEQ_START) { 410 if (!Chain.hasOneUse()) 411 return false; 412 Chain = Chain.getOperand(0); 413 } 414 415 if (!Chain.getNumOperands()) 416 return false; 417 if (Chain.getOperand(0).getNode() == Callee.getNode()) 418 return true; 419 if (Chain.getOperand(0).getOpcode() == ISD::TokenFactor && 420 Callee.getValue(1).isOperandOf(Chain.getOperand(0).getNode()) && 421 Callee.getValue(1).hasOneUse()) 422 return true; 423 return false; 424 } 425 426 void X86DAGToDAGISel::PreprocessISelDAG() { 427 // OptForSize is used in pattern predicates that isel is matching. 428 OptForSize = MF->getFunction()->hasFnAttr(Attribute::OptimizeForSize); 429 430 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(), 431 E = CurDAG->allnodes_end(); I != E; ) { 432 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues. 433 434 if (OptLevel != CodeGenOpt::None && 435 (N->getOpcode() == X86ISD::CALL || 436 N->getOpcode() == X86ISD::TC_RETURN)) { 437 /// Also try moving call address load from outside callseq_start to just 438 /// before the call to allow it to be folded. 439 /// 440 /// [Load chain] 441 /// ^ 442 /// | 443 /// [Load] 444 /// ^ ^ 445 /// | | 446 /// / \-- 447 /// / | 448 ///[CALLSEQ_START] | 449 /// ^ | 450 /// | | 451 /// [LOAD/C2Reg] | 452 /// | | 453 /// \ / 454 /// \ / 455 /// [CALL] 456 bool HasCallSeq = N->getOpcode() == X86ISD::CALL; 457 SDValue Chain = N->getOperand(0); 458 SDValue Load = N->getOperand(1); 459 if (!isCalleeLoad(Load, Chain, HasCallSeq)) 460 continue; 461 MoveBelowOrigChain(CurDAG, Load, SDValue(N, 0), Chain); 462 ++NumLoadMoved; 463 continue; 464 } 465 466 // Lower fpround and fpextend nodes that target the FP stack to be store and 467 // load to the stack. This is a gross hack. We would like to simply mark 468 // these as being illegal, but when we do that, legalize produces these when 469 // it expands calls, then expands these in the same legalize pass. We would 470 // like dag combine to be able to hack on these between the call expansion 471 // and the node legalization. As such this pass basically does "really 472 // late" legalization of these inline with the X86 isel pass. 473 // FIXME: This should only happen when not compiled with -O0. 474 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND) 475 continue; 476 477 EVT SrcVT = N->getOperand(0).getValueType(); 478 EVT DstVT = N->getValueType(0); 479 480 // If any of the sources are vectors, no fp stack involved. 481 if (SrcVT.isVector() || DstVT.isVector()) 482 continue; 483 484 // If the source and destination are SSE registers, then this is a legal 485 // conversion that should not be lowered. 486 bool SrcIsSSE = X86Lowering.isScalarFPTypeInSSEReg(SrcVT); 487 bool DstIsSSE = X86Lowering.isScalarFPTypeInSSEReg(DstVT); 488 if (SrcIsSSE && DstIsSSE) 489 continue; 490 491 if (!SrcIsSSE && !DstIsSSE) { 492 // If this is an FPStack extension, it is a noop. 493 if (N->getOpcode() == ISD::FP_EXTEND) 494 continue; 495 // If this is a value-preserving FPStack truncation, it is a noop. 496 if (N->getConstantOperandVal(1)) 497 continue; 498 } 499 500 // Here we could have an FP stack truncation or an FPStack <-> SSE convert. 501 // FPStack has extload and truncstore. SSE can fold direct loads into other 502 // operations. Based on this, decide what we want to do. 503 EVT MemVT; 504 if (N->getOpcode() == ISD::FP_ROUND) 505 MemVT = DstVT; // FP_ROUND must use DstVT, we can't do a 'trunc load'. 506 else 507 MemVT = SrcIsSSE ? SrcVT : DstVT; 508 509 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT); 510 DebugLoc dl = N->getDebugLoc(); 511 512 // FIXME: optimize the case where the src/dest is a load or store? 513 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(), dl, 514 N->getOperand(0), 515 MemTmp, MachinePointerInfo(), MemVT, 516 false, false, 0); 517 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, dl, DstVT, Store, MemTmp, 518 MachinePointerInfo(), 519 MemVT, false, false, 0); 520 521 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the 522 // extload we created. This will cause general havok on the dag because 523 // anything below the conversion could be folded into other existing nodes. 524 // To avoid invalidating 'I', back it up to the convert node. 525 --I; 526 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result); 527 528 // Now that we did that, the node is dead. Increment the iterator to the 529 // next node to process, then delete N. 530 ++I; 531 CurDAG->DeleteNode(N); 532 } 533 } 534 535 536 /// EmitSpecialCodeForMain - Emit any code that needs to be executed only in 537 /// the main function. 538 void X86DAGToDAGISel::EmitSpecialCodeForMain(MachineBasicBlock *BB, 539 MachineFrameInfo *MFI) { 540 const TargetInstrInfo *TII = TM.getInstrInfo(); 541 if (Subtarget->isTargetCygMing()) { 542 unsigned CallOp = 543 Subtarget->is64Bit() ? X86::WINCALL64pcrel32 : X86::CALLpcrel32; 544 BuildMI(BB, DebugLoc(), 545 TII->get(CallOp)).addExternalSymbol("__main"); 546 } 547 } 548 549 void X86DAGToDAGISel::EmitFunctionEntryCode() { 550 // If this is main, emit special code for main. 551 if (const Function *Fn = MF->getFunction()) 552 if (Fn->hasExternalLinkage() && Fn->getName() == "main") 553 EmitSpecialCodeForMain(MF->begin(), MF->getFrameInfo()); 554 } 555 556 static bool isDispSafeForFrameIndex(int64_t Val) { 557 // On 64-bit platforms, we can run into an issue where a frame index 558 // includes a displacement that, when added to the explicit displacement, 559 // will overflow the displacement field. Assuming that the frame index 560 // displacement fits into a 31-bit integer (which is only slightly more 561 // aggressive than the current fundamental assumption that it fits into 562 // a 32-bit integer), a 31-bit disp should always be safe. 563 return isInt<31>(Val); 564 } 565 566 bool X86DAGToDAGISel::FoldOffsetIntoAddress(uint64_t Offset, 567 X86ISelAddressMode &AM) { 568 int64_t Val = AM.Disp + Offset; 569 CodeModel::Model M = TM.getCodeModel(); 570 if (Subtarget->is64Bit()) { 571 if (!X86::isOffsetSuitableForCodeModel(Val, M, 572 AM.hasSymbolicDisplacement())) 573 return true; 574 // In addition to the checks required for a register base, check that 575 // we do not try to use an unsafe Disp with a frame index. 576 if (AM.BaseType == X86ISelAddressMode::FrameIndexBase && 577 !isDispSafeForFrameIndex(Val)) 578 return true; 579 } 580 AM.Disp = Val; 581 return false; 582 583 } 584 585 bool X86DAGToDAGISel::MatchLoadInAddress(LoadSDNode *N, X86ISelAddressMode &AM){ 586 SDValue Address = N->getOperand(1); 587 588 // load gs:0 -> GS segment register. 589 // load fs:0 -> FS segment register. 590 // 591 // This optimization is valid because the GNU TLS model defines that 592 // gs:0 (or fs:0 on X86-64) contains its own address. 593 // For more information see http://people.redhat.com/drepper/tls.pdf 594 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address)) 595 if (C->getSExtValue() == 0 && AM.Segment.getNode() == 0 && 596 Subtarget->isTargetELF()) 597 switch (N->getPointerInfo().getAddrSpace()) { 598 case 256: 599 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); 600 return false; 601 case 257: 602 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); 603 return false; 604 } 605 606 return true; 607 } 608 609 /// MatchWrapper - Try to match X86ISD::Wrapper and X86ISD::WrapperRIP nodes 610 /// into an addressing mode. These wrap things that will resolve down into a 611 /// symbol reference. If no match is possible, this returns true, otherwise it 612 /// returns false. 613 bool X86DAGToDAGISel::MatchWrapper(SDValue N, X86ISelAddressMode &AM) { 614 // If the addressing mode already has a symbol as the displacement, we can 615 // never match another symbol. 616 if (AM.hasSymbolicDisplacement()) 617 return true; 618 619 SDValue N0 = N.getOperand(0); 620 CodeModel::Model M = TM.getCodeModel(); 621 622 // Handle X86-64 rip-relative addresses. We check this before checking direct 623 // folding because RIP is preferable to non-RIP accesses. 624 if (Subtarget->is64Bit() && 625 // Under X86-64 non-small code model, GV (and friends) are 64-bits, so 626 // they cannot be folded into immediate fields. 627 // FIXME: This can be improved for kernel and other models? 628 (M == CodeModel::Small || M == CodeModel::Kernel) && 629 // Base and index reg must be 0 in order to use %rip as base and lowering 630 // must allow RIP. 631 !AM.hasBaseOrIndexReg() && N.getOpcode() == X86ISD::WrapperRIP) { 632 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 633 X86ISelAddressMode Backup = AM; 634 AM.GV = G->getGlobal(); 635 AM.SymbolFlags = G->getTargetFlags(); 636 if (FoldOffsetIntoAddress(G->getOffset(), AM)) { 637 AM = Backup; 638 return true; 639 } 640 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 641 X86ISelAddressMode Backup = AM; 642 AM.CP = CP->getConstVal(); 643 AM.Align = CP->getAlignment(); 644 AM.SymbolFlags = CP->getTargetFlags(); 645 if (FoldOffsetIntoAddress(CP->getOffset(), AM)) { 646 AM = Backup; 647 return true; 648 } 649 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { 650 AM.ES = S->getSymbol(); 651 AM.SymbolFlags = S->getTargetFlags(); 652 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 653 AM.JT = J->getIndex(); 654 AM.SymbolFlags = J->getTargetFlags(); 655 } else { 656 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); 657 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags(); 658 } 659 660 if (N.getOpcode() == X86ISD::WrapperRIP) 661 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); 662 return false; 663 } 664 665 // Handle the case when globals fit in our immediate field: This is true for 666 // X86-32 always and X86-64 when in -static -mcmodel=small mode. In 64-bit 667 // mode, this results in a non-RIP-relative computation. 668 if (!Subtarget->is64Bit() || 669 ((M == CodeModel::Small || M == CodeModel::Kernel) && 670 TM.getRelocationModel() == Reloc::Static)) { 671 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(N0)) { 672 AM.GV = G->getGlobal(); 673 AM.Disp += G->getOffset(); 674 AM.SymbolFlags = G->getTargetFlags(); 675 } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) { 676 AM.CP = CP->getConstVal(); 677 AM.Align = CP->getAlignment(); 678 AM.Disp += CP->getOffset(); 679 AM.SymbolFlags = CP->getTargetFlags(); 680 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) { 681 AM.ES = S->getSymbol(); 682 AM.SymbolFlags = S->getTargetFlags(); 683 } else if (JumpTableSDNode *J = dyn_cast<JumpTableSDNode>(N0)) { 684 AM.JT = J->getIndex(); 685 AM.SymbolFlags = J->getTargetFlags(); 686 } else { 687 AM.BlockAddr = cast<BlockAddressSDNode>(N0)->getBlockAddress(); 688 AM.SymbolFlags = cast<BlockAddressSDNode>(N0)->getTargetFlags(); 689 } 690 return false; 691 } 692 693 return true; 694 } 695 696 /// MatchAddress - Add the specified node to the specified addressing mode, 697 /// returning true if it cannot be done. This just pattern matches for the 698 /// addressing mode. 699 bool X86DAGToDAGISel::MatchAddress(SDValue N, X86ISelAddressMode &AM) { 700 if (MatchAddressRecursively(N, AM, 0)) 701 return true; 702 703 // Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has 704 // a smaller encoding and avoids a scaled-index. 705 if (AM.Scale == 2 && 706 AM.BaseType == X86ISelAddressMode::RegBase && 707 AM.Base_Reg.getNode() == 0) { 708 AM.Base_Reg = AM.IndexReg; 709 AM.Scale = 1; 710 } 711 712 // Post-processing: Convert foo to foo(%rip), even in non-PIC mode, 713 // because it has a smaller encoding. 714 // TODO: Which other code models can use this? 715 if (TM.getCodeModel() == CodeModel::Small && 716 Subtarget->is64Bit() && 717 AM.Scale == 1 && 718 AM.BaseType == X86ISelAddressMode::RegBase && 719 AM.Base_Reg.getNode() == 0 && 720 AM.IndexReg.getNode() == 0 && 721 AM.SymbolFlags == X86II::MO_NO_FLAG && 722 AM.hasSymbolicDisplacement()) 723 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64); 724 725 return false; 726 } 727 728 bool X86DAGToDAGISel::MatchAddressRecursively(SDValue N, X86ISelAddressMode &AM, 729 unsigned Depth) { 730 DebugLoc dl = N.getDebugLoc(); 731 DEBUG({ 732 dbgs() << "MatchAddress: "; 733 AM.dump(); 734 }); 735 // Limit recursion. 736 if (Depth > 5) 737 return MatchAddressBase(N, AM); 738 739 // If this is already a %rip relative address, we can only merge immediates 740 // into it. Instead of handling this in every case, we handle it here. 741 // RIP relative addressing: %rip + 32-bit displacement! 742 if (AM.isRIPRelative()) { 743 // FIXME: JumpTable and ExternalSymbol address currently don't like 744 // displacements. It isn't very important, but this should be fixed for 745 // consistency. 746 if (!AM.ES && AM.JT != -1) return true; 747 748 if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N)) 749 if (!FoldOffsetIntoAddress(Cst->getSExtValue(), AM)) 750 return false; 751 return true; 752 } 753 754 switch (N.getOpcode()) { 755 default: break; 756 case ISD::Constant: { 757 uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue(); 758 if (!FoldOffsetIntoAddress(Val, AM)) 759 return false; 760 break; 761 } 762 763 case X86ISD::Wrapper: 764 case X86ISD::WrapperRIP: 765 if (!MatchWrapper(N, AM)) 766 return false; 767 break; 768 769 case ISD::LOAD: 770 if (!MatchLoadInAddress(cast<LoadSDNode>(N), AM)) 771 return false; 772 break; 773 774 case ISD::FrameIndex: 775 if (AM.BaseType == X86ISelAddressMode::RegBase && 776 AM.Base_Reg.getNode() == 0 && 777 (!Subtarget->is64Bit() || isDispSafeForFrameIndex(AM.Disp))) { 778 AM.BaseType = X86ISelAddressMode::FrameIndexBase; 779 AM.Base_FrameIndex = cast<FrameIndexSDNode>(N)->getIndex(); 780 return false; 781 } 782 break; 783 784 case ISD::SHL: 785 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) 786 break; 787 788 if (ConstantSDNode 789 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) { 790 unsigned Val = CN->getZExtValue(); 791 // Note that we handle x<<1 as (,x,2) rather than (x,x) here so 792 // that the base operand remains free for further matching. If 793 // the base doesn't end up getting used, a post-processing step 794 // in MatchAddress turns (,x,2) into (x,x), which is cheaper. 795 if (Val == 1 || Val == 2 || Val == 3) { 796 AM.Scale = 1 << Val; 797 SDValue ShVal = N.getNode()->getOperand(0); 798 799 // Okay, we know that we have a scale by now. However, if the scaled 800 // value is an add of something and a constant, we can fold the 801 // constant into the disp field here. 802 if (CurDAG->isBaseWithConstantOffset(ShVal)) { 803 AM.IndexReg = ShVal.getNode()->getOperand(0); 804 ConstantSDNode *AddVal = 805 cast<ConstantSDNode>(ShVal.getNode()->getOperand(1)); 806 uint64_t Disp = AddVal->getSExtValue() << Val; 807 if (!FoldOffsetIntoAddress(Disp, AM)) 808 return false; 809 } 810 811 AM.IndexReg = ShVal; 812 return false; 813 } 814 break; 815 } 816 817 case ISD::SMUL_LOHI: 818 case ISD::UMUL_LOHI: 819 // A mul_lohi where we need the low part can be folded as a plain multiply. 820 if (N.getResNo() != 0) break; 821 // FALL THROUGH 822 case ISD::MUL: 823 case X86ISD::MUL_IMM: 824 // X*[3,5,9] -> X+X*[2,4,8] 825 if (AM.BaseType == X86ISelAddressMode::RegBase && 826 AM.Base_Reg.getNode() == 0 && 827 AM.IndexReg.getNode() == 0) { 828 if (ConstantSDNode 829 *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) 830 if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 || 831 CN->getZExtValue() == 9) { 832 AM.Scale = unsigned(CN->getZExtValue())-1; 833 834 SDValue MulVal = N.getNode()->getOperand(0); 835 SDValue Reg; 836 837 // Okay, we know that we have a scale by now. However, if the scaled 838 // value is an add of something and a constant, we can fold the 839 // constant into the disp field here. 840 if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() && 841 isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) { 842 Reg = MulVal.getNode()->getOperand(0); 843 ConstantSDNode *AddVal = 844 cast<ConstantSDNode>(MulVal.getNode()->getOperand(1)); 845 uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue(); 846 if (FoldOffsetIntoAddress(Disp, AM)) 847 Reg = N.getNode()->getOperand(0); 848 } else { 849 Reg = N.getNode()->getOperand(0); 850 } 851 852 AM.IndexReg = AM.Base_Reg = Reg; 853 return false; 854 } 855 } 856 break; 857 858 case ISD::SUB: { 859 // Given A-B, if A can be completely folded into the address and 860 // the index field with the index field unused, use -B as the index. 861 // This is a win if a has multiple parts that can be folded into 862 // the address. Also, this saves a mov if the base register has 863 // other uses, since it avoids a two-address sub instruction, however 864 // it costs an additional mov if the index register has other uses. 865 866 // Add an artificial use to this node so that we can keep track of 867 // it if it gets CSE'd with a different node. 868 HandleSDNode Handle(N); 869 870 // Test if the LHS of the sub can be folded. 871 X86ISelAddressMode Backup = AM; 872 if (MatchAddressRecursively(N.getNode()->getOperand(0), AM, Depth+1)) { 873 AM = Backup; 874 break; 875 } 876 // Test if the index field is free for use. 877 if (AM.IndexReg.getNode() || AM.isRIPRelative()) { 878 AM = Backup; 879 break; 880 } 881 882 int Cost = 0; 883 SDValue RHS = Handle.getValue().getNode()->getOperand(1); 884 // If the RHS involves a register with multiple uses, this 885 // transformation incurs an extra mov, due to the neg instruction 886 // clobbering its operand. 887 if (!RHS.getNode()->hasOneUse() || 888 RHS.getNode()->getOpcode() == ISD::CopyFromReg || 889 RHS.getNode()->getOpcode() == ISD::TRUNCATE || 890 RHS.getNode()->getOpcode() == ISD::ANY_EXTEND || 891 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND && 892 RHS.getNode()->getOperand(0).getValueType() == MVT::i32)) 893 ++Cost; 894 // If the base is a register with multiple uses, this 895 // transformation may save a mov. 896 if ((AM.BaseType == X86ISelAddressMode::RegBase && 897 AM.Base_Reg.getNode() && 898 !AM.Base_Reg.getNode()->hasOneUse()) || 899 AM.BaseType == X86ISelAddressMode::FrameIndexBase) 900 --Cost; 901 // If the folded LHS was interesting, this transformation saves 902 // address arithmetic. 903 if ((AM.hasSymbolicDisplacement() && !Backup.hasSymbolicDisplacement()) + 904 ((AM.Disp != 0) && (Backup.Disp == 0)) + 905 (AM.Segment.getNode() && !Backup.Segment.getNode()) >= 2) 906 --Cost; 907 // If it doesn't look like it may be an overall win, don't do it. 908 if (Cost >= 0) { 909 AM = Backup; 910 break; 911 } 912 913 // Ok, the transformation is legal and appears profitable. Go for it. 914 SDValue Zero = CurDAG->getConstant(0, N.getValueType()); 915 SDValue Neg = CurDAG->getNode(ISD::SUB, dl, N.getValueType(), Zero, RHS); 916 AM.IndexReg = Neg; 917 AM.Scale = 1; 918 919 // Insert the new nodes into the topological ordering. 920 if (Zero.getNode()->getNodeId() == -1 || 921 Zero.getNode()->getNodeId() > N.getNode()->getNodeId()) { 922 CurDAG->RepositionNode(N.getNode(), Zero.getNode()); 923 Zero.getNode()->setNodeId(N.getNode()->getNodeId()); 924 } 925 if (Neg.getNode()->getNodeId() == -1 || 926 Neg.getNode()->getNodeId() > N.getNode()->getNodeId()) { 927 CurDAG->RepositionNode(N.getNode(), Neg.getNode()); 928 Neg.getNode()->setNodeId(N.getNode()->getNodeId()); 929 } 930 return false; 931 } 932 933 case ISD::ADD: { 934 // Add an artificial use to this node so that we can keep track of 935 // it if it gets CSE'd with a different node. 936 HandleSDNode Handle(N); 937 938 X86ISelAddressMode Backup = AM; 939 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) && 940 !MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)) 941 return false; 942 AM = Backup; 943 944 // Try again after commuting the operands. 945 if (!MatchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth+1)&& 946 !MatchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth+1)) 947 return false; 948 AM = Backup; 949 950 // If we couldn't fold both operands into the address at the same time, 951 // see if we can just put each operand into a register and fold at least 952 // the add. 953 if (AM.BaseType == X86ISelAddressMode::RegBase && 954 !AM.Base_Reg.getNode() && 955 !AM.IndexReg.getNode()) { 956 N = Handle.getValue(); 957 AM.Base_Reg = N.getOperand(0); 958 AM.IndexReg = N.getOperand(1); 959 AM.Scale = 1; 960 return false; 961 } 962 N = Handle.getValue(); 963 break; 964 } 965 966 case ISD::OR: 967 // Handle "X | C" as "X + C" iff X is known to have C bits clear. 968 if (CurDAG->isBaseWithConstantOffset(N)) { 969 X86ISelAddressMode Backup = AM; 970 ConstantSDNode *CN = cast<ConstantSDNode>(N.getOperand(1)); 971 972 // Start with the LHS as an addr mode. 973 if (!MatchAddressRecursively(N.getOperand(0), AM, Depth+1) && 974 !FoldOffsetIntoAddress(CN->getSExtValue(), AM)) 975 return false; 976 AM = Backup; 977 } 978 break; 979 980 case ISD::AND: { 981 // Perform some heroic transforms on an and of a constant-count shift 982 // with a constant to enable use of the scaled offset field. 983 984 SDValue Shift = N.getOperand(0); 985 if (Shift.getNumOperands() != 2) break; 986 987 // Scale must not be used already. 988 if (AM.IndexReg.getNode() != 0 || AM.Scale != 1) break; 989 990 SDValue X = Shift.getOperand(0); 991 ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N.getOperand(1)); 992 ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Shift.getOperand(1)); 993 if (!C1 || !C2) break; 994 995 // Handle "(X >> (8-C1)) & C2" as "(X >> 8) & 0xff)" if safe. This 996 // allows us to convert the shift and and into an h-register extract and 997 // a scaled index. 998 if (Shift.getOpcode() == ISD::SRL && Shift.hasOneUse()) { 999 unsigned ScaleLog = 8 - C1->getZExtValue(); 1000 if (ScaleLog > 0 && ScaleLog < 4 && 1001 C2->getZExtValue() == (UINT64_C(0xff) << ScaleLog)) { 1002 SDValue Eight = CurDAG->getConstant(8, MVT::i8); 1003 SDValue Mask = CurDAG->getConstant(0xff, N.getValueType()); 1004 SDValue Srl = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), 1005 X, Eight); 1006 SDValue And = CurDAG->getNode(ISD::AND, dl, N.getValueType(), 1007 Srl, Mask); 1008 SDValue ShlCount = CurDAG->getConstant(ScaleLog, MVT::i8); 1009 SDValue Shl = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), 1010 And, ShlCount); 1011 1012 // Insert the new nodes into the topological ordering. 1013 if (Eight.getNode()->getNodeId() == -1 || 1014 Eight.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1015 CurDAG->RepositionNode(X.getNode(), Eight.getNode()); 1016 Eight.getNode()->setNodeId(X.getNode()->getNodeId()); 1017 } 1018 if (Mask.getNode()->getNodeId() == -1 || 1019 Mask.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1020 CurDAG->RepositionNode(X.getNode(), Mask.getNode()); 1021 Mask.getNode()->setNodeId(X.getNode()->getNodeId()); 1022 } 1023 if (Srl.getNode()->getNodeId() == -1 || 1024 Srl.getNode()->getNodeId() > Shift.getNode()->getNodeId()) { 1025 CurDAG->RepositionNode(Shift.getNode(), Srl.getNode()); 1026 Srl.getNode()->setNodeId(Shift.getNode()->getNodeId()); 1027 } 1028 if (And.getNode()->getNodeId() == -1 || 1029 And.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1030 CurDAG->RepositionNode(N.getNode(), And.getNode()); 1031 And.getNode()->setNodeId(N.getNode()->getNodeId()); 1032 } 1033 if (ShlCount.getNode()->getNodeId() == -1 || 1034 ShlCount.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1035 CurDAG->RepositionNode(X.getNode(), ShlCount.getNode()); 1036 ShlCount.getNode()->setNodeId(N.getNode()->getNodeId()); 1037 } 1038 if (Shl.getNode()->getNodeId() == -1 || 1039 Shl.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1040 CurDAG->RepositionNode(N.getNode(), Shl.getNode()); 1041 Shl.getNode()->setNodeId(N.getNode()->getNodeId()); 1042 } 1043 CurDAG->ReplaceAllUsesWith(N, Shl); 1044 AM.IndexReg = And; 1045 AM.Scale = (1 << ScaleLog); 1046 return false; 1047 } 1048 } 1049 1050 // Handle "(X << C1) & C2" as "(X & (C2>>C1)) << C1" if safe and if this 1051 // allows us to fold the shift into this addressing mode. 1052 if (Shift.getOpcode() != ISD::SHL) break; 1053 1054 // Not likely to be profitable if either the AND or SHIFT node has more 1055 // than one use (unless all uses are for address computation). Besides, 1056 // isel mechanism requires their node ids to be reused. 1057 if (!N.hasOneUse() || !Shift.hasOneUse()) 1058 break; 1059 1060 // Verify that the shift amount is something we can fold. 1061 unsigned ShiftCst = C1->getZExtValue(); 1062 if (ShiftCst != 1 && ShiftCst != 2 && ShiftCst != 3) 1063 break; 1064 1065 // Get the new AND mask, this folds to a constant. 1066 SDValue NewANDMask = CurDAG->getNode(ISD::SRL, dl, N.getValueType(), 1067 SDValue(C2, 0), SDValue(C1, 0)); 1068 SDValue NewAND = CurDAG->getNode(ISD::AND, dl, N.getValueType(), X, 1069 NewANDMask); 1070 SDValue NewSHIFT = CurDAG->getNode(ISD::SHL, dl, N.getValueType(), 1071 NewAND, SDValue(C1, 0)); 1072 1073 // Insert the new nodes into the topological ordering. 1074 if (C1->getNodeId() > X.getNode()->getNodeId()) { 1075 CurDAG->RepositionNode(X.getNode(), C1); 1076 C1->setNodeId(X.getNode()->getNodeId()); 1077 } 1078 if (NewANDMask.getNode()->getNodeId() == -1 || 1079 NewANDMask.getNode()->getNodeId() > X.getNode()->getNodeId()) { 1080 CurDAG->RepositionNode(X.getNode(), NewANDMask.getNode()); 1081 NewANDMask.getNode()->setNodeId(X.getNode()->getNodeId()); 1082 } 1083 if (NewAND.getNode()->getNodeId() == -1 || 1084 NewAND.getNode()->getNodeId() > Shift.getNode()->getNodeId()) { 1085 CurDAG->RepositionNode(Shift.getNode(), NewAND.getNode()); 1086 NewAND.getNode()->setNodeId(Shift.getNode()->getNodeId()); 1087 } 1088 if (NewSHIFT.getNode()->getNodeId() == -1 || 1089 NewSHIFT.getNode()->getNodeId() > N.getNode()->getNodeId()) { 1090 CurDAG->RepositionNode(N.getNode(), NewSHIFT.getNode()); 1091 NewSHIFT.getNode()->setNodeId(N.getNode()->getNodeId()); 1092 } 1093 1094 CurDAG->ReplaceAllUsesWith(N, NewSHIFT); 1095 1096 AM.Scale = 1 << ShiftCst; 1097 AM.IndexReg = NewAND; 1098 return false; 1099 } 1100 } 1101 1102 return MatchAddressBase(N, AM); 1103 } 1104 1105 /// MatchAddressBase - Helper for MatchAddress. Add the specified node to the 1106 /// specified addressing mode without any further recursion. 1107 bool X86DAGToDAGISel::MatchAddressBase(SDValue N, X86ISelAddressMode &AM) { 1108 // Is the base register already occupied? 1109 if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base_Reg.getNode()) { 1110 // If so, check to see if the scale index register is set. 1111 if (AM.IndexReg.getNode() == 0) { 1112 AM.IndexReg = N; 1113 AM.Scale = 1; 1114 return false; 1115 } 1116 1117 // Otherwise, we cannot select it. 1118 return true; 1119 } 1120 1121 // Default, generate it as a register. 1122 AM.BaseType = X86ISelAddressMode::RegBase; 1123 AM.Base_Reg = N; 1124 return false; 1125 } 1126 1127 /// SelectAddr - returns true if it is able pattern match an addressing mode. 1128 /// It returns the operands which make up the maximal addressing mode it can 1129 /// match by reference. 1130 /// 1131 /// Parent is the parent node of the addr operand that is being matched. It 1132 /// is always a load, store, atomic node, or null. It is only null when 1133 /// checking memory operands for inline asm nodes. 1134 bool X86DAGToDAGISel::SelectAddr(SDNode *Parent, SDValue N, SDValue &Base, 1135 SDValue &Scale, SDValue &Index, 1136 SDValue &Disp, SDValue &Segment) { 1137 X86ISelAddressMode AM; 1138 1139 if (Parent && 1140 // This list of opcodes are all the nodes that have an "addr:$ptr" operand 1141 // that are not a MemSDNode, and thus don't have proper addrspace info. 1142 Parent->getOpcode() != ISD::INTRINSIC_W_CHAIN && // unaligned loads, fixme 1143 Parent->getOpcode() != ISD::INTRINSIC_VOID && // nontemporal stores 1144 Parent->getOpcode() != X86ISD::TLSCALL) { // Fixme 1145 unsigned AddrSpace = 1146 cast<MemSDNode>(Parent)->getPointerInfo().getAddrSpace(); 1147 // AddrSpace 256 -> GS, 257 -> FS. 1148 if (AddrSpace == 256) 1149 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); 1150 if (AddrSpace == 257) 1151 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); 1152 } 1153 1154 if (MatchAddress(N, AM)) 1155 return false; 1156 1157 EVT VT = N.getValueType(); 1158 if (AM.BaseType == X86ISelAddressMode::RegBase) { 1159 if (!AM.Base_Reg.getNode()) 1160 AM.Base_Reg = CurDAG->getRegister(0, VT); 1161 } 1162 1163 if (!AM.IndexReg.getNode()) 1164 AM.IndexReg = CurDAG->getRegister(0, VT); 1165 1166 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1167 return true; 1168 } 1169 1170 /// SelectScalarSSELoad - Match a scalar SSE load. In particular, we want to 1171 /// match a load whose top elements are either undef or zeros. The load flavor 1172 /// is derived from the type of N, which is either v4f32 or v2f64. 1173 /// 1174 /// We also return: 1175 /// PatternChainNode: this is the matched node that has a chain input and 1176 /// output. 1177 bool X86DAGToDAGISel::SelectScalarSSELoad(SDNode *Root, 1178 SDValue N, SDValue &Base, 1179 SDValue &Scale, SDValue &Index, 1180 SDValue &Disp, SDValue &Segment, 1181 SDValue &PatternNodeWithChain) { 1182 if (N.getOpcode() == ISD::SCALAR_TO_VECTOR) { 1183 PatternNodeWithChain = N.getOperand(0); 1184 if (ISD::isNON_EXTLoad(PatternNodeWithChain.getNode()) && 1185 PatternNodeWithChain.hasOneUse() && 1186 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) && 1187 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) { 1188 LoadSDNode *LD = cast<LoadSDNode>(PatternNodeWithChain); 1189 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1190 return false; 1191 return true; 1192 } 1193 } 1194 1195 // Also handle the case where we explicitly require zeros in the top 1196 // elements. This is a vector shuffle from the zero vector. 1197 if (N.getOpcode() == X86ISD::VZEXT_MOVL && N.getNode()->hasOneUse() && 1198 // Check to see if the top elements are all zeros (or bitcast of zeros). 1199 N.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR && 1200 N.getOperand(0).getNode()->hasOneUse() && 1201 ISD::isNON_EXTLoad(N.getOperand(0).getOperand(0).getNode()) && 1202 N.getOperand(0).getOperand(0).hasOneUse() && 1203 IsProfitableToFold(N.getOperand(0), N.getNode(), Root) && 1204 IsLegalToFold(N.getOperand(0), N.getNode(), Root, OptLevel)) { 1205 // Okay, this is a zero extending load. Fold it. 1206 LoadSDNode *LD = cast<LoadSDNode>(N.getOperand(0).getOperand(0)); 1207 if (!SelectAddr(LD, LD->getBasePtr(), Base, Scale, Index, Disp, Segment)) 1208 return false; 1209 PatternNodeWithChain = SDValue(LD, 0); 1210 return true; 1211 } 1212 return false; 1213 } 1214 1215 1216 /// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing 1217 /// mode it matches can be cost effectively emitted as an LEA instruction. 1218 bool X86DAGToDAGISel::SelectLEAAddr(SDValue N, 1219 SDValue &Base, SDValue &Scale, 1220 SDValue &Index, SDValue &Disp, 1221 SDValue &Segment) { 1222 X86ISelAddressMode AM; 1223 1224 // Set AM.Segment to prevent MatchAddress from using one. LEA doesn't support 1225 // segments. 1226 SDValue Copy = AM.Segment; 1227 SDValue T = CurDAG->getRegister(0, MVT::i32); 1228 AM.Segment = T; 1229 if (MatchAddress(N, AM)) 1230 return false; 1231 assert (T == AM.Segment); 1232 AM.Segment = Copy; 1233 1234 EVT VT = N.getValueType(); 1235 unsigned Complexity = 0; 1236 if (AM.BaseType == X86ISelAddressMode::RegBase) 1237 if (AM.Base_Reg.getNode()) 1238 Complexity = 1; 1239 else 1240 AM.Base_Reg = CurDAG->getRegister(0, VT); 1241 else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase) 1242 Complexity = 4; 1243 1244 if (AM.IndexReg.getNode()) 1245 Complexity++; 1246 else 1247 AM.IndexReg = CurDAG->getRegister(0, VT); 1248 1249 // Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg, or with 1250 // a simple shift. 1251 if (AM.Scale > 1) 1252 Complexity++; 1253 1254 // FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA 1255 // to a LEA. This is determined with some expermentation but is by no means 1256 // optimal (especially for code size consideration). LEA is nice because of 1257 // its three-address nature. Tweak the cost function again when we can run 1258 // convertToThreeAddress() at register allocation time. 1259 if (AM.hasSymbolicDisplacement()) { 1260 // For X86-64, we should always use lea to materialize RIP relative 1261 // addresses. 1262 if (Subtarget->is64Bit()) 1263 Complexity = 4; 1264 else 1265 Complexity += 2; 1266 } 1267 1268 if (AM.Disp && (AM.Base_Reg.getNode() || AM.IndexReg.getNode())) 1269 Complexity++; 1270 1271 // If it isn't worth using an LEA, reject it. 1272 if (Complexity <= 2) 1273 return false; 1274 1275 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1276 return true; 1277 } 1278 1279 /// SelectTLSADDRAddr - This is only run on TargetGlobalTLSAddress nodes. 1280 bool X86DAGToDAGISel::SelectTLSADDRAddr(SDValue N, SDValue &Base, 1281 SDValue &Scale, SDValue &Index, 1282 SDValue &Disp, SDValue &Segment) { 1283 assert(N.getOpcode() == ISD::TargetGlobalTLSAddress); 1284 const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N); 1285 1286 X86ISelAddressMode AM; 1287 AM.GV = GA->getGlobal(); 1288 AM.Disp += GA->getOffset(); 1289 AM.Base_Reg = CurDAG->getRegister(0, N.getValueType()); 1290 AM.SymbolFlags = GA->getTargetFlags(); 1291 1292 if (N.getValueType() == MVT::i32) { 1293 AM.Scale = 1; 1294 AM.IndexReg = CurDAG->getRegister(X86::EBX, MVT::i32); 1295 } else { 1296 AM.IndexReg = CurDAG->getRegister(0, MVT::i64); 1297 } 1298 1299 getAddressOperands(AM, Base, Scale, Index, Disp, Segment); 1300 return true; 1301 } 1302 1303 1304 bool X86DAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N, 1305 SDValue &Base, SDValue &Scale, 1306 SDValue &Index, SDValue &Disp, 1307 SDValue &Segment) { 1308 if (!ISD::isNON_EXTLoad(N.getNode()) || 1309 !IsProfitableToFold(N, P, P) || 1310 !IsLegalToFold(N, P, P, OptLevel)) 1311 return false; 1312 1313 return SelectAddr(N.getNode(), 1314 N.getOperand(1), Base, Scale, Index, Disp, Segment); 1315 } 1316 1317 /// getGlobalBaseReg - Return an SDNode that returns the value of 1318 /// the global base register. Output instructions required to 1319 /// initialize the global base register, if necessary. 1320 /// 1321 SDNode *X86DAGToDAGISel::getGlobalBaseReg() { 1322 unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF); 1323 return CurDAG->getRegister(GlobalBaseReg, TLI.getPointerTy()).getNode(); 1324 } 1325 1326 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { 1327 SDValue Chain = Node->getOperand(0); 1328 SDValue In1 = Node->getOperand(1); 1329 SDValue In2L = Node->getOperand(2); 1330 SDValue In2H = Node->getOperand(3); 1331 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1332 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1333 return NULL; 1334 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1335 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1336 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain}; 1337 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), 1338 MVT::i32, MVT::i32, MVT::Other, Ops, 1339 array_lengthof(Ops)); 1340 cast<MachineSDNode>(ResNode)->setMemRefs(MemOp, MemOp + 1); 1341 return ResNode; 1342 } 1343 1344 // FIXME: Figure out some way to unify this with the 'or' and other code 1345 // below. 1346 SDNode *X86DAGToDAGISel::SelectAtomicLoadAdd(SDNode *Node, EVT NVT) { 1347 if (Node->hasAnyUseOfValue(0)) 1348 return 0; 1349 1350 // Optimize common patterns for __sync_add_and_fetch and 1351 // __sync_sub_and_fetch where the result is not used. This allows us 1352 // to use "lock" version of add, sub, inc, dec instructions. 1353 // FIXME: Do not use special instructions but instead add the "lock" 1354 // prefix to the target node somehow. The extra information will then be 1355 // transferred to machine instruction and it denotes the prefix. 1356 SDValue Chain = Node->getOperand(0); 1357 SDValue Ptr = Node->getOperand(1); 1358 SDValue Val = Node->getOperand(2); 1359 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1360 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1361 return 0; 1362 1363 bool isInc = false, isDec = false, isSub = false, isCN = false; 1364 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val); 1365 if (CN && CN->getSExtValue() == (int32_t)CN->getSExtValue()) { 1366 isCN = true; 1367 int64_t CNVal = CN->getSExtValue(); 1368 if (CNVal == 1) 1369 isInc = true; 1370 else if (CNVal == -1) 1371 isDec = true; 1372 else if (CNVal >= 0) 1373 Val = CurDAG->getTargetConstant(CNVal, NVT); 1374 else { 1375 isSub = true; 1376 Val = CurDAG->getTargetConstant(-CNVal, NVT); 1377 } 1378 } else if (Val.hasOneUse() && 1379 Val.getOpcode() == ISD::SUB && 1380 X86::isZeroNode(Val.getOperand(0))) { 1381 isSub = true; 1382 Val = Val.getOperand(1); 1383 } 1384 1385 DebugLoc dl = Node->getDebugLoc(); 1386 unsigned Opc = 0; 1387 switch (NVT.getSimpleVT().SimpleTy) { 1388 default: return 0; 1389 case MVT::i8: 1390 if (isInc) 1391 Opc = X86::LOCK_INC8m; 1392 else if (isDec) 1393 Opc = X86::LOCK_DEC8m; 1394 else if (isSub) { 1395 if (isCN) 1396 Opc = X86::LOCK_SUB8mi; 1397 else 1398 Opc = X86::LOCK_SUB8mr; 1399 } else { 1400 if (isCN) 1401 Opc = X86::LOCK_ADD8mi; 1402 else 1403 Opc = X86::LOCK_ADD8mr; 1404 } 1405 break; 1406 case MVT::i16: 1407 if (isInc) 1408 Opc = X86::LOCK_INC16m; 1409 else if (isDec) 1410 Opc = X86::LOCK_DEC16m; 1411 else if (isSub) { 1412 if (isCN) { 1413 if (immSext8(Val.getNode())) 1414 Opc = X86::LOCK_SUB16mi8; 1415 else 1416 Opc = X86::LOCK_SUB16mi; 1417 } else 1418 Opc = X86::LOCK_SUB16mr; 1419 } else { 1420 if (isCN) { 1421 if (immSext8(Val.getNode())) 1422 Opc = X86::LOCK_ADD16mi8; 1423 else 1424 Opc = X86::LOCK_ADD16mi; 1425 } else 1426 Opc = X86::LOCK_ADD16mr; 1427 } 1428 break; 1429 case MVT::i32: 1430 if (isInc) 1431 Opc = X86::LOCK_INC32m; 1432 else if (isDec) 1433 Opc = X86::LOCK_DEC32m; 1434 else if (isSub) { 1435 if (isCN) { 1436 if (immSext8(Val.getNode())) 1437 Opc = X86::LOCK_SUB32mi8; 1438 else 1439 Opc = X86::LOCK_SUB32mi; 1440 } else 1441 Opc = X86::LOCK_SUB32mr; 1442 } else { 1443 if (isCN) { 1444 if (immSext8(Val.getNode())) 1445 Opc = X86::LOCK_ADD32mi8; 1446 else 1447 Opc = X86::LOCK_ADD32mi; 1448 } else 1449 Opc = X86::LOCK_ADD32mr; 1450 } 1451 break; 1452 case MVT::i64: 1453 if (isInc) 1454 Opc = X86::LOCK_INC64m; 1455 else if (isDec) 1456 Opc = X86::LOCK_DEC64m; 1457 else if (isSub) { 1458 Opc = X86::LOCK_SUB64mr; 1459 if (isCN) { 1460 if (immSext8(Val.getNode())) 1461 Opc = X86::LOCK_SUB64mi8; 1462 else if (i64immSExt32(Val.getNode())) 1463 Opc = X86::LOCK_SUB64mi32; 1464 } 1465 } else { 1466 Opc = X86::LOCK_ADD64mr; 1467 if (isCN) { 1468 if (immSext8(Val.getNode())) 1469 Opc = X86::LOCK_ADD64mi8; 1470 else if (i64immSExt32(Val.getNode())) 1471 Opc = X86::LOCK_ADD64mi32; 1472 } 1473 } 1474 break; 1475 } 1476 1477 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1478 dl, NVT), 0); 1479 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1480 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1481 if (isInc || isDec) { 1482 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain }; 1483 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 6), 0); 1484 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1485 SDValue RetVals[] = { Undef, Ret }; 1486 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1487 } else { 1488 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; 1489 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0); 1490 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1491 SDValue RetVals[] = { Undef, Ret }; 1492 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1493 } 1494 } 1495 1496 enum AtomicOpc { 1497 OR, 1498 AND, 1499 XOR, 1500 AtomicOpcEnd 1501 }; 1502 1503 enum AtomicSz { 1504 ConstantI8, 1505 I8, 1506 SextConstantI16, 1507 ConstantI16, 1508 I16, 1509 SextConstantI32, 1510 ConstantI32, 1511 I32, 1512 SextConstantI64, 1513 ConstantI64, 1514 I64, 1515 AtomicSzEnd 1516 }; 1517 1518 static const unsigned int AtomicOpcTbl[AtomicOpcEnd][AtomicSzEnd] = { 1519 { 1520 X86::LOCK_OR8mi, 1521 X86::LOCK_OR8mr, 1522 X86::LOCK_OR16mi8, 1523 X86::LOCK_OR16mi, 1524 X86::LOCK_OR16mr, 1525 X86::LOCK_OR32mi8, 1526 X86::LOCK_OR32mi, 1527 X86::LOCK_OR32mr, 1528 X86::LOCK_OR64mi8, 1529 X86::LOCK_OR64mi32, 1530 X86::LOCK_OR64mr 1531 }, 1532 { 1533 X86::LOCK_AND8mi, 1534 X86::LOCK_AND8mr, 1535 X86::LOCK_AND16mi8, 1536 X86::LOCK_AND16mi, 1537 X86::LOCK_AND16mr, 1538 X86::LOCK_AND32mi8, 1539 X86::LOCK_AND32mi, 1540 X86::LOCK_AND32mr, 1541 X86::LOCK_AND64mi8, 1542 X86::LOCK_AND64mi32, 1543 X86::LOCK_AND64mr 1544 }, 1545 { 1546 X86::LOCK_XOR8mi, 1547 X86::LOCK_XOR8mr, 1548 X86::LOCK_XOR16mi8, 1549 X86::LOCK_XOR16mi, 1550 X86::LOCK_XOR16mr, 1551 X86::LOCK_XOR32mi8, 1552 X86::LOCK_XOR32mi, 1553 X86::LOCK_XOR32mr, 1554 X86::LOCK_XOR64mi8, 1555 X86::LOCK_XOR64mi32, 1556 X86::LOCK_XOR64mr 1557 } 1558 }; 1559 1560 SDNode *X86DAGToDAGISel::SelectAtomicLoadArith(SDNode *Node, EVT NVT) { 1561 if (Node->hasAnyUseOfValue(0)) 1562 return 0; 1563 1564 // Optimize common patterns for __sync_or_and_fetch and similar arith 1565 // operations where the result is not used. This allows us to use the "lock" 1566 // version of the arithmetic instruction. 1567 // FIXME: Same as for 'add' and 'sub', try to merge those down here. 1568 SDValue Chain = Node->getOperand(0); 1569 SDValue Ptr = Node->getOperand(1); 1570 SDValue Val = Node->getOperand(2); 1571 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1572 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) 1573 return 0; 1574 1575 // Which index into the table. 1576 enum AtomicOpc Op; 1577 switch (Node->getOpcode()) { 1578 case ISD::ATOMIC_LOAD_OR: 1579 Op = OR; 1580 break; 1581 case ISD::ATOMIC_LOAD_AND: 1582 Op = AND; 1583 break; 1584 case ISD::ATOMIC_LOAD_XOR: 1585 Op = XOR; 1586 break; 1587 default: 1588 return 0; 1589 } 1590 1591 bool isCN = false; 1592 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Val); 1593 if (CN && (int32_t)CN->getSExtValue() == CN->getSExtValue()) { 1594 isCN = true; 1595 Val = CurDAG->getTargetConstant(CN->getSExtValue(), NVT); 1596 } 1597 1598 unsigned Opc = 0; 1599 switch (NVT.getSimpleVT().SimpleTy) { 1600 default: return 0; 1601 case MVT::i8: 1602 if (isCN) 1603 Opc = AtomicOpcTbl[Op][ConstantI8]; 1604 else 1605 Opc = AtomicOpcTbl[Op][I8]; 1606 break; 1607 case MVT::i16: 1608 if (isCN) { 1609 if (immSext8(Val.getNode())) 1610 Opc = AtomicOpcTbl[Op][SextConstantI16]; 1611 else 1612 Opc = AtomicOpcTbl[Op][ConstantI16]; 1613 } else 1614 Opc = AtomicOpcTbl[Op][I16]; 1615 break; 1616 case MVT::i32: 1617 if (isCN) { 1618 if (immSext8(Val.getNode())) 1619 Opc = AtomicOpcTbl[Op][SextConstantI32]; 1620 else 1621 Opc = AtomicOpcTbl[Op][ConstantI32]; 1622 } else 1623 Opc = AtomicOpcTbl[Op][I32]; 1624 break; 1625 case MVT::i64: 1626 Opc = AtomicOpcTbl[Op][I64]; 1627 if (isCN) { 1628 if (immSext8(Val.getNode())) 1629 Opc = AtomicOpcTbl[Op][SextConstantI64]; 1630 else if (i64immSExt32(Val.getNode())) 1631 Opc = AtomicOpcTbl[Op][ConstantI64]; 1632 } 1633 break; 1634 } 1635 1636 assert(Opc != 0 && "Invalid arith lock transform!"); 1637 1638 DebugLoc dl = Node->getDebugLoc(); 1639 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, 1640 dl, NVT), 0); 1641 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); 1642 MemOp[0] = cast<MemSDNode>(Node)->getMemOperand(); 1643 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; 1644 SDValue Ret = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops, 7), 0); 1645 cast<MachineSDNode>(Ret)->setMemRefs(MemOp, MemOp + 1); 1646 SDValue RetVals[] = { Undef, Ret }; 1647 return CurDAG->getMergeValues(RetVals, 2, dl).getNode(); 1648 } 1649 1650 /// HasNoSignedComparisonUses - Test whether the given X86ISD::CMP node has 1651 /// any uses which require the SF or OF bits to be accurate. 1652 static bool HasNoSignedComparisonUses(SDNode *N) { 1653 // Examine each user of the node. 1654 for (SDNode::use_iterator UI = N->use_begin(), 1655 UE = N->use_end(); UI != UE; ++UI) { 1656 // Only examine CopyToReg uses. 1657 if (UI->getOpcode() != ISD::CopyToReg) 1658 return false; 1659 // Only examine CopyToReg uses that copy to EFLAGS. 1660 if (cast<RegisterSDNode>(UI->getOperand(1))->getReg() != 1661 X86::EFLAGS) 1662 return false; 1663 // Examine each user of the CopyToReg use. 1664 for (SDNode::use_iterator FlagUI = UI->use_begin(), 1665 FlagUE = UI->use_end(); FlagUI != FlagUE; ++FlagUI) { 1666 // Only examine the Flag result. 1667 if (FlagUI.getUse().getResNo() != 1) continue; 1668 // Anything unusual: assume conservatively. 1669 if (!FlagUI->isMachineOpcode()) return false; 1670 // Examine the opcode of the user. 1671 switch (FlagUI->getMachineOpcode()) { 1672 // These comparisons don't treat the most significant bit specially. 1673 case X86::SETAr: case X86::SETAEr: case X86::SETBr: case X86::SETBEr: 1674 case X86::SETEr: case X86::SETNEr: case X86::SETPr: case X86::SETNPr: 1675 case X86::SETAm: case X86::SETAEm: case X86::SETBm: case X86::SETBEm: 1676 case X86::SETEm: case X86::SETNEm: case X86::SETPm: case X86::SETNPm: 1677 case X86::JA_4: case X86::JAE_4: case X86::JB_4: case X86::JBE_4: 1678 case X86::JE_4: case X86::JNE_4: case X86::JP_4: case X86::JNP_4: 1679 case X86::CMOVA16rr: case X86::CMOVA16rm: 1680 case X86::CMOVA32rr: case X86::CMOVA32rm: 1681 case X86::CMOVA64rr: case X86::CMOVA64rm: 1682 case X86::CMOVAE16rr: case X86::CMOVAE16rm: 1683 case X86::CMOVAE32rr: case X86::CMOVAE32rm: 1684 case X86::CMOVAE64rr: case X86::CMOVAE64rm: 1685 case X86::CMOVB16rr: case X86::CMOVB16rm: 1686 case X86::CMOVB32rr: case X86::CMOVB32rm: 1687 case X86::CMOVB64rr: case X86::CMOVB64rm: 1688 case X86::CMOVBE16rr: case X86::CMOVBE16rm: 1689 case X86::CMOVBE32rr: case X86::CMOVBE32rm: 1690 case X86::CMOVBE64rr: case X86::CMOVBE64rm: 1691 case X86::CMOVE16rr: case X86::CMOVE16rm: 1692 case X86::CMOVE32rr: case X86::CMOVE32rm: 1693 case X86::CMOVE64rr: case X86::CMOVE64rm: 1694 case X86::CMOVNE16rr: case X86::CMOVNE16rm: 1695 case X86::CMOVNE32rr: case X86::CMOVNE32rm: 1696 case X86::CMOVNE64rr: case X86::CMOVNE64rm: 1697 case X86::CMOVNP16rr: case X86::CMOVNP16rm: 1698 case X86::CMOVNP32rr: case X86::CMOVNP32rm: 1699 case X86::CMOVNP64rr: case X86::CMOVNP64rm: 1700 case X86::CMOVP16rr: case X86::CMOVP16rm: 1701 case X86::CMOVP32rr: case X86::CMOVP32rm: 1702 case X86::CMOVP64rr: case X86::CMOVP64rm: 1703 continue; 1704 // Anything else: assume conservatively. 1705 default: return false; 1706 } 1707 } 1708 } 1709 return true; 1710 } 1711 1712 SDNode *X86DAGToDAGISel::Select(SDNode *Node) { 1713 EVT NVT = Node->getValueType(0); 1714 unsigned Opc, MOpc; 1715 unsigned Opcode = Node->getOpcode(); 1716 DebugLoc dl = Node->getDebugLoc(); 1717 1718 DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n'); 1719 1720 if (Node->isMachineOpcode()) { 1721 DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n'); 1722 return NULL; // Already selected. 1723 } 1724 1725 switch (Opcode) { 1726 default: break; 1727 case X86ISD::GlobalBaseReg: 1728 return getGlobalBaseReg(); 1729 1730 case X86ISD::ATOMOR64_DAG: 1731 return SelectAtomic64(Node, X86::ATOMOR6432); 1732 case X86ISD::ATOMXOR64_DAG: 1733 return SelectAtomic64(Node, X86::ATOMXOR6432); 1734 case X86ISD::ATOMADD64_DAG: 1735 return SelectAtomic64(Node, X86::ATOMADD6432); 1736 case X86ISD::ATOMSUB64_DAG: 1737 return SelectAtomic64(Node, X86::ATOMSUB6432); 1738 case X86ISD::ATOMNAND64_DAG: 1739 return SelectAtomic64(Node, X86::ATOMNAND6432); 1740 case X86ISD::ATOMAND64_DAG: 1741 return SelectAtomic64(Node, X86::ATOMAND6432); 1742 case X86ISD::ATOMSWAP64_DAG: 1743 return SelectAtomic64(Node, X86::ATOMSWAP6432); 1744 1745 case ISD::ATOMIC_LOAD_ADD: { 1746 SDNode *RetVal = SelectAtomicLoadAdd(Node, NVT); 1747 if (RetVal) 1748 return RetVal; 1749 break; 1750 } 1751 case ISD::ATOMIC_LOAD_XOR: 1752 case ISD::ATOMIC_LOAD_AND: 1753 case ISD::ATOMIC_LOAD_OR: { 1754 SDNode *RetVal = SelectAtomicLoadArith(Node, NVT); 1755 if (RetVal) 1756 return RetVal; 1757 break; 1758 } 1759 case ISD::AND: 1760 case ISD::OR: 1761 case ISD::XOR: { 1762 // For operations of the form (x << C1) op C2, check if we can use a smaller 1763 // encoding for C2 by transforming it into (x op (C2>>C1)) << C1. 1764 SDValue N0 = Node->getOperand(0); 1765 SDValue N1 = Node->getOperand(1); 1766 1767 if (N0->getOpcode() != ISD::SHL || !N0->hasOneUse()) 1768 break; 1769 1770 // i8 is unshrinkable, i16 should be promoted to i32. 1771 if (NVT != MVT::i32 && NVT != MVT::i64) 1772 break; 1773 1774 ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1); 1775 ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1)); 1776 if (!Cst || !ShlCst) 1777 break; 1778 1779 int64_t Val = Cst->getSExtValue(); 1780 uint64_t ShlVal = ShlCst->getZExtValue(); 1781 1782 // Make sure that we don't change the operation by removing bits. 1783 // This only matters for OR and XOR, AND is unaffected. 1784 if (Opcode != ISD::AND && ((Val >> ShlVal) << ShlVal) != Val) 1785 break; 1786 1787 unsigned ShlOp, Op = 0; 1788 EVT CstVT = NVT; 1789 1790 // Check the minimum bitwidth for the new constant. 1791 // TODO: AND32ri is the same as AND64ri32 with zext imm. 1792 // TODO: MOV32ri+OR64r is cheaper than MOV64ri64+OR64rr 1793 // TODO: Using 16 and 8 bit operations is also possible for or32 & xor32. 1794 if (!isInt<8>(Val) && isInt<8>(Val >> ShlVal)) 1795 CstVT = MVT::i8; 1796 else if (!isInt<32>(Val) && isInt<32>(Val >> ShlVal)) 1797 CstVT = MVT::i32; 1798 1799 // Bail if there is no smaller encoding. 1800 if (NVT == CstVT) 1801 break; 1802 1803 switch (NVT.getSimpleVT().SimpleTy) { 1804 default: llvm_unreachable("Unsupported VT!"); 1805 case MVT::i32: 1806 assert(CstVT == MVT::i8); 1807 ShlOp = X86::SHL32ri; 1808 1809 switch (Opcode) { 1810 case ISD::AND: Op = X86::AND32ri8; break; 1811 case ISD::OR: Op = X86::OR32ri8; break; 1812 case ISD::XOR: Op = X86::XOR32ri8; break; 1813 } 1814 break; 1815 case MVT::i64: 1816 assert(CstVT == MVT::i8 || CstVT == MVT::i32); 1817 ShlOp = X86::SHL64ri; 1818 1819 switch (Opcode) { 1820 case ISD::AND: Op = CstVT==MVT::i8? X86::AND64ri8 : X86::AND64ri32; break; 1821 case ISD::OR: Op = CstVT==MVT::i8? X86::OR64ri8 : X86::OR64ri32; break; 1822 case ISD::XOR: Op = CstVT==MVT::i8? X86::XOR64ri8 : X86::XOR64ri32; break; 1823 } 1824 break; 1825 } 1826 1827 // Emit the smaller op and the shift. 1828 SDValue NewCst = CurDAG->getTargetConstant(Val >> ShlVal, CstVT); 1829 SDNode *New = CurDAG->getMachineNode(Op, dl, NVT, N0->getOperand(0),NewCst); 1830 return CurDAG->SelectNodeTo(Node, ShlOp, NVT, SDValue(New, 0), 1831 getI8Imm(ShlVal)); 1832 break; 1833 } 1834 case X86ISD::UMUL: { 1835 SDValue N0 = Node->getOperand(0); 1836 SDValue N1 = Node->getOperand(1); 1837 1838 unsigned LoReg; 1839 switch (NVT.getSimpleVT().SimpleTy) { 1840 default: llvm_unreachable("Unsupported VT!"); 1841 case MVT::i8: LoReg = X86::AL; Opc = X86::MUL8r; break; 1842 case MVT::i16: LoReg = X86::AX; Opc = X86::MUL16r; break; 1843 case MVT::i32: LoReg = X86::EAX; Opc = X86::MUL32r; break; 1844 case MVT::i64: LoReg = X86::RAX; Opc = X86::MUL64r; break; 1845 } 1846 1847 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, 1848 N0, SDValue()).getValue(1); 1849 1850 SDVTList VTs = CurDAG->getVTList(NVT, NVT, MVT::i32); 1851 SDValue Ops[] = {N1, InFlag}; 1852 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, VTs, Ops, 2); 1853 1854 ReplaceUses(SDValue(Node, 0), SDValue(CNode, 0)); 1855 ReplaceUses(SDValue(Node, 1), SDValue(CNode, 1)); 1856 ReplaceUses(SDValue(Node, 2), SDValue(CNode, 2)); 1857 return NULL; 1858 } 1859 1860 case ISD::SMUL_LOHI: 1861 case ISD::UMUL_LOHI: { 1862 SDValue N0 = Node->getOperand(0); 1863 SDValue N1 = Node->getOperand(1); 1864 1865 bool isSigned = Opcode == ISD::SMUL_LOHI; 1866 if (!isSigned) { 1867 switch (NVT.getSimpleVT().SimpleTy) { 1868 default: llvm_unreachable("Unsupported VT!"); 1869 case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break; 1870 case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break; 1871 case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break; 1872 case MVT::i64: Opc = X86::MUL64r; MOpc = X86::MUL64m; break; 1873 } 1874 } else { 1875 switch (NVT.getSimpleVT().SimpleTy) { 1876 default: llvm_unreachable("Unsupported VT!"); 1877 case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break; 1878 case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break; 1879 case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break; 1880 case MVT::i64: Opc = X86::IMUL64r; MOpc = X86::IMUL64m; break; 1881 } 1882 } 1883 1884 unsigned LoReg, HiReg; 1885 switch (NVT.getSimpleVT().SimpleTy) { 1886 default: llvm_unreachable("Unsupported VT!"); 1887 case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break; 1888 case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break; 1889 case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break; 1890 case MVT::i64: LoReg = X86::RAX; HiReg = X86::RDX; break; 1891 } 1892 1893 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 1894 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 1895 // Multiply is commmutative. 1896 if (!foldedLoad) { 1897 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 1898 if (foldedLoad) 1899 std::swap(N0, N1); 1900 } 1901 1902 SDValue InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, LoReg, 1903 N0, SDValue()).getValue(1); 1904 1905 if (foldedLoad) { 1906 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 1907 InFlag }; 1908 SDNode *CNode = 1909 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops, 1910 array_lengthof(Ops)); 1911 InFlag = SDValue(CNode, 1); 1912 1913 // Update the chain. 1914 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 1915 } else { 1916 SDNode *CNode = CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag); 1917 InFlag = SDValue(CNode, 0); 1918 } 1919 1920 // Prevent use of AH in a REX instruction by referencing AX instead. 1921 if (HiReg == X86::AH && Subtarget->is64Bit() && 1922 !SDValue(Node, 1).use_empty()) { 1923 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1924 X86::AX, MVT::i16, InFlag); 1925 InFlag = Result.getValue(2); 1926 // Get the low part if needed. Don't use getCopyFromReg for aliasing 1927 // registers. 1928 if (!SDValue(Node, 0).use_empty()) 1929 ReplaceUses(SDValue(Node, 1), 1930 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 1931 1932 // Shift AX down 8 bits. 1933 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, 1934 Result, 1935 CurDAG->getTargetConstant(8, MVT::i8)), 0); 1936 // Then truncate it down to i8. 1937 ReplaceUses(SDValue(Node, 1), 1938 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 1939 } 1940 // Copy the low half of the result, if it is needed. 1941 if (!SDValue(Node, 0).use_empty()) { 1942 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1943 LoReg, NVT, InFlag); 1944 InFlag = Result.getValue(2); 1945 ReplaceUses(SDValue(Node, 0), Result); 1946 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 1947 } 1948 // Copy the high half of the result, if it is needed. 1949 if (!SDValue(Node, 1).use_empty()) { 1950 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 1951 HiReg, NVT, InFlag); 1952 InFlag = Result.getValue(2); 1953 ReplaceUses(SDValue(Node, 1), Result); 1954 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 1955 } 1956 1957 return NULL; 1958 } 1959 1960 case ISD::SDIVREM: 1961 case ISD::UDIVREM: { 1962 SDValue N0 = Node->getOperand(0); 1963 SDValue N1 = Node->getOperand(1); 1964 1965 bool isSigned = Opcode == ISD::SDIVREM; 1966 if (!isSigned) { 1967 switch (NVT.getSimpleVT().SimpleTy) { 1968 default: llvm_unreachable("Unsupported VT!"); 1969 case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break; 1970 case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break; 1971 case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break; 1972 case MVT::i64: Opc = X86::DIV64r; MOpc = X86::DIV64m; break; 1973 } 1974 } else { 1975 switch (NVT.getSimpleVT().SimpleTy) { 1976 default: llvm_unreachable("Unsupported VT!"); 1977 case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break; 1978 case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break; 1979 case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break; 1980 case MVT::i64: Opc = X86::IDIV64r; MOpc = X86::IDIV64m; break; 1981 } 1982 } 1983 1984 unsigned LoReg, HiReg, ClrReg; 1985 unsigned ClrOpcode, SExtOpcode; 1986 switch (NVT.getSimpleVT().SimpleTy) { 1987 default: llvm_unreachable("Unsupported VT!"); 1988 case MVT::i8: 1989 LoReg = X86::AL; ClrReg = HiReg = X86::AH; 1990 ClrOpcode = 0; 1991 SExtOpcode = X86::CBW; 1992 break; 1993 case MVT::i16: 1994 LoReg = X86::AX; HiReg = X86::DX; 1995 ClrOpcode = X86::MOV16r0; ClrReg = X86::DX; 1996 SExtOpcode = X86::CWD; 1997 break; 1998 case MVT::i32: 1999 LoReg = X86::EAX; ClrReg = HiReg = X86::EDX; 2000 ClrOpcode = X86::MOV32r0; 2001 SExtOpcode = X86::CDQ; 2002 break; 2003 case MVT::i64: 2004 LoReg = X86::RAX; ClrReg = HiReg = X86::RDX; 2005 ClrOpcode = X86::MOV64r0; 2006 SExtOpcode = X86::CQO; 2007 break; 2008 } 2009 2010 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; 2011 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); 2012 bool signBitIsZero = CurDAG->SignBitIsZero(N0); 2013 2014 SDValue InFlag; 2015 if (NVT == MVT::i8 && (!isSigned || signBitIsZero)) { 2016 // Special case for div8, just use a move with zero extension to AX to 2017 // clear the upper 8 bits (AH). 2018 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; 2019 if (TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) { 2020 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N0.getOperand(0) }; 2021 Move = 2022 SDValue(CurDAG->getMachineNode(X86::MOVZX32rm8, dl, MVT::i32, 2023 MVT::Other, Ops, 2024 array_lengthof(Ops)), 0); 2025 Chain = Move.getValue(1); 2026 ReplaceUses(N0.getValue(1), Chain); 2027 } else { 2028 Move = 2029 SDValue(CurDAG->getMachineNode(X86::MOVZX32rr8, dl, MVT::i32, N0),0); 2030 Chain = CurDAG->getEntryNode(); 2031 } 2032 Chain = CurDAG->getCopyToReg(Chain, dl, X86::EAX, Move, SDValue()); 2033 InFlag = Chain.getValue(1); 2034 } else { 2035 InFlag = 2036 CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, 2037 LoReg, N0, SDValue()).getValue(1); 2038 if (isSigned && !signBitIsZero) { 2039 // Sign extend the low part into the high part. 2040 InFlag = 2041 SDValue(CurDAG->getMachineNode(SExtOpcode, dl, MVT::Glue, InFlag),0); 2042 } else { 2043 // Zero out the high part, effectively zero extending the input. 2044 SDValue ClrNode = 2045 SDValue(CurDAG->getMachineNode(ClrOpcode, dl, NVT), 0); 2046 InFlag = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, ClrReg, 2047 ClrNode, InFlag).getValue(1); 2048 } 2049 } 2050 2051 if (foldedLoad) { 2052 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, N1.getOperand(0), 2053 InFlag }; 2054 SDNode *CNode = 2055 CurDAG->getMachineNode(MOpc, dl, MVT::Other, MVT::Glue, Ops, 2056 array_lengthof(Ops)); 2057 InFlag = SDValue(CNode, 1); 2058 // Update the chain. 2059 ReplaceUses(N1.getValue(1), SDValue(CNode, 0)); 2060 } else { 2061 InFlag = 2062 SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, N1, InFlag), 0); 2063 } 2064 2065 // Prevent use of AH in a REX instruction by referencing AX instead. 2066 // Shift it down 8 bits. 2067 if (HiReg == X86::AH && Subtarget->is64Bit() && 2068 !SDValue(Node, 1).use_empty()) { 2069 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2070 X86::AX, MVT::i16, InFlag); 2071 InFlag = Result.getValue(2); 2072 2073 // If we also need AL (the quotient), get it by extracting a subreg from 2074 // Result. The fast register allocator does not like multiple CopyFromReg 2075 // nodes using aliasing registers. 2076 if (!SDValue(Node, 0).use_empty()) 2077 ReplaceUses(SDValue(Node, 0), 2078 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2079 2080 // Shift AX right by 8 bits instead of using AH. 2081 Result = SDValue(CurDAG->getMachineNode(X86::SHR16ri, dl, MVT::i16, 2082 Result, 2083 CurDAG->getTargetConstant(8, MVT::i8)), 2084 0); 2085 ReplaceUses(SDValue(Node, 1), 2086 CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, MVT::i8, Result)); 2087 } 2088 // Copy the division (low) result, if it is needed. 2089 if (!SDValue(Node, 0).use_empty()) { 2090 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2091 LoReg, NVT, InFlag); 2092 InFlag = Result.getValue(2); 2093 ReplaceUses(SDValue(Node, 0), Result); 2094 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 2095 } 2096 // Copy the remainder (high) result, if it is needed. 2097 if (!SDValue(Node, 1).use_empty()) { 2098 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl, 2099 HiReg, NVT, InFlag); 2100 InFlag = Result.getValue(2); 2101 ReplaceUses(SDValue(Node, 1), Result); 2102 DEBUG(dbgs() << "=> "; Result.getNode()->dump(CurDAG); dbgs() << '\n'); 2103 } 2104 return NULL; 2105 } 2106 2107 case X86ISD::CMP: { 2108 SDValue N0 = Node->getOperand(0); 2109 SDValue N1 = Node->getOperand(1); 2110 2111 // Look for (X86cmp (and $op, $imm), 0) and see if we can convert it to 2112 // use a smaller encoding. 2113 if (N0.getOpcode() == ISD::TRUNCATE && N0.hasOneUse() && 2114 HasNoSignedComparisonUses(Node)) 2115 // Look past the truncate if CMP is the only use of it. 2116 N0 = N0.getOperand(0); 2117 if (N0.getNode()->getOpcode() == ISD::AND && N0.getNode()->hasOneUse() && 2118 N0.getValueType() != MVT::i8 && 2119 X86::isZeroNode(N1)) { 2120 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1)); 2121 if (!C) break; 2122 2123 // For example, convert "testl %eax, $8" to "testb %al, $8" 2124 if ((C->getZExtValue() & ~UINT64_C(0xff)) == 0 && 2125 (!(C->getZExtValue() & 0x80) || 2126 HasNoSignedComparisonUses(Node))) { 2127 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8); 2128 SDValue Reg = N0.getNode()->getOperand(0); 2129 2130 // On x86-32, only the ABCD registers have 8-bit subregisters. 2131 if (!Subtarget->is64Bit()) { 2132 TargetRegisterClass *TRC = 0; 2133 switch (N0.getValueType().getSimpleVT().SimpleTy) { 2134 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2135 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2136 default: llvm_unreachable("Unsupported TEST operand type!"); 2137 } 2138 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2139 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2140 Reg.getValueType(), Reg, RC), 0); 2141 } 2142 2143 // Extract the l-register. 2144 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit, dl, 2145 MVT::i8, Reg); 2146 2147 // Emit a testb. 2148 return CurDAG->getMachineNode(X86::TEST8ri, dl, MVT::i32, Subreg, Imm); 2149 } 2150 2151 // For example, "testl %eax, $2048" to "testb %ah, $8". 2152 if ((C->getZExtValue() & ~UINT64_C(0xff00)) == 0 && 2153 (!(C->getZExtValue() & 0x8000) || 2154 HasNoSignedComparisonUses(Node))) { 2155 // Shift the immediate right by 8 bits. 2156 SDValue ShiftedImm = CurDAG->getTargetConstant(C->getZExtValue() >> 8, 2157 MVT::i8); 2158 SDValue Reg = N0.getNode()->getOperand(0); 2159 2160 // Put the value in an ABCD register. 2161 TargetRegisterClass *TRC = 0; 2162 switch (N0.getValueType().getSimpleVT().SimpleTy) { 2163 case MVT::i64: TRC = &X86::GR64_ABCDRegClass; break; 2164 case MVT::i32: TRC = &X86::GR32_ABCDRegClass; break; 2165 case MVT::i16: TRC = &X86::GR16_ABCDRegClass; break; 2166 default: llvm_unreachable("Unsupported TEST operand type!"); 2167 } 2168 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32); 2169 Reg = SDValue(CurDAG->getMachineNode(X86::COPY_TO_REGCLASS, dl, 2170 Reg.getValueType(), Reg, RC), 0); 2171 2172 // Extract the h-register. 2173 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_8bit_hi, dl, 2174 MVT::i8, Reg); 2175 2176 // Emit a testb. The EXTRACT_SUBREG becomes a COPY that can only 2177 // target GR8_NOREX registers, so make sure the register class is 2178 // forced. 2179 return CurDAG->getMachineNode(X86::TEST8ri_NOREX, dl, MVT::i32, 2180 Subreg, ShiftedImm); 2181 } 2182 2183 // For example, "testl %eax, $32776" to "testw %ax, $32776". 2184 if ((C->getZExtValue() & ~UINT64_C(0xffff)) == 0 && 2185 N0.getValueType() != MVT::i16 && 2186 (!(C->getZExtValue() & 0x8000) || 2187 HasNoSignedComparisonUses(Node))) { 2188 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16); 2189 SDValue Reg = N0.getNode()->getOperand(0); 2190 2191 // Extract the 16-bit subregister. 2192 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_16bit, dl, 2193 MVT::i16, Reg); 2194 2195 // Emit a testw. 2196 return CurDAG->getMachineNode(X86::TEST16ri, dl, MVT::i32, Subreg, Imm); 2197 } 2198 2199 // For example, "testq %rax, $268468232" to "testl %eax, $268468232". 2200 if ((C->getZExtValue() & ~UINT64_C(0xffffffff)) == 0 && 2201 N0.getValueType() == MVT::i64 && 2202 (!(C->getZExtValue() & 0x80000000) || 2203 HasNoSignedComparisonUses(Node))) { 2204 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32); 2205 SDValue Reg = N0.getNode()->getOperand(0); 2206 2207 // Extract the 32-bit subregister. 2208 SDValue Subreg = CurDAG->getTargetExtractSubreg(X86::sub_32bit, dl, 2209 MVT::i32, Reg); 2210 2211 // Emit a testl. 2212 return CurDAG->getMachineNode(X86::TEST32ri, dl, MVT::i32, Subreg, Imm); 2213 } 2214 } 2215 break; 2216 } 2217 } 2218 2219 SDNode *ResNode = SelectCode(Node); 2220 2221 DEBUG(dbgs() << "=> "; 2222 if (ResNode == NULL || ResNode == Node) 2223 Node->dump(CurDAG); 2224 else 2225 ResNode->dump(CurDAG); 2226 dbgs() << '\n'); 2227 2228 return ResNode; 2229 } 2230 2231 bool X86DAGToDAGISel:: 2232 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode, 2233 std::vector<SDValue> &OutOps) { 2234 SDValue Op0, Op1, Op2, Op3, Op4; 2235 switch (ConstraintCode) { 2236 case 'o': // offsetable ?? 2237 case 'v': // not offsetable ?? 2238 default: return true; 2239 case 'm': // memory 2240 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4)) 2241 return true; 2242 break; 2243 } 2244 2245 OutOps.push_back(Op0); 2246 OutOps.push_back(Op1); 2247 OutOps.push_back(Op2); 2248 OutOps.push_back(Op3); 2249 OutOps.push_back(Op4); 2250 return false; 2251 } 2252 2253 /// createX86ISelDag - This pass converts a legalized DAG into a 2254 /// X86-specific DAG, ready for instruction scheduling. 2255 /// 2256 FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM, 2257 llvm::CodeGenOpt::Level OptLevel) { 2258 return new X86DAGToDAGISel(TM, OptLevel); 2259 } 2260
