| /external/llvm/test/MC/ARM/ |
| neont2-mov-encoding.s | 5 vmov.i8 d16, #0x8
16 @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0xc0,0xef,0x18,0x0e]
28 vmov.i8 q8, #0x8
39 @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0xc0,0xef,0x58,0x0e]
|
| neon-mov-encoding.s | 3 vmov.i8 d16, #0x8
14 @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]
27 vmov.i8 q8, #0x8
38 @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2]
137 vmvn.i8 d1, d2
|
| neon-cmp-encoding.s | 3 vceq.i8 d16, d16, d17
7 vceq.i8 q8, q8, q9
12 @ CHECK: vceq.i8 d16, d16, d17 @ encoding: [0xb1,0x08,0x40,0xf3]
16 @ CHECK: vceq.i8 q8, q8, q9 @ encoding: [0xf2,0x08,0x40,0xf3]
103 vceq.i8 d16, d16, #0
109 @ CHECK: vceq.i8 d16, d16, #0 @ encoding: [0x20,0x01,0xf1,0xf3]
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMSelectionDAGInfo.cpp | 101 VT = MVT::i8;
123 VT = MVT::i8;
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neon-mov-encoding.s | 4 vmov.i8 d16, #0x8
15 @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2]
28 vmov.i8 q8, #0x8
39 @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2]
|
| neon-sub-encoding.s | 3 @ CHECK: vsub.i8 d16, d17, d16 @ encoding: [0xa0,0x08,0x41,0xf3]
4 vsub.i8 d16, d17, d16
13 @ CHECK: vsub.i8 q8, q8, q9 @ encoding: [0xe2,0x08,0x40,0xf3]
14 vsub.i8 q8, q8, q9
|
| neont2-mov-encoding.s | 6 @ CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xef]
7 vmov.i8 d16, #0x8
26 @ CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xef]
27 vmov.i8 q8, #0x8
|
| /external/webp/src/dsp/ |
| common_sse2.h | 35 uint8_t i8[16];
43 for (n = 0; n < 16; ++n) fprintf(stderr, "%.2x ", tmp.i8[n]);
|
| /frameworks/rs/script_api/ |
| rs_debug.spec | 81 t: i8, u8, i16, u16
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 82 // X86 is weird. It always uses i8 for shift amounts and setcc results.
135 addRegisterClass(MVT::i8, &X86::GR8RegClass);
147 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
149 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
150 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
165 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
184 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
187 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
204 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
207 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote)
[all...] |
| X86ISelDAGToDAG.cpp | 362 /// Return a target constant with the specified value of type i8.
364 return CurDAG->getTargetConstant(Imm, DL, MVT::i8);
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 39 i8 = 2, // This is an 8 bit integer value
67 v1i8 = 21, // 1 x i8
68 v2i8 = 22, // 2 x i8
69 v4i8 = 23, // 4 x i8
70 v8i8 = 24, // 8 x i8
71 v16i8 = 25, // 16 x i8
72 v32i8 = 26, // 32 x i8
73 v64i8 = 27, // 64 x i8
74 v128i8 = 28, //128 x i8
75 v256i8 = 29, //256 x i8
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 39 i8 = 2, // This is an 8 bit integer value
67 v1i8 = 21, // 1 x i8
68 v2i8 = 22, // 2 x i8
69 v4i8 = 23, // 4 x i8
70 v8i8 = 24, // 8 x i8
71 v16i8 = 25, // 16 x i8
72 v32i8 = 26, // 32 x i8
73 v64i8 = 27, // 64 x i8
74 v128i8 = 28, //128 x i8
75 v256i8 = 29, //256 x i8
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | 290 case MVT::i8:
924 /// simple value type such as i1, i8, and i16.
[all...] |
| /external/llvm/test/Bindings/OCaml/ |
| core.ml | 939 (* CHECK: ret { i8, i64 } { i8 4, i64 5 }
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 473 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
710 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
827 case MVT::i8:
[all...] |
| /external/libavc/encoder/arm/ |
| ih264e_half_pel.s | 88 vmov.i8 d0, #5
91 vmov.i8 d1, #20
276 vmov.i8 d1, #20
295 vmov.i8 d31, #5
395 vmov.i8 d31, #5
500 vmov.i8 d31, #5
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFastISel.cpp | 108 case MVT::i8:
393 case MVT::i8:
420 case MVT::i8:
585 case MVT::i8:
645 case MVT::i8:
739 case MVT::i8:
986 case MVT::i8:
1041 case MVT::i8:
[all...] |
| /external/boringssl/src/crypto/fipsmodule/aes/asm/ |
| bsaes-armv7.pl | 695 vmov.i8 $t0,#0x55 @ compose .LBS0
696 vmov.i8 $t1,#0x33 @ compose .LBS1
701 vmov.i8 $t0,#0x0f @ compose .LBS2
963 vmov.i8 @XMM[8], #0x01 @ bit masks
964 vmov.i8 @XMM[9], #0x02
965 vmov.i8 @XMM[10], #0x04
966 vmov.i8 @XMM[11], #0x08
967 vmov.i8 @XMM[12], #0x10
968 vmov.i8 @XMM[13], #0x20
983 vmov.i8 @XMM[6], #0x4
[all...] |
| /external/v8/src/builtins/ |
| builtins-sharedarraybuffer.cc | 176 CodeStubAssembler::Label i8(&a), u8(&a), i16(&a), u16(&a), i32(&a), u32(&a),
183 &i8, &u8, &i16, &u16, &i32, &u32,
188 a.Bind(&i8);
|
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | 310 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1)
575 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16)
587 if (VT == MVT::i8 || VT == MVT::i16)
734 case MVT::i8: {
785 case MVT::i8:
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86FastISel.cpp | 184 case MVT::i8:
248 // FALLTHROUGH, handling i1 as i8.
249 case MVT::i8: Opc = X86::MOV8mr; break;
280 case MVT::i1: Signed = false; // FALLTHROUGH to handle as i8.
281 case MVT::i8: Opc = X86::MOV8mi; break;
758 if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16)
769 SrcReg = FastEmitZExtFromI1(MVT::i8, SrcReg, /*TODO: Kill=*/false);
770 SrcVT = MVT::i8;
826 case MVT::i8: return X86::CMP8rr;
844 case MVT::i8: return X86::CMP8ri
[all...] |
| X86ISelLowering.cpp | 180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 };
182 // X86 is weird, it always uses i8 for shift amounts and setcc results.
227 addRegisterClass(MVT::i8, X86::GR8RegisterClass);
238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand);
240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand);
241 setTruncStoreAction(MVT::i16, MVT::i8, Expand);
254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't hav
[all...] |
| /external/boringssl/src/crypto/fipsmodule/modes/asm/ |
| ghashv8-armx.pl | 92 vmov.i8 $xC2,#0xe1
151 vmov.i8 $xC2,#0xe1
224 vmov.i8 $xC2,#0xe1
365 s/vmov\.i8/movi/o or # fix up legacy mnemonics
|
| /external/capstone/suite/MC/ARM/ |
| neon-mov-encoding.s.cs | 2 0x18,0x0e,0xc0,0xf2 = vmov.i8 d16, #0x8
12 0x58,0x0e,0xc0,0xf2 = vmov.i8 q8, #0x8
|
