| /external/capstone/suite/MC/ARM/ |
| neont2-add-encoding.s.cs | 4 0x71,0xef,0xa0,0x08 = vadd.i64 d16, d17, d16
62 0xe0,0xef,0xa2,0x04 = vaddhn.i64 d16, q8, q9
65 0xe0,0xff,0xa2,0x04 = vraddhn.i64 d16, q8, q9
|
| neont2-shift-encoding.s.cs | 9 0xff,0xef,0xb0,0x05 = vshl.i64 d16, d16, #63
17 0xff,0xef,0xf0,0x05 = vshl.i64 q8, q8, #63
45 0xe0,0xef,0x30,0x08 = vshrn.i64 d16, q8, #32
80 0xe0,0xef,0x70,0x08 = vrshrn.i64 d16, q8, #32
|
| /external/libhevc/common/arm/ |
| ihevc_inter_pred_chroma_copy_w16out.s | 144 vshl.i64 q0,q0,#6 @vshlq_n_s64(temp, 6)
151 vshl.i64 q11,q11,#6 @vshlq_n_s64(temp, 6)
154 vshl.i64 q12,q12,#6 @vshlq_n_s64(temp, 6)
158 vshl.i64 q13,q13,#6 @vshlq_n_s64(temp, 6)
186 vshl.i64 q0,q0,#6 @vshlq_n_s64(temp, 6)
193 vshl.i64 q11,q11,#6 @vshlq_n_s64(temp, 6)
|
| ihevc_inter_pred_luma_copy_w16out.s | 112 vshl.i64 q0,q0,#6 @vshlq_n_s64(temp, 6)
119 vshl.i64 q11,q11,#6 @vshlq_n_s64(temp, 6)
122 vshl.i64 q12,q12,#6 @vshlq_n_s64(temp, 6)
126 vshl.i64 q13,q13,#6 @vshlq_n_s64(temp, 6)
|
| /prebuilts/go/darwin-x86/test/ |
| zerodivide.go | 29 i64, j64, k64 int64 = 0, 0, 1
63 i64++
121 ErrorTest{"int64 0/0", func() { use(i64 / j64) }, "divide"},
28 i64, j64, k64 int64 = 0, 0, 1 var
|
| rotate.go | 54 i64 int64 = 0x123456789abcdef0
63 ni64 = ^i64
|
| /prebuilts/go/linux-x86/test/ |
| zerodivide.go | 29 i64, j64, k64 int64 = 0, 0, 1
63 i64++
121 ErrorTest{"int64 0/0", func() { use(i64 / j64) }, "divide"},
28 i64, j64, k64 int64 = 0, 0, 1 var
|
| rotate.go | 54 i64 int64 = 0x123456789abcdef0
63 ni64 = ^i64
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
110 setOperationAction(ISD::SREM, MVT::i64, Expand);
111 setOperationAction(ISD::UREM, MVT::i64, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
150 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
151 setOperationAction(ISD::CTPOP, MVT::i64 , Expand)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 101 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
108 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
118 isPPC64 ? MVT::i64 : MVT::i32);
121 isPPC64 ? MVT::i64 : MVT::i32);
159 setOperationAction(ISD::SREM, MVT::i64, Expand);
160 setOperationAction(ISD::UREM, MVT::i64, Expand);
165 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
166 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
169 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
170 setOperationAction(ISD::SDIVREM, MVT::i64, Expand)
[all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFastISel.cpp | 112 case MVT::i64:
452 if (To == MVT::i64) {
453 if (From == MVT::i64)
471 if (To == MVT::i64) {
472 if (From == MVT::i64)
591 case MVT::i64:
651 case MVT::i64:
745 case MVT::i64:
821 bool I32 = getSimpleType(ICmp->getOperand(0)->getType()) != MVT::i64;
998 case MVT::i64
[all...] |
| /external/llvm/test/MC/ARM/ |
| neont2-add-encoding.s | 9 @ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0x71,0xef,0xa0,0x08]
10 vadd.i64 d16, d17, d16
131 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xef,0xa2,0x04]
132 vaddhn.i64 d16, q8, q9
137 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xff,0xa2,0x04]
138 vraddhn.i64 d16, q8, q9
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| neon-add-encoding.s | 8 @ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0xa0,0x08,0x71,0xf2]
9 vadd.i64 d16, d17, d16
130 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2]
131 vaddhn.i64 d16, q8, q9
136 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf3]
137 vraddhn.i64 d16, q8, q9
|
| neont2-add-encoding.s | 9 @ CHECK: vadd.i64 d16, d17, d16 @ encoding: [0x71,0xef,0xa0,0x08]
10 vadd.i64 d16, d17, d16
131 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xef,0xa2,0x04]
132 vaddhn.i64 d16, q8, q9
137 @ CHECK: vraddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xff,0xa2,0x04]
138 vraddhn.i64 d16, q8, q9
|
| neon-shift-encoding.s | 18 @ CHECK: vshl.i64 d16, d16, #63 @ encoding: [0xb0,0x05,0xff,0xf2]
19 vshl.i64 d16, d16, #63
34 @ CHECK: vshl.i64 q8, q8, #63 @ encoding: [0xf0,0x05,0xff,0xf2]
35 vshl.i64 q8, q8, #63
154 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
155 vshrn.i64 d16, q8, #32
224 @ CHECK: vrshrn.i64 d16, q8, #32 @ encoding: [0x70,0x08,0xe0,0xf2]
225 vrshrn.i64 d16, q8, #32
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZCallingConv.h | 85 // CCIfType<[i128], CCPassIndirect<i64>>,
87 // common code into a pair of i64 arguments.
101 LocVT = MVT::i64;
110 // (This duplicates the usual i64 calling convention rules.)
|
| SystemZISelDAGToDAG.cpp | 610 // Truncate values from i64 to i32, for shifts.
611 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 &&
809 if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64)
913 if (N.getValueType() == MVT::i32 && VT == MVT::i64)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 125 AVT = MVT::i64;
169 DAG.getConstant((AVT == MVT::i64) ? 7 : 3, dl,
171 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
239 AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
|
| /external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
| AlphaISelLowering.h | 66 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i64; }
|
| /external/tensorflow/tensorflow/contrib/lite/kernels/internal/ |
| tensor.h | 44 return tensor != nullptr ? tensor->data.i64 : nullptr;
|
| /frameworks/native/libs/sensor/include/sensor/ |
| Sensor.h | 58 int64_t i64[2]; member in union:android::Sensor::uuid_t::__anon46381
|
| /prebuilts/ndk/r16/sources/third_party/shaderc/third_party/glslang/glslang/Include/ |
| ConstantUnion.h | 60 void setI64Const(long long i64)
62 i64Const = i64;
114 bool operator==(const long long i64) const
116 if (i64 == i64Const)
|
| /external/clang/test/Sema/ |
| atomic-ops.c | 51 int __attribute__((vector_size(8))) i64; variable
55 _Static_assert(__atomic_is_lock_free(1, &i64), "");
58 _Static_assert(__atomic_is_lock_free(2, &i64), "");
61 _Static_assert(__atomic_is_lock_free(4, &i64), "");
63 _Static_assert(__atomic_is_lock_free(8, &i64), "");
78 _Static_assert(__atomic_always_lock_free(1, &i64), "");
81 _Static_assert(__atomic_always_lock_free(2, &i64), "");
84 _Static_assert(__atomic_always_lock_free(4, &i64), "");
86 _Static_assert(__atomic_always_lock_free(8, &i64), "");
|
| /external/flatbuffers/tests/MyGame/Example/ |
| TypeAliases.py | 64 def I64(self):
142 def TypeAliasesAddI64(builder, i64): builder.PrependInt64Slot(6, i64, 0)
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/Utils/ |
| X86ShuffleDecode.cpp | 115 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask);
160 DecodeUNPCKLPMask(MVT::getVectorVT(MVT::i64, NElts), ShuffleMask);
|
