/external/mesa3d/src/mesa/drivers/dri/i965/ |
brw_vec4_tes.cpp | 199 unsigned imm_offset = instr->const_index[0]; local 215 if (imm_offset < max_push_slots) { 218 src_reg src = src_reg(ATTR, imm_offset, src_glsl_type); 227 DIV_ROUND_UP(imm_offset + (is_64bit ? 2 : 1), 2)); 236 read->offset = imm_offset; 257 read->offset = imm_offset; 263 read->offset = imm_offset + 1;
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brw_vec4_tcs.cpp | 272 unsigned imm_offset = instr->const_index[0]; local 290 emit_input_urb_read(tmp_d, vertex_index, imm_offset, 294 imm_offset + 1, 0, indirect_offset); local 307 emit_input_urb_read(dst, vertex_index, imm_offset, 318 unsigned imm_offset = instr->const_index[0]; local 323 emit_output_urb_read(dst, imm_offset, nir_intrinsic_component(instr), 334 unsigned imm_offset = instr->const_index[0]; local 362 imm_offset, indirect_offset); 366 imm_offset++; 370 imm_offset, indirect_offset) local [all...] |
brw_fs_nir.cpp | [all...] |
/toolchain/binutils/binutils-2.27/bfd/ |
elf32-score.c | 2180 bfd_vma imm_offset = 0; local 2207 bfd_vma imm_offset = 0; local [all...] |
/external/llvm/lib/Target/AMDGPU/ |
SIInstrInfo.td | 428 (ops node:$ptr, node:$offset, node:$imm_offset), 429 (add (add node:$ptr, node:$offset), node:$imm_offset) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonFrameLowering.cpp | [all...] |