| /art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
| RandomInstructionGenerator.java | 45 public int newOpcode;
61 newOpcode,
79 newOpcode = Integer.parseInt(elements[3]);
126 Opcode newOpcode = null;
131 newOpcode = Opcode.values()[rng.nextInt(opcodeCount)];
133 if (Opcode.isBetween(newOpcode, Opcode.FILLED_NEW_ARRAY, Opcode.FILL_ARRAY_DATA)
134 || Opcode.isBetween(newOpcode, Opcode.PACKED_SWITCH, Opcode.SPARSE_SWITCH)
135 || Opcode.isBetween(newOpcode, Opcode.INVOKE_VIRTUAL, Opcode.INVOKE_INTERFACE)
136 || Opcode.isBetween(newOpcode,
139 || Opcode.isBetween(newOpcode, Opcode.IGET_QUICK, Opcode.IPUT_SHORT_QUICK
[all...] |
| ArithOpChanger.java | 40 public int newOpcode;
46 builder.append(newOpcode);
53 newOpcode = Integer.parseInt(elements[3]);
122 mutation.newOpcode = newOpcodeInfo.value;
138 OpcodeInfo newOpcodeInfo = Instruction.getOpcodeInfo(mutation.newOpcode);
|
| CmpBiasChanger.java | 121 Opcode newOpcode = getLegalDifferentOpcode(cmpBiasInsn);
123 cmpBiasInsn.insn.info = Instruction.getOpcodeInfo(newOpcode);
|
| IfBranchChanger.java | 127 Opcode newOpcode = getModifiedOpcode(ifBranchInsn);
129 ifBranchInsn.insn.info = Instruction.getOpcodeInfo(newOpcode);
|
| InvokeChanger.java | 139 Opcode newOpcode = getDifferentInvokeCallOpcode(invokeInsn);
141 invokeInsn.insn.info = Instruction.getOpcodeInfo(newOpcode);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonOptAddrMode.cpp | 317 short NewOpCode = HII->getBaseWithLongOffset(OldMI);
318 assert(NewOpCode >= 0 && "Invalid New opcode\n");
319 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
327 short NewOpCode = HII->getAbsoluteForm(OldMI);
328 assert(NewOpCode >= 0 && "Invalid New opcode\n");
329 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode))
343 short NewOpCode = HII->xformRegToImmOffset(OldMI);
344 assert(NewOpCode >= 0 && "Invalid New opcode\n");
345 MIB = BuildMI(*BB, InsertPt, OldMI->getDebugLoc(), HII->get(NewOpCode));
374 short NewOpCode = HII->getBaseWithLongOffset(OldMI)
[all...] |
| HexagonCFGOptimizer.cpp | 75 int NewOpcode = 0;
78 NewOpcode = Hexagon::J2_jumpf;
82 NewOpcode = Hexagon::J2_jumpt;
86 NewOpcode = Hexagon::J2_jumpfnewpt;
90 NewOpcode = Hexagon::J2_jumptnewpt;
97 MI.setDesc(TII->get(NewOpcode));
|
| HexagonVLIWPacketizer.cpp | 422 int NewOpcode;
424 NewOpcode = HII->getDotNewPredOp(MI, MBPI);
426 NewOpcode = HII->getDotNewOp(MI);
427 MI->setDesc(HII->get(NewOpcode));
432 int NewOpcode = HII->getDotOldOp(MI->getOpcode());
433 MI->setDesc(HII->get(NewOpcode));
768 int NewOpcode = HII->getDotNewOp(MI);
769 const MCInstrDesc &D = HII->get(NewOpcode);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 138 int NewOpcode;
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
147 BuildMI(MBB, II, dl, TII.get(NewOpcode))
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
|
| /external/swiftshader/third_party/LLVM/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 286 int NewOpcode;
288 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
289 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
293 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
294 BuildMI(MBB, II, dl, TII.get(NewOpcode))
299 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
300 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
|
| /dalvik/dx/src/com/android/dx/ssa/ |
| LiteralOpUpgrader.java | 185 * @param newOpcode A RegOp from {@link RegOps}
189 RegisterSpecList newSources, int newOpcode, Constant cst) {
192 Rop newRop = Rops.ropFor(newOpcode, insn.getResult(), newSources, cst);
|
| EscapeAnalysis.java | 784 * @param newOpcode opcode of new instruction
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FixupLEAs.cpp | 273 int NewOpcode;
277 NewOpcode = isINC ? X86::INC16r : X86::DEC16r;
281 NewOpcode = isINC ? X86::INC32r : X86::DEC32r;
284 NewOpcode = isINC ? X86::INC64r : X86::DEC64r;
289 BuildMI(*MFI, I, MI.getDebugLoc(), TII->get(NewOpcode))
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDILCFGStructurizer.cpp | 228 void insertInstrEnd(MachineBasicBlock *MBB, int NewOpcode,
230 MachineInstr *insertInstrBefore(MachineBasicBlock *MBB, int NewOpcode,
232 MachineInstr *insertInstrBefore(MachineBasicBlock::iterator I, int NewOpcode);
233 void insertCondBranchBefore(MachineBasicBlock::iterator I, int NewOpcode,
236 MachineBasicBlock::iterator I, int NewOpcode,
454 int NewOpcode, const DebugLoc &DL) {
456 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
463 int NewOpcode,
466 MBB->getParent()->CreateMachineInstr(TII->get(NewOpcode), DL);
476 MachineBasicBlock::iterator I, int NewOpcode) {
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 231 int NewOpcode = -1;
234 NewOpcode = Mips::MipsR62MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
235 if (NewOpcode == -1)
236 NewOpcode = Mips::Std2MicroMipsR6(Opcode, Mips::Arch_micromipsr6);
239 NewOpcode = Mips::Std2MicroMips(Opcode, Mips::Arch_micromips);
242 if (NewOpcode == -1)
243 NewOpcode = Mips::Dsp2MicroMips(Opcode, Mips::Arch_mmdsp);
245 if (NewOpcode != -1) {
249 Opcode = NewOpcode;
250 TmpInst.setOpcode (NewOpcode);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZFrameLowering.cpp | 458 unsigned NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
462 if (!NewOpcode) {
467 NewOpcode = ZII->getOpcodeForOffset(Opcode, Offset);
468 assert(NewOpcode && "No restore instruction available");
471 MBBI->setDesc(ZII->get(NewOpcode));
|
| SystemZInstrInfo.cpp | 50 // each having the opcode given by NewOpcode.
52 unsigned NewOpcode) const {
79 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
80 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
97 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
98 assert(NewOpcode && "No support for huge argument lists yet");
99 MI->setDesc(get(NewOpcode));
845 unsigned NewOpcode;
847 NewOpcode = SystemZ::RISBG;
850 NewOpcode = SystemZ::RISBGN
[all...] |
| /external/llvm/lib/Target/Lanai/ |
| LanaiRegisterInfo.cpp | 232 unsigned NewOpcode = getOppositeALULoOpcode(MI.getOpcode());
237 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
|
| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| sb_if_conversion.cpp | 261 unsigned newopcode = get_predsetcc_op(cc, cmptype); local
262 newpredset->bc.set_op(newopcode);
|
| /dalvik/dx/src/com/android/dx/dex/code/ |
| OutputFinisher.java | 516 Dop newOpcode = findOpcodeForInsn(insn, originalOpcode);
518 if (newOpcode == null) {
529 } else if (originalOpcode == newOpcode) {
533 opcodes[i] = newOpcode;
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 408 int64_t NewOpcode = MatchTable[CurrentIdx++];
413 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
415 << "], MIs[" << OldInsnID << "], " << NewOpcode << ")\n");
|
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 408 int64_t NewOpcode = MatchTable[CurrentIdx++];
413 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
415 << "], MIs[" << OldInsnID << "], " << NewOpcode << ")\n");
|
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 408 int64_t NewOpcode = MatchTable[CurrentIdx++];
413 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
415 << "], MIs[" << OldInsnID << "], " << NewOpcode << ")\n");
|
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 408 int64_t NewOpcode = MatchTable[CurrentIdx++];
413 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
415 << "], MIs[" << OldInsnID << "], " << NewOpcode << ")\n");
|
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 408 int64_t NewOpcode = MatchTable[CurrentIdx++];
413 OutMIs[NewInsnID]->setDesc(TII.get(NewOpcode));
415 << "], MIs[" << OldInsnID << "], " << NewOpcode << ")\n");
|
