| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/SmBiosMiscDxe/ |
| MiscSystemSlotDesignation.uni | 29 #string STR_MISC_SYSTEM_SLOT_PCIEX16 #language en-US "PCIE X16 SLOT"
30 #string STR_MISC_SYSTEM_SLOT_PCIEX16_1 #language en-US "PCIE X16 SLOT 1"
31 #string STR_MISC_SYSTEM_SLOT_PCIEX16_2 #language en-US "PCIE X16 SLOT 2"
32 #string STR_MISC_SYSTEM_SLOT_PCIEX4 #language en-US "PCIE X4 SLOT"
33 #string STR_MISC_SYSTEM_SLOT_PCIEX1_1 #language en-US "PCIE X1 SLOT 1"
34 #string STR_MISC_SYSTEM_SLOT_PCIEX1_2 #language en-US "PCIE X1 SLOT 2"
35 #string STR_MISC_SYSTEM_SLOT_PCIEX1_3 #language en-US "PCIE X1 SLOT 3"
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/PlatformDxe/ |
| SlotConfig.h | 63 0x01, //PCIe x1 ICH (Bridge B0:D28:F1)
78 {0x06, FALSE, TRUE}, // PCIe x16 Slot 1 (NOT USED)
79 {0x04, FALSE, TRUE}, // PCIe x16 Slot 2 (NOT USED)
80 {0x03, FALSE, TRUE}, // PCIe x4 Slot (NOT USED)
81 {0x02, FALSE, FALSE}, // Mini PCIe x1 Slot
82 {0x15, FALSE, TRUE}, // PCIe x1 Slot 2 (NOT USED)
83 {0x16, FALSE, TRUE}, // PCIe x1 Slot 3 (NOT USED)
|
| /hardware/qcom/msm8994/original-kernel-headers/linux/ |
| esoc_ctrl.h | 16 #define HSICPCIe "HSIC+PCIe"
17 #define PCIe "PCIe"
|
| /hardware/qcom/msm8996/original-kernel-headers/linux/ |
| esoc_ctrl.h | 16 #define HSICPCIe "HSIC+PCIe"
17 #define PCIe "PCIe"
|
| /hardware/qcom/msm8x84/original-kernel-headers/linux/ |
| esoc_ctrl.h | 16 #define HSICPCIe "HSIC+PCIe"
17 #define PCIe "PCIe"
|
| /device/linaro/bootloader/edk2/ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/ |
| XPressRich3.h | 2 * Header containing the Xpress-RICH3 PCIe Root Complex specific values
35 // PCIe Available Credit Settings
37 // PCIe PCI Standard Configuration Identification Settings registers
40 // PCIe Specific 2 Capabilities Settings
42 // PCIe Windows Settings register
61 * PCIe Control Registers
100 * Initialize Versatile Express PCIe Host Bridge
|
| XPressRich3.c | 2 * Initialize the XPress-RICH3 PCIe Root complex
73 PCI_TRACE ("PCIe Setting up Address Translation");
87 // PCIE Window 0 -> AXI4 Master 0 Address Translations
104 // AXI4 Slave 1 -> PCIE Window 0 Address Translations
145 DEBUG ((EFI_D_ERROR, "PCIe failed to come out of reset: %x.\n", Value));
163 DEBUG ((EFI_D_ERROR, "PCIe link not up: %x.\n", Value));
|
| PciHostBridgeDxe.inf | 2 # INF file for the Xpress-RICH3 PCIe Root Complex
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/PciSioSerialDxe/ |
| PciSioSerialDxe.uni | 2 // Serial driver for standard UARTS on a SIO chip or PCI/PCIE card.
19 #string STR_MODULE_ABSTRACT #language en-US "Serial driver for standard UARTS on a SIO chip or PCI/PCIE card."
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Library/PlatformPcieHelperLib/ |
| PlatformPcieHelperLib.c | 2 Platform Pcie Helper Lib.
87 /** Early initialisation of the PCIe controller.
109 // Early PCIe initialisation
114 // Do North cluster early PCIe init.
|
| /device/linaro/bootloader/arm-trusted-firmware/plat/arm/soc/common/ |
| soc_css_security.c | 53 * Do not initialize PCIe in emulator environment.
62 * PCIE Root Complex Security settings to enable non-secure
|
| /hardware/qcom/msm8994/kernel-headers/linux/ |
| esoc_ctrl.h | 32 #define HSICPCIe "HSIC+PCIe"
34 #define PCIe "PCIe"
|
| /hardware/qcom/msm8996/kernel-headers/linux/ |
| esoc_ctrl.h | 32 #define HSICPCIe "HSIC+PCIe"
34 #define PCIe "PCIe"
|
| /hardware/qcom/msm8x84/kernel-headers/linux/ |
| esoc_ctrl.h | 32 #define HSICPCIe "HSIC+PCIe"
34 #define PCIe "PCIe"
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660AcpiTables/Dsdt/ |
| Ctl.asl | 24 // sysctl pcie
|
| Pci.asl | 21 // PCIe Root bus
70 Name (_HID, "HISI0081") // HiSi PCIe RC config base address
101 // PCIe Root bus
150 Name (_HID, "HISI0081") // HiSi PCIe RC config base address
|
| /device/linaro/bootloader/edk2/OvmfPkg/PciHotPlugInitDxe/ |
| PciHotPlugInit.inf | 3 # driver with resource padding information, for PCIe hotplug purposes.
|
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/ |
| PciTree.asl | 129 // PCIE Root Port #1
131 // PCIE Root Port #2
133 // PCIE Root Port #3
135 // PCIE Root Port #4
201 // PCIE Root Port #1
203 // PCIE Root Port #2
205 // PCIE Root Port #3
207 // PCIE Root Port #4
216 // PCIE Port #1 Slot
225 // PCIE Port #1 Slot
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsPcie.h | 54 #define V_PCH_PCIE_DEVICE_ID_0 0x0F48 // PCIE Root Port #1
55 #define V_PCH_PCIE_DEVICE_ID_1 0x0F4A // PCIE Root Port #2
56 #define V_PCH_PCIE_DEVICE_ID_2 0x0F4C // PCIE Root Port #3
57 #define V_PCH_PCIE_DEVICE_ID_3 0x0F4E // PCIE Root Port #4
|
| /device/linaro/bootloader/arm-trusted-firmware/include/plat/arm/soc/common/ |
| soc_css_def.h | 18 /* Following covers ARM CSS SoC Peripherals and PCIe expansion area */
39 * - the PCIe configuration registers
|
| /device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Dxe/Setup/ |
| QNCRegTable.c | 34 // FNC 0: PCIe Port 0
36 // FNC 0: PCIe Port 1
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Hi1610AcpiTables/Dsdt/ |
| D03Pci.asl | 22 // PCIe Root bus
71 Name (_HID, "HISI0081") // HiSi PCIe RC config base address
101 // PCIe Root bus
150 Name (_HID, "HISI0081") // HiSi PCIe RC config base address
181 // PCIe Root bus
230 Name (_HID, "HISI0081") // HiSi PCIe RC config base address
|
| /device/linaro/bootloader/OpenPlatformPkg/Platforms/AMD/Styx/Binary/AmdModulePkg/Common/ |
| PostCode.h | 73 #define ERROR_PCIE_TRAIN_ERROR 0x261 ///< GIONB PCIE training error
74 #define ERROR_PCIE_SPEED_ERROR 0x262 ///< GIONB PCIE data rate error
75 #define ERROR_PCIE_PLL_ERROR 0x263 ///< GIONB PCIE PLL error
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/ |
| PcieInit.c | 145 and each bit stands for this PCIe Port is enable or not
154 DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
|
| /device/linaro/bootloader/OpenPlatformPkg/Chips/Hisilicon/Pv660/Drivers/PcieInitDxe/ |
| PcieInit.c | 96 DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
|
