| /device/linaro/bootloader/arm-trusted-firmware/include/lib/aarch32/ |
| smcc_macros.S | 16 * Additionally, also save the 'pmcr' register as this is updated whilst
51 ldcopr r4, PMCR
78 * Restore the PMCR register.
81 stcopr r1, PMCR
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| arch_helpers.h | 274 DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
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| smcc_helpers.h | 77 u_register_t pmcr; member in struct:smc_ctx
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| arch.h | 350 /* PMCR definitions */
431 #define PMCR p15, 0, c9, c12, 0
|
| /device/linaro/bootloader/arm-trusted-firmware/bl32/sp_min/aarch32/ |
| entrypoint.S | 166 * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode.
167 * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset
168 * and so set to 1 as ARM has deprecated use of PMCR.LC=0.
170 ldcopr r0, PMCR
172 stcopr r0, PMCR
223 * Set PMCR.DP to 1 to prohibit cycle counting whilst in Secure Mode.
224 * Also, the PMCR.LC field has an architecturally UNKNOWN value on reset
225 * and so set to 1 as ARM has deprecated use of PMCR.LC=0.
227 ldcopr r0, PMCR
229 stcopr r0, PMCR
[all...] |
| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/AcpiTablesPCAT/ |
| Pch.asl | 56 OperationRegion(PMCR, SystemMemory, \PFDR, 0x04)// PMC Function Disable Register
57 Field(PMCR,DWordAcc,Lock,Preserve)
336 Offset(0x00), // 0x74, PMCR
362 Offset(0x00), // 0x84, PMCR
404 Offset(0x00), // 0x84, PMCR
600 Offset(0x00), // 0x54, PMCR
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| /device/linaro/bootloader/arm-trusted-firmware/lib/el3_runtime/aarch32/ |
| context_mgmt.c | 262 * HDCR.HPMN: Set to value of PMCR.N which is the
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| /device/linaro/bootloader/arm-trusted-firmware/lib/el3_runtime/aarch64/ |
| context_mgmt.c | 372 * and EL1 accesses to the PMCR_EL0 or PMCR are not
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| /device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/aarch64/ |
| tegra_helpers.S | 113 ubfx x0, x0, #11, #5 // read PMCR.N field
|
