| /external/clang/test/CodeGen/ |
| systemz-abi.c | 147 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]]
148 // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5
150 // CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8
156 // CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1
171 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]]
172 // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5
174 // CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8
180 // CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1
195 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]]
196 // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]],
[all...] |
| systemz-abi-vector.c | 192 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]]
193 // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5
195 // CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8
201 // CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1
224 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]]
225 // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]], 5
227 // CHECK: [[SCALED_REG_COUNT:%[^ ]+]] = mul i64 [[REG_COUNT]], 8
233 // CHECK: [[REG_COUNT1:%[^ ]+]] = add i64 [[REG_COUNT]], 1
256 // CHECK: [[REG_COUNT:%[^ ]+]] = load i64, i64* [[REG_COUNT_PTR]]
257 // CHECK: [[FITS_IN_REGS:%[^ ]+]] = icmp ult i64 [[REG_COUNT]],
[all...] |
| /external/mesa3d/src/gallium/drivers/ilo/ |
| ilo_render.c | 265 int reg_count = 0, i; local
282 reg_count = 1;
286 reg_count = 1;
290 reg_count = ARRAY_SIZE(pipeline_statistics_regs);
297 assert(!reg_count);
306 } else if (reg_count) {
310 for (i = 0; i < reg_count; i++) {
|
| /external/vixl/test/aarch64/ |
| test-utils-aarch64.cc | 277 int reg_count,
281 for (unsigned n = 0; (n < kNumberOfRegisters) && (i < reg_count); n++) {
298 VIXL_ASSERT(CountSetBits(list, kNumberOfRegisters) == reg_count);
308 int reg_count,
312 for (unsigned n = 0; (n < kNumberOfFPRegisters) && (i < reg_count); n++) {
329 VIXL_ASSERT(CountSetBits(list, kNumberOfFPRegisters) == reg_count);
|
| test-utils-aarch64.h | 238 int reg_count,
246 int reg_count,
|
| test-assembler-aarch64.cc | [all...] |
| /external/google-breakpad/src/third_party/libdisasm/ |
| ia32_reg.c | 77 { REG_DWORD_SIZE, reg_gen | reg_count, 0, "ecx" },
87 { REG_WORD_SIZE, reg_gen | reg_count, 6, "cx" },
|
| libdis.h | 127 reg_count = 0x40000 /* array/rep/loop counter */ enumerator in enum:x86_reg_type
[all...] |
| x86_format.c | 138 {"reg_count" , 0x40000},
[all...] |
| /tools/dexter/slicer/ |
| instrumentation.cc | 106 int reg_count = 0; local
116 reg_count = 1;
122 reg_count = 1;
128 reg_count = 2;
136 auto args = code_ir->Alloc<lir::VRegRange>(reg, reg_count);
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| si_perfcounter.c | 534 unsigned reg_count = count + MIN2(count, regs->num_multi); local
535 reg_count += regs->num_prelude;
538 radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
548 reg_base -= (reg_count - 1) * 4;
549 radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
|
| /tools/dexter/dexter/ |
| experimental.cc | 235 int reg_count = 0; local
245 reg_count = 1;
251 reg_count = 1;
257 reg_count = 2;
265 auto args = code_ir.Alloc<lir::VRegRange>(reg, reg_count);
|
| /device/google/marlin/camera/QCamera2/stack/mm-camera-interface/inc/ |
| mm_camera.h | 514 /* reg_count <=0: infinite
515 * reg_count > 0: register only for required times */
516 int reg_count; member in struct:__anon2471
|
| /hardware/qcom/camera/msm8998/QCamera2/stack/mm-camera-interface/inc/ |
| mm_camera.h | 590 /* reg_count <=0: infinite
591 * reg_count > 0: register only for required times */
592 int reg_count; member in struct:__anon49276
[all...] |
| /toolchain/binutils/binutils-2.27/binutils/ |
| od-macho.c | 1711 unsigned int reg_count; local
[all...] |
| /external/v8/src/compiler/ |
| bytecode-analysis.cc | 163 uint32_t reg_count = accessor.GetRegisterCountOperand(i); local
165 for (uint32_t j = 0; j < reg_count; ++j) {
|
| /external/mesa3d/src/amd/vulkan/ |
| radv_cmd_buffer.c | 745 unsigned reg_offset = 0, reg_count = 0; local
751 ++reg_count;
757 ++reg_count;
761 radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + reg_count, 0));
772 radeon_set_context_reg_seq(cmd_buffer->cs, R_028028_DB_STENCIL_CLEAR + 4 * reg_offset, reg_count);
[all...] |
| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| brw_fs.cpp | 1673 int reg_count = 0; local
[all...] |
| brw_context.h | [all...] |
| /external/google-breakpad/src/third_party/libdisasm/swig/ |
| libdisasm_oop.i | 77 reg_dest = 0x20000, reg_count = 0x40000
|
| /device/google/marlin/camera/QCamera2/stack/mm-camera-interface/src/ |
| mm_camera.c | 482 evt_array->reg_count++;
493 evt_array->reg_count--;
[all...] |
| /hardware/qcom/camera/msm8998/QCamera2/stack/mm-camera-interface/src/ |
| mm_camera.c | 491 evt_array->reg_count++;
502 evt_array->reg_count--;
[all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.h | [all...] |
| /external/clang/lib/CodeGen/ |
| TargetInfo.cpp | [all...] |
| /external/robolectric/v1/lib/main/ |
| sqlite-jdbc-3.7.2.jar | |
