| /external/vixl/test/aarch32/traces/ |
| assembler-cond-rd-rn-operand-rm-rscs-a32.h | 38 0x0e, 0x40, 0xf5, 0xd0 // rscs le r4 r5 r14
41 0x0a, 0x50, 0xfb, 0xa0 // rscs ge r5 r11 r10
44 0x09, 0x00, 0xf9, 0x90 // rscs ls r0 r9 r9
47 0x02, 0x80, 0xf7, 0xd0 // rscs le r8 r7 r2
50 0x0d, 0x10, 0xfa, 0x00 // rscs eq r1 r10 r13
53 0x02, 0x90, 0xfc, 0xd0 // rscs le r9 r12 r2
56 0x05, 0x60, 0xf1, 0x50 // rscs pl r6 r1 r5
59 0x06, 0x10, 0xfc, 0xa0 // rscs ge r1 r12 r6
62 0x03, 0xd0, 0xfc, 0x30 // rscs cc r13 r12 r3
65 0x09, 0x20, 0xf4, 0xc0 // rscs gt r2 r4 r
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-rs-rscs-a32.h | 38 0x18, 0x80, 0xfa, 0x40 // rscs mi r8 r10 r8 LSL r0
41 0x7d, 0xb8, 0xf4, 0x30 // rscs cc r11 r4 r13 ROR r8
44 0x73, 0xd4, 0xfb, 0xe0 // rscs al r13 r11 r3 ROR r4
47 0x34, 0xbb, 0xf5, 0xc0 // rscs gt r11 r5 r4 LSR r11
50 0x78, 0xcd, 0xf0, 0x60 // rscs vs r12 r0 r8 ROR r13
53 0x15, 0xa5, 0xfc, 0x50 // rscs pl r10 r12 r5 LSL r5
56 0x12, 0xa9, 0xf2, 0x90 // rscs ls r10 r2 r2 LSL r9
59 0x39, 0xc7, 0xf7, 0x00 // rscs eq r12 r7 r9 LSR r7
62 0x70, 0x3b, 0xfd, 0x40 // rscs mi r3 r13 r0 ROR r11
65 0x59, 0x9c, 0xf0, 0xb0 // rscs lt r9 r0 r9 ASR r1
[all...] |
| assembler-cond-rd-rn-operand-const-rscs-a32.h | 38 0xff, 0x97, 0xf4, 0xd2 // rscs le r9 r4 0x03fc0000
41 0xff, 0xeb, 0xf3, 0x52 // rscs pl r14 r3 0x0003fc00
44 0xff, 0x15, 0xf6, 0x32 // rscs cc r1 r6 0x3fc00000
47 0xab, 0x57, 0xf1, 0x32 // rscs cc r5 r1 0x02ac0000
50 0xab, 0xe2, 0xf4, 0x52 // rscs pl r14 r4 0xb000000a
53 0xff, 0x2b, 0xfd, 0x22 // rscs cs r2 r13 0x0003fc00
56 0xab, 0xd5, 0xf0, 0x42 // rscs mi r13 r0 0x2ac00000
59 0xff, 0x0a, 0xf0, 0x72 // rscs vc r0 r0 0x000ff000
62 0xff, 0x2e, 0xf9, 0x62 // rscs vs r2 r9 0x00000ff0
65 0xff, 0xf0, 0xf7, 0x32 // rscs cc r15 r7 0x000000f
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to31-rscs-a32.h | 38 0x80, 0xd2, 0xfd, 0x00 // rscs eq r13 r13 r0 LSL 5
41 0x0d, 0xa5, 0xfe, 0x40 // rscs mi r10 r14 r13 LSL 10
44 0x0d, 0x62, 0xf2, 0x80 // rscs hi r6 r2 r13 LSL 4
47 0x0d, 0x31, 0xf5, 0xa0 // rscs ge r3 r5 r13 LSL 2
50 0x61, 0xa5, 0xf5, 0x30 // rscs cc r10 r5 r1 ROR 10
53 0xe7, 0x33, 0xfe, 0xa0 // rscs ge r3 r14 r7 ROR 7
56 0x87, 0xbb, 0xf1, 0x50 // rscs pl r11 r1 r7 LSL 23
59 0x84, 0x8a, 0xf6, 0xd0 // rscs le r8 r6 r4 LSL 21
62 0x82, 0x21, 0xf9, 0x10 // rscs ne r2 r9 r2 LSL 3
65 0x08, 0xe2, 0xfe, 0xa0 // rscs ge r14 r14 r8 LSL
[all...] |
| assembler-cond-rd-rn-operand-rm-shift-amount-1to32-rscs-a32.h | 38 0xc7, 0xd2, 0xf6, 0x00 // rscs eq r13 r6 r7 ASR 5
41 0x48, 0x80, 0xfb, 0x40 // rscs mi r8 r11 r8 ASR 32
44 0x4a, 0x29, 0xf3, 0x80 // rscs hi r2 r3 r10 ASR 18
47 0x2e, 0xd0, 0xf8, 0x90 // rscs ls r13 r8 r14 LSR 32
50 0xc2, 0x81, 0xf9, 0x30 // rscs cc r8 r9 r2 ASR 3
53 0x25, 0xe1, 0xf2, 0x90 // rscs ls r14 r2 r5 LSR 2
56 0xc1, 0x8f, 0xf6, 0x50 // rscs pl r8 r6 r1 ASR 31
59 0xae, 0x21, 0xf0, 0xd0 // rscs le r2 r0 r14 LSR 3
62 0xad, 0x27, 0xf0, 0x10 // rscs ne r2 r0 r13 LSR 15
65 0x23, 0x94, 0xfc, 0xa0 // rscs ge r9 r12 r3 LSR
[all...] |
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| armv1.s | 19 rscs r0, r0, r0
|
| armv1.d | 26 0+3c <[^>]*> e0f00000 ? rscs r0, r0, r0
|
| /external/vixl/test/aarch32/config/ |
| cond-rd-rn-operand-const-a32.json | 47 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1
|
| cond-rd-rn-operand-rm-a32.json | 55 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| cond-rd-rn-operand-rm-shift-amount-1to31-a32.json | 46 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| cond-rd-rn-operand-rm-shift-amount-1to32-a32.json | 46 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm> {, <shift> #<amount> } ; A1
|
| cond-rd-rn-operand-rm-shift-rs-a32.json | 44 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, <Rm>, <shift> <Rs> ; A1
|
| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | 512 COMPARE_T32(Rscs(r0, r0, 2),
522 COMPARE_T32(Rscs(r0, r1, 0x00ffffff),
529 COMPARE_T32(Rscs(r0, r0, 0x00ffffff),
538 COMPARE_T32(Rscs(r0, r1, 0xabcd2345),
547 COMPARE_T32(Rscs(r0, r0, 0xabcd2345),
556 COMPARE_T32(Rscs(r0, r1, r2),
560 COMPARE_T32(Rscs(r0, r1, r1),
564 COMPARE_T32(Rscs(r0, r0, r0),
575 COMPARE_T32(Rscs(r0, r1, Operand(r0, LSR, 2)),
583 COMPARE_T32(Rscs(r0, r0, Operand(r0, ROR, 4))
[all...] |
| test-assembler-cond-rd-rn-operand-const-a32.cc | 67 M(rscs) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-a32.cc | 67 M(rscs) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 67 M(rscs) \
[all...] |
| test-assembler-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 67 M(rscs) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | 131 M(Rscs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-a32.cc | 131 M(Rscs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 131 M(Rscs) \
[all...] |
| /external/vixl/src/aarch32/ |
| constants-aarch32.cc | 276 return "rscs";
|
| /prebuilts/vndk/v27/arm/arch-arm-armv7-a-neon/shared/vndk-core/ |
| libvixl-arm.so | |
| /prebuilts/vndk/v27/arm64/arch-arm-armv7-a-neon/shared/vndk-core/ |
| libvixl-arm.so | |
| /prebuilts/vndk/v27/x86/arch-x86-x86/shared/vndk-core/ |
| libvixl-arm.so | |
| /prebuilts/vndk/v27/x86_64/arch-x86-x86_64/shared/vndk-core/ |
| libvixl-arm.so | |
