1 // Copyright 2016, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 { 28 "mnemonics" : [ 29 "Adc", // ADC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 30 "Adcs", // ADCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 31 "Add", // ADD{<c>}{<q>} <Rd>, PC, #<const> ; A1 32 // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 33 // ADD{<c>}{<q>} {<Rd>}, SP, #<const> ; A1 34 "Adds", // ADDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 35 // ADDS{<c>}{<q>} {<Rd>}, SP, #<const> ; A1 36 "And", // AND{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 37 "Ands", // ANDS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 38 "Bic", // BIC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 39 "Bics", // BICS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 40 "Eor", // EOR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 41 "Eors", // EORS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 42 "Orr", // ORR{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 43 "Orrs", // ORRS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 44 "Rsb", // RSB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 45 "Rsbs", // RSBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 46 "Rsc", // RSC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 47 "Rscs", // RSCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 48 "Sbc", // SBC{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 49 "Sbcs", // SBCS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 50 "Sub", // SUB{<c>}{<q>} <Rd>, PC, #<const> ; A2 51 // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 52 // SUB{<c>}{<q>} {<Rd>}, SP, #<const> ; A1 53 "Subs" // SUBS{<c>}{<q>} {<Rd>}, <Rn>, #<const> ; A1 54 // SUBS{<c>}{<q>} {<Rd>}, SP, #<const> ; A1 55 ], 56 "description" : { 57 "operands": [ 58 { 59 "name": "cond", 60 "type": "Condition" 61 }, 62 { 63 "name": "rd", 64 "type": "AllRegisters" 65 }, 66 { 67 "name": "rn", 68 "type": "AllRegisters" 69 }, 70 { 71 "name": "op", 72 "wrapper": "Operand", 73 "operands": [ 74 { 75 "name": "immediate", 76 "type": "A32ModifiedImmediate" 77 } 78 ] 79 } 80 ], 81 "inputs":[ 82 { 83 "name": "apsr", 84 "type": "NZCV" 85 }, 86 { 87 "name": "rd", 88 "type": "Register" 89 }, 90 { 91 "name": "rn", 92 "type": "Register" 93 } 94 ] 95 }, 96 "test-files": [ 97 { 98 "type": "assembler", 99 "test-cases": [ 100 { 101 "name": "Operands", 102 "operands": [ 103 "cond", "rd", "rn", "immediate" 104 ], 105 "operand-limit": 500 106 } 107 ] 108 }, 109 { 110 "type": "simulator", 111 "test-cases": [ 112 { 113 "name": "Condition", 114 "operands": [ 115 "cond" 116 ], 117 "inputs": [ 118 "apsr" 119 ] 120 }, 121 { 122 "name": "RdIsRn", 123 "operands": [ 124 "rd", "rn", "immediate" 125 ], 126 "inputs": [ 127 "rd", "rn" 128 ], 129 "operand-filter": "rd == rn", 130 "operand-limit": 10, 131 "input-filter": "rd == rn" 132 }, 133 { 134 "name": "RdIsNotRn", 135 "operands": [ 136 "rd", "rn", "immediate" 137 ], 138 "inputs": [ 139 "rd", "rn" 140 ], 141 "operand-filter": "rd != rn", 142 "operand-limit": 10 143 }, 144 { 145 "name": "ModifiedImmediate", 146 "operands": [ 147 "immediate" 148 ], 149 "inputs": [ 150 "rn" 151 ] 152 } 153 ] 154 } 155 ] 156 } 157
