| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/rx/ |
| mvtcp.sm | 1 # mvtcp #{uimm2},#{simm16},${uimm16}
|
| macros.inc | 11 macro simm16 {-32768;32768}
15 macro imm {{simm8};{simm16};{simm24};{simm32}}
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/score/ |
| addi.s | 4 * (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767
7 * (1)addi rD, simm16 : rD = rD + simm16, -32768 <= simm16 <= 32767
|
| ldi.s | 3 * ldi <-> ldiu! : for ldiu! : register number must be in 0-15, simm16: [0-255]
4 * (1)ldi rD, simm16 : rD = simm16
|
| arith_32.s | 30 /* addi rD,SImm16 -> addi! rD,SImm6 */
|
| cmp_32.s | 20 /* cmpi.c rD,SImm16 -> cmpi! rD,SImm5 */
|
| load_store_32.s | 36 /* ldi rD,SImm16 -> ldiu! rD,Imm6 */
|
| /toolchain/binutils/binutils-2.27/cpu/ |
| or1korbis.cpu | 23 (dnh h-simm16 "16-bit signed immediate" ((MACH ORBIS-MACHS)) (immediate (INT 16)) () () ())
83 (df f-simm16 "simm16" ((MACH ORBIS-MACHS) SIGN-OPT) 15 16 INT #f #f)
109 (name f-simm16-split)
116 (and (sra (ifield f-simm16-split)
120 (and (ifield f-simm16-split)
123 (set (ifield f-simm16-split)
316 (name simm16)
319 (type h-simm16)
320 (index f-simm16)
[all...] |
| mep-sample-ucidsp.cpu | 35 ; uci.elfext.1 $simm16
37 ; simm16 = I[4:7]||i[20:31]
43 ; define simm16
44 (df f-uci_elfext_1-hi "uci_elfext_1 simm16 hi 4s7" (mep-ext1-isa) 4 4 INT #f #f)
45 (df f-uci_elfext_1-lo "uci_elfext_1 simm16 lo 20s31" (mep-ext1-isa) 20 12 UINT #f #f)
|
| m32r.cpu | 474 (df f-simm16 "simm16" () 16 16 INT #f #f)
681 (dshpo simm16 "16 bit signed immediate" () h-sint f-simm16)
722 (index f-simm16)
873 "addv3 $dr,$sr,$simm16"
874 (+ OP1_8 OP2_8 dr sr simm16)
876 (set dr (add sr simm16))
877 (set condbit (add-oflag sr simm16 (const 0))))
1149 "cmpi $src2,$simm16"
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| or1k-opc.c | 293 /* l.lwz $rD,${simm16}($rA) */
296 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
299 /* l.lws $rD,${simm16}($rA) */
302 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
305 /* l.lwa $rD,${simm16}($rA) */
308 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
311 /* l.lbz $rD,${simm16}($rA) */
314 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } },
317 /* l.lbs $rD,${simm16}($rA) */
320 { { MNEM, ' ', OP (RD), ',', OP (SIMM16), '(', OP (RA), ')', 0 } }
[all...] |
| or1k-opinst.c | 130 { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
138 { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
146 { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
156 { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
164 { INPUT, "simm16", HW_H_SIMM16, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 }
[all...] |
| m10200-opc.c | 125 #define SIMM16 (SIMM8+1)
129 #define SIMM16N (SIMM16+1)
204 { "mov", 0xf80000, 0xfc0000, FMT_3, {SIMM16, DN0}},
248 { "add", 0xf7180000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
251 { "add", 0xf7080000, 0xfffc0000, FMT_6, {SIMM16, AN0}},
276 { "cmp", 0xf7480000, 0xfffc0000, FMT_6, {SIMM16, DN0}},
|
| m32r-opc.c | 282 /* addv3 $dr,$sr,$simm16 */
285 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
420 /* cmpi $src2,$simm16 */
423 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
432 /* cmpui $src2,$simm16 */
435 { { MNEM, ' ', OP (SRC2), ',', OP (SIMM16), 0 } },
876 /* sll3 $dr,$sr,$simm16 */
879 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } },
894 /* sra3 $dr,$sr,$simm16 */
897 { { MNEM, ' ', OP (DR), ',', OP (SR), ',', OP (SIMM16), 0 } }
[all...] |
| or1k-desc.c | [all...] |
| m10300-opc.c | 183 #define SIMM16 (SIMM8+1)
187 #define PAREN (SIMM16+1)
539 { "mov", 0x2c0000, 0xfc0000, 0, FMT_S2, 0, {SIMM16, DN0}},
[all...] |
| m32r-desc.c | 271 { M32R_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { { { (1<<MACH_BASE), 0 } } } } },
345 /* simm16: 16 bit signed immediate */
346 { "simm16", M32R_OPERAND_SIMM16, HW_H_SINT, 16, 16,
495 /* addv3 $dr,$sr,$simm16 */
610 /* cmpi $src2,$simm16 */
620 /* cmpui $src2,$simm16 */
[all...] |
| m32r-opinst.c | 88 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
187 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
416 { INPUT, "simm16", HW_H_SINT, CGEN_MODE_INT, OP_ENT (SIMM16), 0, 0 },
[all...] |
| /external/llvm/test/CodeGen/AMDGPU/ |
| llvm.amdgcn.s.getreg.ll | 7 define void @s_getreg_test(i32 addrspace(1)* %out) { ; simm16=45574 for lds size.
|
| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.cpp | 796 const unsigned SImm16 = MI->getOperand(OpNo).getImm();
797 const unsigned Id = SImm16 & ID_MASK_;
800 if ((SImm16 & ~ID_MASK_) != 0) // Unused/unknown bits must be 0.
806 if ((SImm16 & ~(ID_MASK_|OP_GS_MASK_|STREAM_ID_MASK_)) != 0) // Unused/unknown bits must be 0.
808 const unsigned OpGs = (SImm16 & OP_GS_MASK_) >> OP_SHIFT_;
809 const unsigned StreamId = (SImm16 & STREAM_ID_MASK_) >> STREAM_ID_SHIFT_;
820 if ((SImm16 & ~(ID_MASK_|OP_SYS_MASK_)) != 0) // Unused/unknown bits must be 0.
822 const unsigned OpSys = (SImm16 & OP_SYS_MASK_) >> OP_SHIFT_;
829 O << SImm16; // Unknown simm16 code
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIInstructions.td | 399 (ins SReg_64:$sdst, u16imm:$simm16), " $sdst, $simm16"
405 (ins hwreg:$simm16), " $sdst, $simm16"
411 (ins SReg_32:$sdst, hwreg:$simm16), " $simm16, $sdst"
417 (ins i32imm:$imm, hwreg:$simm16), " $simm16, $imm"
424 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
[all...] |
| SIInstrFormats.td | 215 bits <16> simm16;
217 let Inst{15-0} = simm16;
225 bits <16> simm16;
228 let Inst{15-0} = simm16;
237 bits <16> simm16;
239 let Inst{15-0} = simm16;
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeInstrInfo.td | 84 def simm16 : Operand<i32>;
103 let MIOperandInfo = (ops GPR, simm16);
147 def ADJCALLSTACKDOWN : MBlazePseudo<(outs), (ins simm16:$amt),
151 (ins uimm16:$amt1, simm16:$amt2),
413 def ADDIK : ArithI<0x0C, "addik ", add, simm16, immSExt16>;
414 def RSUBIK : ArithRI<0x0D, "rsubik ", sub, simm16, immSExt16>;
421 def ADDI : ArithI<0x08, "addi ", addc, simm16, immSExt16>;
422 def RSUBI : ArithRI<0x09, "rsubi ", subc, simm16, immSExt16>;
425 def ADDIC : ArithI<0x0A, "addic ", adde, simm16, immSExt16>;
426 def RSUBIC : ArithRI<0x0B, "rsubic ", sube, simm16, immSExt16>
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.td | 24 let MIOperandInfo = (ops CPU16Regs, simm16);
36 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
42 let MIOperandInfo = (ops CPU16RegsPlusSP, simm16);
65 FI816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
83 FRI16<op, (outs CPU16Regs:$rx), (ins simm16:$imm),
97 FRI16<op, (outs), (ins CPU16Regs:$rx, simm16:$imm),
106 FRI16<_op, (outs CPU16Regs:$rx), (ins CPU16Regs:$rx_, simm16:$imm),
122 MipsPseudo16<(outs CPU16Regs:$cc), (ins CPU16Regs:$rx, simm16:$imm),
161 FEXT_I816<_func, (outs), (ins simm16:$imm), !strconcat(asmstr, asmstr2),
194 FEXT_RI16<_op, (outs CPU16Regs:$rx), (ins simm16:$imm)
[all...] |
| /external/valgrind/VEX/priv/ |
| guest_ppc_toIR.c | 4979 Long simm16 = extend_s_16to64(uimm16); local
7132 Int simm16 = extend_s_16to32(uimm16); local
7430 Int simm16 = extend_s_16to32(uimm16); local
7652 Int simm16 = extend_s_16to32(uimm16); local
8409 ULong simm16 = extend_s_16to64(uimm16); local
10088 Int simm16 = extend_s_16to32(uimm16); local
10226 Int simm16 = extend_s_16to32(uimm16); local
11469 Int simm16 = extend_s_16to32(uimm16); local
[all...] |
