| /art/runtime/interpreter/mterp/mips/ |
| op_add_long.S | 6 * sltu v1,v0,a2
9 %include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "preinstr":"addu v0, a2, a0", "instr":"addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1" }
|
| op_sub_long.S | 5 * sltu a0,a0,v0
8 %include "mips/binopWide.S" { "result0":"v0", "result1":"v1", "preinstr":"subu v0, a0, a2", "instr":"subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0" }
|
| op_add_long_2addr.S | 4 %include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "preinstr":"addu v0, a2, a0", "instr":"addu a1, a3, a1; sltu v1, v0, a2; addu v1, v1, a1" }
|
| op_neg_long.S | 1 %include "mips/unopWide.S" {"result0":"v0", "result1":"v1", "preinstr":"negu v0, a0", "instr":"negu v1, a1; sltu a0, zero, v0; subu v1, v1, a0"}
|
| op_sub_long_2addr.S | 4 %include "mips/binopWide2addr.S" { "result0":"v0", "result1":"v1", "preinstr":"subu v0, a0, a2", "instr":"subu v1, a1, a3; sltu a0, a0, v0; subu v1, v1, a0" }
|
| /external/llvm/test/CodeGen/Mips/ |
| 2008-06-05-Carry.ll | 6 ; CHECK: sltu
17 ; CHECK: sltu
|
| llcarry.ll | 17 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
30 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
43 ; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/mips/ |
| bgeu.d | 10 [0-9a-f]+ <[^>]*> sltu at,a0,a1
21 [0-9a-f]+ <[^>]*> sltu at,a0,at
28 [0-9a-f]+ <[^>]*> sltu at,a0,at
33 [0-9a-f]+ <[^>]*> sltu at,a0,at
36 [0-9a-f]+ <[^>]*> sltu at,a1,a0
43 [0-9a-f]+ <[^>]*> sltu at,a0,a1
47 [0-9a-f]+ <[^>]*> sltu at,a1,a0
|
| bltu.d | 10 [0-9a-f]+ <[^>]*> sltu at,a0,a1
21 [0-9a-f]+ <[^>]*> sltu at,a0,at
28 [0-9a-f]+ <[^>]*> sltu at,a0,at
33 [0-9a-f]+ <[^>]*> sltu at,a0,at
36 [0-9a-f]+ <[^>]*> sltu at,a1,a0
43 [0-9a-f]+ <[^>]*> sltu at,a0,a1
47 [0-9a-f]+ <[^>]*> sltu at,a1,a0
|
| mipsr6@bgeu.d | 11 [0-9a-f]+ <[^>]*> sltu at,a0,a1
26 [0-9a-f]+ <[^>]*> sltu at,a0,at
35 [0-9a-f]+ <[^>]*> sltu at,a0,at
41 [0-9a-f]+ <[^>]*> sltu at,a0,at
45 [0-9a-f]+ <[^>]*> sltu at,a1,a0
55 [0-9a-f]+ <[^>]*> sltu at,a0,a1
59 [0-9a-f]+ <[^>]*> sltu at,a1,a0
|
| mipsr6@bltu.d | 11 [0-9a-f]+ <[^>]*> sltu at,a0,a1
26 [0-9a-f]+ <[^>]*> sltu at,a0,at
35 [0-9a-f]+ <[^>]*> sltu at,a0,at
41 [0-9a-f]+ <[^>]*> sltu at,a0,at
45 [0-9a-f]+ <[^>]*> sltu at,a1,a0
55 [0-9a-f]+ <[^>]*> sltu at,a0,a1
59 [0-9a-f]+ <[^>]*> sltu at,a1,a0
|
| micromips-warn-branch-delay.s | 16 sltu $17,$31,$0
|
| branch-likely.d | 34 [0-9a-f]+ <[^>]*> sltu at,a0,a1
37 [0-9a-f]+ <[^>]*> sltu at,a1,a0
40 [0-9a-f]+ <[^>]*> sltu at,a0,a1
44 [0-9a-f]+ <[^>]*> sltu at,a1,a0
62 [0-9a-f]+ <[^>]*> sltu at,a0,a1
65 [0-9a-f]+ <[^>]*> sltu at,a1,a0
68 [0-9a-f]+ <[^>]*> sltu at,a0,a1
72 [0-9a-f]+ <[^>]*> sltu at,a1,a0
|
| micromips@branch-likely.d | 39 [0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
43 [0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
47 [0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
51 [0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
71 [0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
75 [0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
79 [0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
83 [0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
|
| micromips@bgeu.d | 11 [0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
26 [0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
35 [0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
41 [0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
45 [0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
55 [0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
59 [0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
|
| micromips@bltu.d | 11 [0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
26 [0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
35 [0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
41 [0-9a-f]+ <[^>]*> 0024 0b90 sltu at,a0,at
45 [0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
55 [0-9a-f]+ <[^>]*> 00a4 0b90 sltu at,a0,a1
59 [0-9a-f]+ <[^>]*> 0085 0b90 sltu at,a1,a0
|
| mips16.s | 150 sltu $2,0
151 sltu $2,1
152 sltu $2,-1
153 sltu $2,255
154 sltu $2,256
155 sltu $2,$3
|
| /external/llvm/test/MC/Mips/ |
| macro-bcc-imm.s | 23 # ALL: sltu $1, $6, $1
27 # ALL: sltu $1, $1, $6
31 # ALL: sltu $1, $6, $1
35 # ALL: sltu $1, $1, $6
55 # ALL: sltu $1, $6, $1
59 # ALL: sltu $1, $1, $6
63 # ALL: sltu $1, $6, $1
67 # ALL: sltu $1, $1, $6
|
| mips_gprel16.s | 33 sltu $2, $zero, $1
57 sltu $2, $zero, $1
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| add.ll | 108 ; GP32: sltu $[[T0:[0-9]+]], $3, $7
115 ; MM32: sltu $[[T0:[0-9]+]], $3, $7
131 ; GP32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
137 ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]]
140 ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]]
147 ; GP64: sltu $[[T0:[0-9]+]], $3, $7
153 ; MM32: sltu $[[T2:[0-9]+]], $[[T1]], $[[T0]]
157 ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]]
162 ; MM32: sltu $[[T11:[0-9]+]], $[[T9]], $[[T7]]
169 ; MM64: sltu $[[T0:[0-9]+]], $3, $
[all...] |
| sub.ll | 103 ; GP32: sltu $[[T0:[0-9]+]], $5, $7
118 ; GP32-NOT-MM: sltu $[[T1:[0-9]+]], $5, $[[T0]]
125 ; GP32-NOT-MM: sltu $[[T8:[0-9]+]], $6, $[[T4]]
128 ; GP32-NOT-MM: sltu $[[T10:[0-9]+]], $7, $[[T5]]
134 ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]]
141 ; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]]
144 ; GP32-MM: sltu $[[T2]], $7, $[[T4]]
150 ; GP64: sltu $[[T0:[0-9]+]], $5, $7
|
| /external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/ |
| cond-branch.ll | 45 ; MIPS32-OM1: sltu {{.*}}, $zero, {{.*}}
129 ; MIPS32: sltu
132 ; MIPS32-OM1: sltu
146 ; MIPS32: sltu
149 ; MIPS32-OM1: sltu
164 ; MIPS32: sltu
167 ; MIPS32-OM1: sltu
181 ; MIPS32: sltu
184 ; MIPS32-OM1: sltu
|
| icmp.ll | 32 ; MIPS32: sltu {{.*}}, $zero, {{.*}}
50 ; MIPS32: sltu
69 ; MIPS32: sltu
88 ; MIPS32: sltu
107 ; MIPS32: sltu
148 ; MIPS32: sltu
174 ; MIPS32: sltu
|
| vector-icmp.ll | 96 ; MIPS32: sltu [[T4]],zero,[[T4]]
98 ; MIPS32: sltu [[T5]],zero,[[T5]]
100 ; MIPS32: sltu [[T6]],zero,[[T6]]
102 ; MIPS32: sltu [[T7]],zero,[[T7]]
189 ; MIPS32: sltu [[T4:.*]],a0,[[T0]]
191 ; MIPS32: sltu [[T5:.*]],a1,[[T1]]
193 ; MIPS32: sltu [[T6:.*]],a2,[[T2]]
195 ; MIPS32: sltu [[T7:.*]],a3,[[T3]]
216 ; MIPS32: sltu v0,[[T0]],[[T4:.*]]
217 ; MIPS32: sltu v1,[[T1]],[[T5:.*]
[all...] |
| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| sel1.ll | 10 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
27 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
44 ; CHECK-NEXT: sltu $[[T3:[0-9]+]], $zero, $[[T2]]
59 ; CHECK-NEXT: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
75 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
91 ; CHECK: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
|
